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axi_ad9680: register map changes

main
Rejeesh Kutty 2014-07-02 12:50:09 -04:00
parent 31abd07613
commit e4ce00f7fb
4 changed files with 82 additions and 171 deletions
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161
library/axi_ad9680/axi_ad9680.v
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@ -50,9 +50,12 @@ module axi_ad9680 (
// dma interface // dma interface
adc_clk, adc_clk,
adc_dwr, adc_enable_0,
adc_ddata, adc_valid_0,
adc_dsync, adc_data_0,
adc_enable_1,
adc_valid_1,
adc_data_1,
adc_dovf, adc_dovf,
adc_dunf, adc_dunf,
@ -76,19 +79,14 @@ module axi_ad9680 (
s_axi_rvalid, s_axi_rvalid,
s_axi_rresp, s_axi_rresp,
s_axi_rdata, s_axi_rdata,
s_axi_rready, s_axi_rready);
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff; parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff; parameter C_HIGHADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000; parameter C_BASEADDR = 32'h00000000;
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
@ -99,9 +97,12 @@ module axi_ad9680 (
// dma interface // dma interface
output adc_clk; output adc_clk;
output adc_dwr; output adc_enable_0;
output [127:0] adc_ddata; output adc_valid_0;
output adc_dsync; output [63:0] adc_data_0;
output adc_enable_1;
output adc_valid_1;
output [63:0] adc_data_1;
input adc_dovf; input adc_dovf;
input adc_dunf; input adc_dunf;
@ -127,20 +128,11 @@ module axi_ad9680 (
output [31:0] s_axi_rdata; output [31:0] s_axi_rdata;
input s_axi_rready; input s_axi_rready;
// debug signals
output adc_mon_valid;
output [239:0] adc_mon_data;
// internal registers // internal registers
reg adc_data_cnt = 'd0; reg up_status_pn_err = 'd0;
reg adc_dsync = 'd0; reg up_status_pn_oos = 'd0;
reg adc_dwr = 'd0; reg up_status_or = 'd0;
reg [127:0] adc_ddata = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0; reg up_ack = 'd0;
@ -157,22 +149,11 @@ module axi_ad9680 (
wire adc_or_a_s; wire adc_or_a_s;
wire adc_or_b_s; wire adc_or_b_s;
wire adc_status_s; wire adc_status_s;
wire adc_enable_a_s; wire [ 1:0] up_adc_pn_err_s;
wire [63:0] adc_channel_data_a_s; wire [ 1:0] up_adc_pn_oos_s;
wire adc_enable_b_s; wire [ 1:0] up_adc_or_s;
wire [63:0] adc_channel_data_b_s; wire [31:0] up_rdata_s[0:2];
wire up_adc_pn_err_a_s; wire up_ack_s[0:2];
wire up_adc_pn_oos_a_s;
wire up_adc_or_a_s;
wire [31:0] up_adc_channel_rdata_a_s;
wire up_adc_channel_ack_a_s;
wire up_adc_pn_err_b_s;
wire up_adc_pn_oos_b_s;
wire up_adc_or_b_s;
wire [31:0] up_adc_channel_rdata_b_s;
wire up_adc_channel_ack_b_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire up_sel_s; wire up_sel_s;
wire up_wr_s; wire up_wr_s;
wire [13:0] up_addr_s; wire [13:0] up_addr_s;
@ -183,60 +164,26 @@ module axi_ad9680 (
assign up_clk = s_axi_aclk; assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn; assign up_rstn = s_axi_aresetn;
// monitor signals // defaults
assign adc_mon_valid = 1'b1; assign adc_valid_0 = 1'b1;
assign adc_mon_data[ 63: 0] = adc_channel_data_a_s; assign adc_valid_1 = 1'b1;
assign adc_mon_data[127: 64] = adc_channel_data_b_s;
assign adc_mon_data[183:128] = adc_data_a_s;
assign adc_mon_data[239:184] = adc_data_b_s;
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_b_s, adc_enable_a_s})
2'b11: begin // both I and Q
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= {adc_channel_data_b_s[63:48], adc_channel_data_a_s[63:48],
adc_channel_data_b_s[47:32], adc_channel_data_a_s[47:32],
adc_channel_data_b_s[31:16], adc_channel_data_a_s[31:16],
adc_channel_data_b_s[15: 0], adc_channel_data_a_s[15: 0]};
end
2'b10: begin // Q only
adc_dsync <= 1'b1;
adc_dwr <= adc_data_cnt;
adc_ddata <= {adc_channel_data_b_s, adc_ddata[127:64]};
end
2'b01: begin // I only
adc_dsync <= 1'b1;
adc_dwr <= adc_data_cnt;
adc_ddata <= {adc_channel_data_a_s, adc_ddata[127:64]};
end
default: begin // no channels
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= {8{16'hdead}};
end
endcase
end
// processor read interface // processor read interface
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0; up_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0; up_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0; up_status_or <= 'd0;
up_rdata <= 'd0; up_rdata <= 'd0;
up_ack <= 'd0; up_ack <= 'd0;
end else begin end else begin
up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s; up_status_pn_err <= | up_adc_pn_err_s;
up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s; up_status_pn_oos <= | up_adc_pn_oos_s;
up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s; up_status_or <= | up_adc_or_s;
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s; up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s; up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
end end
end end
@ -260,19 +207,19 @@ module axi_ad9680 (
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_data (adc_data_a_s), .adc_data (adc_data_a_s),
.adc_or (adc_or_a_s), .adc_or (adc_or_a_s),
.adc_dfmt_data (adc_channel_data_a_s), .adc_dfmt_data (adc_data_0),
.adc_enable (adc_enable_a_s), .adc_enable (adc_enable_0),
.up_adc_pn_err (up_adc_pn_err_a_s), .up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_a_s), .up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_a_s), .up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_sel (up_sel_s),
.up_wr (up_wr_s), .up_wr (up_wr_s),
.up_addr (up_addr_s), .up_addr (up_addr_s),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_a_s), .up_rdata (up_rdata_s[0]),
.up_ack (up_adc_channel_ack_a_s)); .up_ack (up_ack_s[0]));
// channel // channel
@ -281,19 +228,19 @@ module axi_ad9680 (
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_data (adc_data_b_s), .adc_data (adc_data_b_s),
.adc_or (adc_or_b_s), .adc_or (adc_or_b_s),
.adc_dfmt_data (adc_channel_data_b_s), .adc_dfmt_data (adc_data_1),
.adc_enable (adc_enable_b_s), .adc_enable (adc_enable_1),
.up_adc_pn_err (up_adc_pn_err_b_s), .up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_b_s), .up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_b_s), .up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_sel (up_sel_s),
.up_wr (up_wr_s), .up_wr (up_wr_s),
.up_addr (up_addr_s), .up_addr (up_addr_s),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_b_s), .up_rdata (up_rdata_s[1]),
.up_ack (up_adc_channel_ack_b_s)); .up_ack (up_ack_s[1]));
// common processor control // common processor control
@ -305,12 +252,12 @@ module axi_ad9680 (
.adc_ddr_edgesel (), .adc_ddr_edgesel (),
.adc_pin_mode (), .adc_pin_mode (),
.adc_status (adc_status_s), .adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_status_ovf (adc_dovf), .adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf), .adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd40), .adc_clk_ratio (32'd40),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0), .delay_clk (1'b0),
.delay_rst (), .delay_rst (),
.delay_sel (), .delay_sel (),
@ -331,14 +278,16 @@ module axi_ad9680 (
.drp_locked (1'd1), .drp_locked (1'd1),
.up_usr_chanmax (), .up_usr_chanmax (),
.adc_usr_chanmax (8'd1), .adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_sel (up_sel_s),
.up_wr (up_wr_s), .up_wr (up_wr_s),
.up_addr (up_addr_s), .up_addr (up_addr_s),
.up_wdata (up_wdata_s), .up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s), .up_rdata (up_rdata_s[2]),
.up_ack (up_adc_common_ack_s)); .up_ack (up_ack_s[2]));
// up bus interface // up bus interface

8
library/axi_ad9680/axi_ad9680_channel.v
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@ -103,10 +103,10 @@ module axi_ad9680_channel (
wire adc_pn_oos_s; wire adc_pn_oos_s;
wire adc_pn_err_s; wire adc_pn_err_s;
wire adc_pn_type_s;
wire adc_dfmt_enable_s; wire adc_dfmt_enable_s;
wire adc_dfmt_type_s; wire adc_dfmt_type_s;
wire adc_dfmt_se_s; wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations // instantiations
@ -115,7 +115,7 @@ module axi_ad9680_channel (
.adc_data (adc_data), .adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s), .adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s), .adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s)); .adc_pnseq_sel (adc_pnseq_sel_s));
genvar n; genvar n;
generate generate
@ -136,17 +136,17 @@ module axi_ad9680_channel (
.adc_clk (adc_clk), .adc_clk (adc_clk),
.adc_rst (adc_rst), .adc_rst (adc_rst),
.adc_enable (adc_enable), .adc_enable (adc_enable),
.adc_pn_sel (),
.adc_iqcor_enb (), .adc_iqcor_enb (),
.adc_dcfilt_enb (), .adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s), .adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s), .adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s), .adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (), .adc_dcfilt_offset (),
.adc_dcfilt_coeff (), .adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (), .adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (), .adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s), .adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s), .adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or), .adc_or (adc_or),

1
library/axi_ad9680/axi_ad9680_ip.tcl
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@ -6,6 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9680 adi_ip_create axi_ad9680
adi_ip_files axi_ad9680 [list \ adi_ip_files axi_ad9680 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \

83
library/axi_ad9680/axi_ad9680_pnmon.v
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@ -54,7 +54,7 @@ module axi_ad9680_pnmon (
// processor interface PN9 (0x0), PN23 (0x1) // processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type); adc_pnseq_sel);
// adc interface // adc interface
@ -68,28 +68,16 @@ module axi_ad9680_pnmon (
// processor interface PN9 (0x0), PN23 (0x1) // processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type; input [ 3:0] adc_pnseq_sel;
// internal registers // internal registers
reg [55:0] adc_pn_data = 'd0; reg [55:0] adc_pn_data_in = 'd0;
reg adc_pn_match_d_1 = 'd0; reg [55:0] adc_pn_data_pn = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals // internal signals
wire [55:0] adc_pn_data_in_s; wire [55:0] adc_pn_data_pn_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [55:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function // PN23 function
@ -223,58 +211,31 @@ module axi_ad9680_pnmon (
end end
endfunction endfunction
// pn sequence checking algorithm is commonly used in most applications. // pn sequence select
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_in_s = { ~adc_data[13], adc_data[12: 0], assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
~adc_data[27], adc_data[26:14],
~adc_data[41], adc_data[40:28],
~adc_data[55], adc_data[54:42]};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[55:28] == adc_pn_data[55:28]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[27: 0] == adc_pn_data[27: 0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 56'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
if (adc_pn_type == 1'b0) begin adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0],
adc_pn_data <= pn9(adc_pn_data_s); ~adc_data[27], adc_data[26:14],
~adc_data[41], adc_data[40:28],
~adc_data[55], adc_data[54:42]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin end else begin
adc_pn_data <= pn23(adc_pn_data_s); adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end end
end end
// pn oos and counters (64 to clear and set). // pn oos & pn err
always @(posedge adc_clk) begin ad_pnmon #(.DATA_WIDTH(56)) i_pnmon (
adc_pn_match_d_1 <= adc_pn_match_d_1_s; .adc_clk (adc_clk),
adc_pn_match_d_0 <= adc_pn_match_d_0_s; .adc_valid_in (1'b1),
adc_pn_match_z <= adc_pn_match_z_s; .adc_data_in (adc_pn_data_in),
adc_pn_err <= adc_pn_err_s; .adc_data_pn (adc_pn_data_pn),
if (adc_pn_update_s == 1'b1) begin .adc_pn_oos (adc_pn_oos),
if (adc_pn_oos_count >= 16) begin .adc_pn_err (adc_pn_err));
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
endmodule endmodule