ad9671_fmc: removed
Rejeesh Kutty
parent
73680d1ed9
commit
e520f5c55a
File diff suppressed because one or more lines are too long
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@ -1,29 +0,0 @@
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create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
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create_clock -period "12.500 ns" -name n_clk_ref [get_ports {ref_clk}]
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create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
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create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
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set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
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set_clock_groups -asynchronous -group [get_clocks {n_clk_ref} ]
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set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
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set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
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set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
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set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
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set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
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set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
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set_false_path -from {sys_resetn} -to *
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set_false_path -from * -to {sys_resetn}
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@ -1,85 +0,0 @@
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load_package flow
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source ../../scripts/adi_env.tcl
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project_new ad9671_fmc_a5gt -overwrite
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source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
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set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
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set_global_assignment -name VERILOG_FILE ../common/ad9671_fmc_spi.v
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# reference clock
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set_location_assignment PIN_AB9 -to ref_clk
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set_location_assignment PIN_AB8 -to "ref_clk(n)"
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk
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set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk
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# lane data
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set_location_assignment PIN_R1 -to rx_data[0]
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set_location_assignment PIN_R2 -to "rx_data[0](n)"
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set_location_assignment PIN_U1 -to rx_data[1]
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set_location_assignment PIN_U2 -to "rx_data[1](n)"
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0]
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set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1]
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0]
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set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1]
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# jesd signals
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set_location_assignment PIN_AL8 -to rx_sync
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set_location_assignment PIN_AK8 -to "rx_sync(n)"
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
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set_location_assignment PIN_AP7 -to rx_sysref
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set_location_assignment PIN_AN7 -to "rx_sysref(n)"
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
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# spi
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set_location_assignment PIN_AT15 -to spi_ad9671_csn
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set_location_assignment PIN_AH17 -to spi_ad9671_clk
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set_location_assignment PIN_AG17 -to spi_ad9671_sdio
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set_location_assignment PIN_AW15 -to spi_ad9516_csn
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set_location_assignment PIN_AP9 -to spi_ad9516_clk
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set_location_assignment PIN_AN9 -to spi_ad9516_sdio
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set_location_assignment PIN_AW14 -to spi_ad9553_csn
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set_location_assignment PIN_AU15 -to spi_ad9553_clk
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set_location_assignment PIN_AT6 -to spi_ad9553_sdio
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9671_csn
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9671_clk
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9671_sdio
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9516_csn
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9516_clk
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9516_sdio
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9553_csn
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9553_clk
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set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_ad9553_sdio
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# gpio
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set_location_assignment PIN_AK16 -to reset_ad9516
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set_location_assignment PIN_AG23 -to reset_ad9671
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set_location_assignment PIN_AK15 -to trig
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set_location_assignment PIN_AU13 -to prci_sck
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set_location_assignment PIN_AV6 -to prci_cnv
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set_location_assignment PIN_AD16 -to prci_sdo
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set_location_assignment PIN_AT13 -to prcq_sck
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set_location_assignment PIN_AV7 -to prcq_cnv
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set_location_assignment PIN_AC16 -to prcq_sdo
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set_instance_assignment -name IO_STANDARD "2.5 V" -to reset_ad9516
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set_instance_assignment -name IO_STANDARD "2.5 V" -to reset_ad9671
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set_instance_assignment -name IO_STANDARD "2.5 V" -to trig
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set_instance_assignment -name IO_STANDARD "2.5 V" -to prci_sck
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set_instance_assignment -name IO_STANDARD "2.5 V" -to prci_cnv
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set_instance_assignment -name IO_STANDARD "2.5 V" -to prci_sdo
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set_instance_assignment -name IO_STANDARD "2.5 V" -to prcq_sck
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set_instance_assignment -name IO_STANDARD "2.5 V" -to prcq_cnv
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set_instance_assignment -name IO_STANDARD "2.5 V" -to prcq_sdo
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execute_flow -compile
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@ -1,16 +0,0 @@
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set worst_path [get_timing_paths -npaths 1 -setup]
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foreach_in_collection path $worst_path {
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set slack [get_path_info $path -slack]
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}
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if {$slack > 0} {
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set worst_path [get_timing_paths -npaths 1 -hold]
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foreach_in_collection path $worst_path {
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set slack [get_path_info $path -slack]
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}
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}
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if {$slack < 0} {
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use_this_invalid_command_to_crash
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}
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@ -1,437 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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sys_clk,
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sys_resetn,
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// ddr3
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ddr3_a,
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ddr3_ba,
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ddr3_clk_p,
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ddr3_clk_n,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_we_n,
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ddr3_reset_n,
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ddr3_dq,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_odt,
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ddr3_rzq,
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// ethernet
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eth_rx_clk,
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eth_rx_data,
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eth_rx_cntrl,
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eth_tx_clk_out,
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eth_tx_data,
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eth_tx_cntrl,
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eth_mdc,
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eth_mdio_i,
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eth_mdio_o,
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eth_mdio_t,
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// board gpio
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led_grn,
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led_red,
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push_buttons,
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dip_switches,
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// lane interface
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ref_clk,
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rx_data,
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rx_sync,
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rx_sysref,
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// spi
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spi_ad9671_csn,
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spi_ad9671_clk,
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spi_ad9671_sdio,
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spi_ad9516_csn,
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spi_ad9516_clk,
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spi_ad9516_sdio,
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spi_ad9553_csn,
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spi_ad9553_clk,
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spi_ad9553_sdio,
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// gpio
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reset_ad9516,
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reset_ad9671,
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trig,
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prci_sck,
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prci_cnv,
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prci_sdo,
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prcq_sck,
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prcq_cnv,
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prcq_sdo);
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// clock and resets
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input sys_clk;
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input sys_resetn;
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// ddr3
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output [ 13:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_clk_p;
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output ddr3_clk_n;
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output ddr3_cke;
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output ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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output ddr3_ras_n;
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output ddr3_cas_n;
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output ddr3_we_n;
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output ddr3_reset_n;
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inout [ 63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_p;
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inout [ 7:0] ddr3_dqs_n;
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output ddr3_odt;
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input ddr3_rzq;
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// ethernet
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input eth_rx_clk;
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input [ 3:0] eth_rx_data;
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input eth_rx_cntrl;
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output eth_tx_clk_out;
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output [ 3:0] eth_tx_data;
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output eth_tx_cntrl;
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output eth_mdc;
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input eth_mdio_i;
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output eth_mdio_o;
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output eth_mdio_t;
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// board gpio
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output [ 7:0] led_grn;
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output [ 7:0] led_red;
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input [ 2:0] push_buttons;
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input [ 7:0] dip_switches;
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// lane interface
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input ref_clk;
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input [ 1:0] rx_data;
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output rx_sync;
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output rx_sysref;
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// spi
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output spi_ad9671_csn;
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output spi_ad9671_clk;
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inout spi_ad9671_sdio;
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output spi_ad9516_csn;
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output spi_ad9516_clk;
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inout spi_ad9516_sdio;
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output spi_ad9553_csn;
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output spi_ad9553_clk;
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inout spi_ad9553_sdio;
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// gpio
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output reset_ad9516;
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output reset_ad9671;
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output trig;
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output prci_sck;
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output prci_cnv;
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input prci_sdo;
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output prcq_sck;
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output prcq_cnv;
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input prcq_sdo;
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// internal registers
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reg rx_sysref_m1 = 'd0;
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reg rx_sysref_m2 = 'd0;
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reg rx_sysref_m3 = 'd0;
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reg rx_sysref = 'd0;
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reg rx_sof_0 = 'd0;
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// internal clocks and resets
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wire sys_125m_clk;
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wire sys_25m_clk;
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wire sys_2m5_clk;
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wire eth_tx_clk;
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wire rx_clk;
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wire adc_clk;
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// internal registers
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reg dma_sync = 'd0;
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reg dma_wr = 'd0;
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reg [127:0] dma_data = 'd0;
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// internal signals
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wire sys_pll_locked_s;
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wire eth_tx_reset_s;
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wire eth_tx_mode_1g_s;
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wire eth_tx_mode_10m_100m_n_s;
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wire [ 2:0] spi_csn_s;
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wire spi_clk_s;
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wire spi_mosi_s;
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wire spi_miso_s;
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wire [ 7:0] adc_valid_s;
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wire [ 7:0] adc_enable_s;
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wire [127:0] adc_data_s;
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wire adc_dovf_s;
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wire [ 3:0] rx_ip_sof_s;
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wire [ 63:0] rx_ip_data_s;
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wire [ 63:0] rx_data_s;
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wire rx_sw_rstn_s;
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wire rx_sysref_s;
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wire rx_err_s;
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wire rx_ready_s;
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wire [ 3:0] rx_rst_state_s;
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wire rx_lane_aligned_s;
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wire [ 1:0] rx_analog_reset_s;
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wire [ 1:0] rx_digital_reset_s;
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wire [ 1:0] rx_cdr_locked_s;
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wire [ 1:0] rx_cal_busy_s;
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wire rx_pll_locked_s;
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wire [ 15:0] rx_xcvr_status_s;
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wire [ 1:0] rx_data_sof;
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// ethernet transmit clock
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assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
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(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
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altddio_out #(.width(1)) i_eth_tx_clk_out (
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.aset (1'b0),
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.sset (1'b0),
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.sclr (1'b0),
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.oe (1'b1),
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.oe_out (),
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.datain_h (1'b1),
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.datain_l (1'b0),
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.outclocken (1'b1),
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.aclr (eth_tx_reset_s),
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.outclock (eth_tx_clk),
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.dataout (eth_tx_clk_out));
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assign eth_tx_reset_s = ~sys_pll_locked_s;
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always @(posedge adc_clk) begin
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dma_sync <= 1'b1;
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dma_wr <= | adc_enable_s;
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dma_data <= adc_data_s;
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end
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always @(posedge rx_clk) begin
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rx_sysref_m1 <= rx_sysref_s;
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rx_sysref_m2 <= rx_sysref_m1;
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rx_sysref_m3 <= rx_sysref_m2;
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rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
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end
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sld_signaltap #(
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.sld_advanced_trigger_entity ("basic,1,"),
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.sld_data_bits (130),
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.sld_data_bit_cntr_bits (8),
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.sld_enable_advanced_trigger (0),
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.sld_mem_address_bits (10),
|
||||
.sld_node_crc_bits (32),
|
||||
.sld_node_crc_hiword (10311),
|
||||
.sld_node_crc_loword (14297),
|
||||
.sld_node_info (1076736),
|
||||
.sld_ram_block_type ("AUTO"),
|
||||
.sld_sample_depth (1024),
|
||||
.sld_storage_qualifier_gap_record (0),
|
||||
.sld_storage_qualifier_mode ("OFF"),
|
||||
.sld_trigger_bits (2),
|
||||
.sld_trigger_in_enabled (0),
|
||||
.sld_trigger_level (1),
|
||||
.sld_trigger_level_pipeline (1))
|
||||
i_signaltap (
|
||||
.acq_clk (rx_clk),
|
||||
.acq_data_in ({rx_sysref, rx_sync, rx_ip_data_s}),
|
||||
.acq_trigger_in ({rx_sysref, rx_sync}));
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 2; n = n + 1) begin: g_align_1
|
||||
ad_jesd_align i_jesd_align (
|
||||
.rx_clk (rx_clk),
|
||||
.rx_sof (rx_ip_sof_s),
|
||||
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
|
||||
.rx_data_sof(rx_data_sof[n]),
|
||||
.rx_data (rx_data_s[n*32+31:n*32]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(rx_clk)
|
||||
begin
|
||||
rx_sof_0 <= |rx_data_sof ;
|
||||
end
|
||||
|
||||
assign rx_xcvr_status_s[15:11] = 5'd0;
|
||||
assign rx_xcvr_status_s[10:10] = rx_sync;
|
||||
assign rx_xcvr_status_s[ 9: 9] = rx_ready_s;
|
||||
assign rx_xcvr_status_s[ 8: 8] = rx_pll_locked_s;
|
||||
assign rx_xcvr_status_s[ 7: 4] = rx_rst_state_s;
|
||||
assign rx_xcvr_status_s[ 3: 2] = rx_cdr_locked_s;
|
||||
assign rx_xcvr_status_s[ 1: 0] = rx_cal_busy_s;
|
||||
|
||||
ad_xcvr_rx_rst #(.NUM_OF_LANES (2)) i_xcvr_rx_rst (
|
||||
.rx_clk (rx_clk),
|
||||
.rx_rstn (sys_resetn),
|
||||
.rx_sw_rstn (rx_sw_rstn_s),
|
||||
.rx_pll_locked (rx_pll_locked_s),
|
||||
.rx_cal_busy (rx_cal_busy_s),
|
||||
.rx_cdr_locked (rx_cdr_locked_s),
|
||||
.rx_analog_reset (rx_analog_reset_s),
|
||||
.rx_digital_reset (rx_digital_reset_s),
|
||||
.rx_ready (rx_ready_s),
|
||||
.rx_rst_state (rx_rst_state_s));
|
||||
|
||||
assign spi_ad9671_csn = spi_csn_s[0];
|
||||
assign spi_ad9516_csn = spi_csn_s[1];
|
||||
assign spi_ad9553_csn = spi_csn_s[2];
|
||||
assign spi_ad9671_clk = spi_clk_s;
|
||||
assign spi_ad9516_clk = spi_clk_s;
|
||||
assign spi_ad9553_clk = spi_clk_s;
|
||||
|
||||
ad9671_fmc_spi i_ad9671_fmc_spi (
|
||||
.spi_ad9671_csn (spi_csn_s[0]),
|
||||
.spi_ad9516_csn (spi_csn_s[1]),
|
||||
.spi_ad9553_csn (spi_csn_s[2]),
|
||||
.spi_clk (spi_clk_s),
|
||||
.spi_mosi (spi_mosi_s),
|
||||
.spi_miso (spi_miso_s),
|
||||
.spi_ad9671_sdio (spi_ad9671_sdio),
|
||||
.spi_ad9516_sdio (spi_ad9516_sdio),
|
||||
.spi_ad9553_sdio (spi_ad9553_sdio));
|
||||
|
||||
system_bd i_system_bd (
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_reset_reset_n (sys_resetn),
|
||||
.sys_125m_clk_clk (sys_125m_clk),
|
||||
.sys_25m_clk_clk (sys_25m_clk),
|
||||
.sys_2m5_clk_clk (sys_2m5_clk),
|
||||
.sys_pll_locked_export (sys_pll_locked_s),
|
||||
.sys_ddr3_phy_mem_a (ddr3_a),
|
||||
.sys_ddr3_phy_mem_ba (ddr3_ba),
|
||||
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
|
||||
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
|
||||
.sys_ddr3_phy_mem_cke (ddr3_cke),
|
||||
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
|
||||
.sys_ddr3_phy_mem_dm (ddr3_dm),
|
||||
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
|
||||
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
|
||||
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
|
||||
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
|
||||
.sys_ddr3_phy_mem_dq (ddr3_dq),
|
||||
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
|
||||
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_ddr3_phy_mem_odt (ddr3_odt),
|
||||
.sys_ddr3_oct_rzqin (ddr3_rzq),
|
||||
.sys_ethernet_tx_clk_clk (eth_tx_clk),
|
||||
.sys_ethernet_rx_clk_clk (eth_rx_clk),
|
||||
.sys_ethernet_status_set_10 (),
|
||||
.sys_ethernet_status_set_1000 (),
|
||||
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
|
||||
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
|
||||
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
|
||||
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
|
||||
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
|
||||
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
|
||||
.sys_ethernet_mdio_mdc (eth_mdc),
|
||||
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
|
||||
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
|
||||
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
|
||||
.sys_gpio_in_port ({rx_xcvr_status_s, 3'd0, prci_sdo, prcq_sdo, push_buttons, dip_switches}),
|
||||
.sys_gpio_out_port ({7'd0, reset_ad9516,
|
||||
reset_ad9671, trig, prci_sck, prci_cnv, prcq_sck, prcq_cnv,
|
||||
rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
|
||||
.sys_spi_MISO (spi_miso_s),
|
||||
.sys_spi_MOSI (spi_mosi_s),
|
||||
.sys_spi_SCLK (spi_clk_s),
|
||||
.sys_spi_SS_n (spi_csn_s),
|
||||
.axi_dmac_0_fifo_wr_clock_clk (adc_clk),
|
||||
.axi_dmac_0_fifo_wr_if_ovf (adc_dovf_s),
|
||||
.axi_dmac_0_fifo_wr_if_wren (dma_wr),
|
||||
.axi_dmac_0_fifo_wr_if_data (dma_data),
|
||||
.axi_dmac_0_fifo_wr_if_sync (dma_sync),
|
||||
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
|
||||
.sys_jesd204b_s1_rx_link_valid (),
|
||||
.sys_jesd204b_s1_rx_link_ready (1'b1),
|
||||
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
|
||||
.sys_jesd204b_s1_sysref_export (rx_sysref),
|
||||
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
|
||||
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
|
||||
.sys_jesd204b_s1_sync_n_export (rx_sync),
|
||||
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
|
||||
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
|
||||
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
|
||||
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
|
||||
.sys_jesd204b_s1_locked_export (rx_cdr_locked_s),
|
||||
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
|
||||
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
|
||||
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
|
||||
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
|
||||
.axi_ad9671_1_xcvr_clk_clk (rx_clk),
|
||||
.axi_ad9671_1_xcvr_data_data (rx_data_s),
|
||||
.axi_ad9671_1_xcvr_data_data_sof (rx_sof_0),
|
||||
.axi_ad9671_1_adc_clock_clk (adc_clk),
|
||||
.axi_ad9671_1_adc_dma_if_valid (adc_valid_s),
|
||||
.axi_ad9671_1_adc_dma_if_enable (adc_enable_s),
|
||||
.axi_ad9671_1_adc_dma_if_data (adc_data_s),
|
||||
.axi_ad9671_1_adc_dma_if_dovf (adc_dovf_s),
|
||||
.axi_ad9671_1_adc_dma_if_dunf (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -1,231 +0,0 @@
|
|||
|
||||
# ad9671
|
||||
|
||||
set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o]
|
||||
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
|
||||
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
|
||||
set spi_csn_i [create_bd_port -dir I spi_csn_i]
|
||||
set spi_clk_i [create_bd_port -dir I spi_clk_i]
|
||||
set spi_clk_o [create_bd_port -dir O spi_clk_o]
|
||||
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
|
||||
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
|
||||
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
|
||||
|
||||
set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
|
||||
set rx_sync [create_bd_port -dir O rx_sync]
|
||||
set rx_sysref [create_bd_port -dir O rx_sysref]
|
||||
set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p]
|
||||
set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n]
|
||||
set gt_rx_data_sof [create_bd_port -dir O gt_rx_data_sof]
|
||||
set ad9671_sof [create_bd_port -dir I ad9671_sof]
|
||||
|
||||
|
||||
set adc_clk [create_bd_port -dir O adc_clk]
|
||||
set adc_enable [create_bd_port -dir O -from 7 -to 0 adc_enable]
|
||||
set adc_valid [create_bd_port -dir O -from 7 -to 0 adc_valid]
|
||||
set adc_data [create_bd_port -dir O -from 127 -to 0 adc_data]
|
||||
set dma_wr [create_bd_port -dir I dma_wr]
|
||||
set dma_sync [create_bd_port -dir I dma_sync]
|
||||
set dma_data [create_bd_port -dir I -from 127 -to 0 dma_data]
|
||||
|
||||
# interrupts
|
||||
|
||||
set ad9671_dma_irq [create_bd_port -dir O ad9671_dma_irq]
|
||||
|
||||
# adc peripherals
|
||||
|
||||
set axi_ad9671_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core]
|
||||
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core]
|
||||
|
||||
set axi_ad9671_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9671_jesd]
|
||||
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9671_jesd
|
||||
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9671_jesd
|
||||
|
||||
set axi_ad9671_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9671_gt]
|
||||
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {2}] [get_bd_cells axi_ad9671_gt]
|
||||
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {4}] $axi_ad9671_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9671_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9671_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {4}] $axi_ad9671_gt
|
||||
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {4}] $axi_ad9671_gt
|
||||
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9671_gt
|
||||
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9671_gt
|
||||
|
||||
set axi_ad9671_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9671_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9671_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9671_dma
|
||||
|
||||
set axi_ad9671_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9671_gt_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9671_gt_interconnect
|
||||
|
||||
set axi_ad9671_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9671_dma_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9671_dma_interconnect
|
||||
|
||||
# additions to default configuration
|
||||
|
||||
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {24}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
|
||||
|
||||
set_property LEFT 23 [get_bd_ports GPIO_I]
|
||||
set_property LEFT 23 [get_bd_ports GPIO_O]
|
||||
set_property LEFT 23 [get_bd_ports GPIO_T]
|
||||
|
||||
# connections (spi and gpio)
|
||||
|
||||
connect_bd_net -net spi_csn_2_o [get_bd_ports spi_csn_2_o] [get_bd_pins sys_ps7/SPI0_SS2_O]
|
||||
connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
|
||||
connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
|
||||
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
|
||||
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
|
||||
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
|
||||
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
|
||||
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
|
||||
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
|
||||
|
||||
# connections (gt)
|
||||
|
||||
connect_bd_net -net axi_ad9671_gt_ref_clk_c [get_bd_pins axi_ad9671_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_data_p [get_bd_pins axi_ad9671_gt/rx_data_p] [get_bd_ports rx_data_p]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_data_n [get_bd_pins axi_ad9671_gt/rx_data_n] [get_bd_ports rx_data_n]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_sync [get_bd_pins axi_ad9671_gt/rx_sync] [get_bd_ports rx_sync]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_sysref [get_bd_pins axi_ad9671_gt/rx_sysref] [get_bd_ports rx_sysref]
|
||||
|
||||
# connections (adc)
|
||||
|
||||
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_gt/rx_clk_g]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_gt/rx_clk]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_core/rx_clk]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins axi_ad9671_jesd/rx_core_clk]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_ports adc_clk]
|
||||
|
||||
connect_bd_net -net axi_ad9671_gt_rx_rst [get_bd_pins axi_ad9671_gt/rx_rst] [get_bd_pins axi_ad9671_jesd/rx_reset]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_sysref [get_bd_pins axi_ad9671_jesd/rx_sysref]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_gt_charisk [get_bd_pins axi_ad9671_gt/rx_gt_charisk] [get_bd_pins axi_ad9671_jesd/gt_rxcharisk_in]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_gt_disperr [get_bd_pins axi_ad9671_gt/rx_gt_disperr] [get_bd_pins axi_ad9671_jesd/gt_rxdisperr_in]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_gt_notintable [get_bd_pins axi_ad9671_gt/rx_gt_notintable] [get_bd_pins axi_ad9671_jesd/gt_rxnotintable_in]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_gt_data [get_bd_pins axi_ad9671_gt/rx_gt_data] [get_bd_pins axi_ad9671_jesd/gt_rxdata_in]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_rst_done [get_bd_pins axi_ad9671_gt/rx_rst_done] [get_bd_pins axi_ad9671_jesd/rx_reset_done]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_ip_comma_align [get_bd_pins axi_ad9671_gt/rx_ip_comma_align] [get_bd_pins axi_ad9671_jesd/rxencommaalign_out]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_ip_sync [get_bd_pins axi_ad9671_gt/rx_ip_sync] [get_bd_pins axi_ad9671_jesd/rx_sync]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_ip_sof [get_bd_pins axi_ad9671_gt/rx_ip_sof] [get_bd_pins axi_ad9671_jesd/rx_start_of_frame]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_ip_data [get_bd_pins axi_ad9671_gt/rx_ip_data] [get_bd_pins axi_ad9671_jesd/rx_tdata]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_data [get_bd_pins axi_ad9671_gt/rx_data] [get_bd_pins axi_ad9671_core/rx_data]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_data_sof [get_bd_pins axi_ad9671_gt/rx_data_sof] [get_bd_ports gt_rx_data_sof]
|
||||
connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core/adc_clk] [get_bd_pins axi_ad9671_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_ad9671_core_adc_enable [get_bd_pins axi_ad9671_core/adc_enable] [get_bd_ports adc_enable]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid [get_bd_pins axi_ad9671_core/adc_valid] [get_bd_ports adc_valid]
|
||||
connect_bd_net -net axi_ad9671_core_adc_data [get_bd_pins axi_ad9671_core/adc_data] [get_bd_ports adc_data]
|
||||
connect_bd_net -net axi_ad9671_core_sof [get_bd_pins axi_ad9671_core/rx_data_sof] [get_bd_ports ad9671_sof]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dwr [get_bd_ports dma_wr] [get_bd_pins axi_ad9671_dma/fifo_wr_en]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dsync [get_bd_ports dma_sync] [get_bd_pins axi_ad9671_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_ports dma_data] [get_bd_pins axi_ad9671_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_ad9671_core_adc_dovf [get_bd_pins axi_ad9671_core/adc_dovf] [get_bd_pins axi_ad9671_dma/fifo_wr_overflow]
|
||||
connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_ports ad9671_dma_irq]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9671_gt/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9671_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9671_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9671_dma/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_dma/s_axi_aresetn]
|
||||
|
||||
# interconnect (gt es)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad9671_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9671_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9671_gt/m_axi]
|
||||
connect_bd_intf_net -intf_net axi_ad9671_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9671_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_gt/m_axi_aresetn]
|
||||
|
||||
# interconnect (dma)
|
||||
|
||||
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
|
||||
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
|
||||
|
||||
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad9671_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9671_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_ad9671_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9671_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9671_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9671_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9671_dma/m_dest_axi_aresetn]
|
||||
|
||||
# ila
|
||||
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {170}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {4}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE4_WIDTH {8}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_ad9671_gt_rx_mon_data [get_bd_pins axi_ad9671_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_mon_trigger [get_bd_pins axi_ad9671_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_ad9671_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
|
||||
connect_bd_net -net axi_ad9671_core_adc_valid [get_bd_pins ila_jesd_rx_mon/PROBE4]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core/s_axi/axi_lite] SEG_data_ad9671_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_gt/s_axi/axi_lite] SEG_data_ad9671_gt
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_jesd/s_axi/Reg] SEG_data_ad9671_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_dma/s_axi/axi_lite] SEG_data_ad9671_dma
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9671_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9671_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad9671_fmc_spi (
|
||||
|
||||
spi_ad9671_csn,
|
||||
spi_ad9516_csn,
|
||||
spi_ad9553_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso,
|
||||
|
||||
spi_ad9671_sdio,
|
||||
spi_ad9516_sdio,
|
||||
spi_ad9553_sdio);
|
||||
|
||||
// 4 wire
|
||||
|
||||
input spi_ad9671_csn;
|
||||
input spi_ad9516_csn;
|
||||
input spi_ad9553_csn;
|
||||
input spi_clk;
|
||||
input spi_mosi;
|
||||
output spi_miso;
|
||||
|
||||
// 3 wire
|
||||
|
||||
inout spi_ad9671_sdio;
|
||||
inout spi_ad9516_sdio;
|
||||
inout spi_ad9553_sdio;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 5:0] spi_count = 'd0;
|
||||
reg spi_rd_wr_n = 'd0;
|
||||
reg spi_enable = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire spi_csn_s;
|
||||
wire spi_enable_s;
|
||||
wire spi_ad9516_miso_s;
|
||||
wire spi_ad9671_miso_s;
|
||||
wire spi_ad9553_miso_s;
|
||||
|
||||
// check on rising edge and change on falling edge
|
||||
|
||||
assign spi_csn_s = spi_ad9553_csn & spi_ad9516_csn & spi_ad9671_csn;
|
||||
assign spi_enable_s = spi_enable & ~spi_csn_s;
|
||||
|
||||
always @(posedge spi_clk or posedge spi_csn_s) begin
|
||||
if (spi_csn_s == 1'b1) begin
|
||||
spi_count <= 6'd0;
|
||||
spi_rd_wr_n <= 1'd0;
|
||||
end else begin
|
||||
spi_count <= spi_count + 1'b1;
|
||||
if (spi_count == 6'd0) begin
|
||||
spi_rd_wr_n <= spi_mosi;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge spi_clk or posedge spi_csn_s) begin
|
||||
if (spi_csn_s == 1'b1) begin
|
||||
spi_enable <= 1'b0;
|
||||
end else begin
|
||||
if (((spi_count == 6'd16) && (spi_ad9671_csn == 1'b0)) ||
|
||||
((spi_count == 6'd16) && (spi_ad9516_csn == 1'b0)) ||
|
||||
((spi_count == 6'd16) && (spi_ad9553_csn == 1'b0))) begin
|
||||
spi_enable <= spi_rd_wr_n;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign spi_miso = ((spi_ad9671_miso_s & ~spi_ad9671_csn) |
|
||||
(spi_ad9516_miso_s & ~spi_ad9516_csn) |
|
||||
(spi_ad9553_miso_s & ~spi_ad9553_csn));
|
||||
|
||||
// io buffers
|
||||
|
||||
assign spi_ad9671_miso_s = spi_ad9671_sdio;
|
||||
assign spi_ad9671_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
|
||||
|
||||
assign spi_ad9516_miso_s = spi_ad9516_sdio;
|
||||
assign spi_ad9516_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
|
||||
|
||||
assign spi_ad9553_miso_s = spi_ad9553_sdio;
|
||||
assign spi_ad9553_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
||||
source ../common/ad9671_fmc_bd.tcl
|
||||
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
|
||||
# constraints
|
||||
# ultrasound
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AD9} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P
|
||||
set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H11 FMC_HPC_LA04_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports reset_ad9516] ; ## G15 FMC_HPC_LA12_P
|
||||
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports reset_ad9671] ; ## C27 FMC_HPC_LA27_N
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports trig] ; ## H17 FMC_HPC_LA11_N
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports prci_sck] ; ## C18 FMC_HPC_LA14_P
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports prci_cnv] ; ## C14 FMC_HPC_LA10_P
|
||||
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports prci_sdo] ; ## C22 FMC_HPC_LA18_CC_P
|
||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports prcq_sck] ; ## C19 FMC_HPC_LA14_N
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports prcq_cnv] ; ## C15 FMC_HPC_LA10_N
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports prcq_sdo] ; ## C23 FMC_HPC_LA18_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports spi_ad9671_csn] ; ## H08 FMC_HPC_LA02_N
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_ad9671_clk] ; ## D14 FMC_HPC_LA09_P
|
||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_ad9671_sdio] ; ## D15 FMC_HPC_LA09_N
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports spi_ad9516_csn] ; ## G09 FMC_HPC_LA03_P
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_ad9516_clk] ; ## G12 FMC_HPC_LA08_P
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_ad9516_sdio] ; ## G13 FMC_HPC_LA08_N
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_ad9553_csn] ; ## G10 FMC_HPC_LA03_N
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_ad9553_clk] ; ## H07 FMC_HPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_ad9553_sdio] ; ## H13 FMC_HPC_LA07_P
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
|
||||
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_ad9671_gt_rx_clk]
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
|
||||
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
adi_project_create ad9671_fmc_zc706
|
||||
adi_project_files ad9671_fmc_zc706 [list \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc" \
|
||||
"../common/ad9671_fmc_spi.v" \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
|
||||
adi_project_run ad9671_fmc_zc706
|
||||
|
||||
|
||||
|
|
@ -1,340 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb,
|
||||
|
||||
gpio_bd,
|
||||
|
||||
hdmi_out_clk,
|
||||
hdmi_vsync,
|
||||
hdmi_hsync,
|
||||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
spdif,
|
||||
|
||||
iic_scl,
|
||||
iic_sda,
|
||||
|
||||
rx_ref_clk_p,
|
||||
rx_ref_clk_n,
|
||||
rx_sysref_p,
|
||||
rx_sysref_n,
|
||||
rx_sync_p,
|
||||
rx_sync_n,
|
||||
rx_data_p,
|
||||
rx_data_n,
|
||||
|
||||
spi_ad9671_csn,
|
||||
spi_ad9671_clk,
|
||||
spi_ad9671_sdio,
|
||||
spi_ad9516_csn,
|
||||
spi_ad9516_clk,
|
||||
spi_ad9516_sdio,
|
||||
spi_ad9553_csn,
|
||||
spi_ad9553_clk,
|
||||
spi_ad9553_sdio,
|
||||
|
||||
reset_ad9516,
|
||||
reset_ad9671,
|
||||
trig,
|
||||
prci_sck,
|
||||
prci_cnv,
|
||||
prci_sdo,
|
||||
prcq_sck,
|
||||
prcq_cnv,
|
||||
prcq_sdo);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
inout [ 2:0] DDR_ba;
|
||||
inout DDR_cas_n;
|
||||
inout DDR_ck_n;
|
||||
inout DDR_ck_p;
|
||||
inout DDR_cke;
|
||||
inout DDR_cs_n;
|
||||
inout [ 3:0] DDR_dm;
|
||||
inout [31:0] DDR_dq;
|
||||
inout [ 3:0] DDR_dqs_n;
|
||||
inout [ 3:0] DDR_dqs_p;
|
||||
inout DDR_odt;
|
||||
inout DDR_ras_n;
|
||||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
inout FIXED_IO_ps_clk;
|
||||
inout FIXED_IO_ps_porb;
|
||||
inout FIXED_IO_ps_srstb;
|
||||
|
||||
inout [14:0] gpio_bd;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [23:0] hdmi_data;
|
||||
|
||||
output spdif;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
input rx_ref_clk_p;
|
||||
input rx_ref_clk_n;
|
||||
output rx_sysref_p;
|
||||
output rx_sysref_n;
|
||||
output rx_sync_p;
|
||||
output rx_sync_n;
|
||||
input [ 1:0] rx_data_p;
|
||||
input [ 1:0] rx_data_n;
|
||||
|
||||
output spi_ad9671_csn;
|
||||
output spi_ad9671_clk;
|
||||
inout spi_ad9671_sdio;
|
||||
output spi_ad9516_csn;
|
||||
output spi_ad9516_clk;
|
||||
inout spi_ad9516_sdio;
|
||||
output spi_ad9553_csn;
|
||||
output spi_ad9553_clk;
|
||||
inout spi_ad9553_sdio;
|
||||
|
||||
inout reset_ad9516;
|
||||
inout reset_ad9671;
|
||||
inout trig;
|
||||
inout prci_sck;
|
||||
inout prci_cnv;
|
||||
inout prci_sdo;
|
||||
inout prcq_sck;
|
||||
inout prcq_cnv;
|
||||
inout prcq_sdo;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dma_wr = 'd0;
|
||||
reg dma_sync = 'd0;
|
||||
reg [127:0] dma_data = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 2:0] spi_csn;
|
||||
wire spi_clk;
|
||||
wire spi_mosi;
|
||||
wire spi_miso;
|
||||
wire rx_ref_clk;
|
||||
wire rx_sysref;
|
||||
wire rx_sync;
|
||||
wire [ 1:0] gt_rx_data_sof;
|
||||
wire ad9671_sof;
|
||||
wire [ 23:0] gpio_i;
|
||||
wire [ 23:0] gpio_o;
|
||||
wire [ 23:0] gpio_t;
|
||||
wire adc_clk;
|
||||
wire [ 7:0] adc_enable;
|
||||
wire [ 7:0] adc_valid;
|
||||
wire [127:0] adc_data;
|
||||
wire [15:0] ps_intrs;
|
||||
|
||||
assign ad9671_sof = |gt_rx_data_sof;
|
||||
|
||||
// pack place holder
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
dma_wr <= | adc_enable;
|
||||
dma_sync <= 1'b1;
|
||||
dma_data <= adc_data;
|
||||
end
|
||||
|
||||
// spi
|
||||
|
||||
assign spi_ad9671_csn = spi_csn[0];
|
||||
assign spi_ad9516_csn = spi_csn[1];
|
||||
assign spi_ad9553_csn = spi_csn[2];
|
||||
assign spi_ad9671_clk = spi_clk;
|
||||
assign spi_ad9516_clk = spi_clk;
|
||||
assign spi_ad9553_clk = spi_clk;
|
||||
|
||||
ad9671_fmc_spi i_spi (
|
||||
.spi_ad9671_csn (spi_csn[0]),
|
||||
.spi_ad9516_csn (spi_csn[1]),
|
||||
.spi_ad9553_csn (spi_csn[2]),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_ad9671_sdio (spi_ad9671_sdio),
|
||||
.spi_ad9516_sdio (spi_ad9516_sdio),
|
||||
.spi_ad9553_sdio (spi_ad9553_sdio));
|
||||
|
||||
// data interface
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (rx_ref_clk_p),
|
||||
.IB (rx_ref_clk_n),
|
||||
.O (rx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
OBUFDS i_obufds_rx_sysref (
|
||||
.I (rx_sysref),
|
||||
.O (rx_sysref_p),
|
||||
.OB (rx_sysref_n));
|
||||
|
||||
OBUFDS i_obufds_rx_sync (
|
||||
.I (rx_sync),
|
||||
.O (rx_sync_p),
|
||||
.OB (rx_sync_n));
|
||||
|
||||
// gpio/ctl interface
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(24)) i_iobuf (
|
||||
.dt (gpio_t[23:0]),
|
||||
.di (gpio_o[23:0]),
|
||||
.do (gpio_i[23:0]),
|
||||
.dio ({ reset_ad9516, // 23
|
||||
reset_ad9671, // 22
|
||||
trig, // 21
|
||||
prci_sck, // 20
|
||||
prci_cnv, // 19
|
||||
prci_sdo, // 18
|
||||
prcq_sck, // 17
|
||||
prcq_cnv, // 16
|
||||
prcq_sdo, // 15
|
||||
gpio_bd})); // 0
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
.DDR_cas_n (DDR_cas_n),
|
||||
.DDR_ck_n (DDR_ck_n),
|
||||
.DDR_ck_p (DDR_ck_p),
|
||||
.DDR_cke (DDR_cke),
|
||||
.DDR_cs_n (DDR_cs_n),
|
||||
.DDR_dm (DDR_dm),
|
||||
.DDR_dq (DDR_dq),
|
||||
.DDR_dqs_n (DDR_dqs_n),
|
||||
.DDR_dqs_p (DDR_dqs_p),
|
||||
.DDR_odt (DDR_odt),
|
||||
.DDR_ras_n (DDR_ras_n),
|
||||
.DDR_reset_n (DDR_reset_n),
|
||||
.DDR_we_n (DDR_we_n),
|
||||
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||
.FIXED_IO_mio (FIXED_IO_mio),
|
||||
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data (adc_data),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_valid (adc_valid),
|
||||
.dma_data (dma_data),
|
||||
.dma_sync (dma_sync),
|
||||
.dma_wr (dma_wr),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
.ps_intr_5 (ps_intrs[5]),
|
||||
.ps_intr_6 (ps_intrs[6]),
|
||||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.ad9671_dma_irq (ps_intrs[13]),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_sysref (rx_sysref),
|
||||
.gt_rx_data_sof(gt_rx_data_sof),
|
||||
.ad9671_sof(ad9671_sof),
|
||||
.spdif (spdif),
|
||||
.spi_clk_i (spi_clk),
|
||||
.spi_clk_o (spi_clk),
|
||||
.spi_csn_0_o (spi_csn[0]),
|
||||
.spi_csn_1_o (spi_csn[1]),
|
||||
.spi_csn_2_o (spi_csn[2]),
|
||||
.spi_csn_i (1'b1),
|
||||
.spi_sdi_i (spi_miso),
|
||||
.spi_sdo_i (spi_mosi),
|
||||
.spi_sdo_o (spi_mosi));
|
||||
|
||||
endmodule
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue