fmcomms5: Updated zc702 project to the latest framework

main
Adrian Costina 2015-03-31 17:44:09 +03:00
parent fb3ee53790
commit e58e9bc701
3 changed files with 126 additions and 98 deletions

View File

@ -2,3 +2,17 @@
source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
source ../common/fmcomms5_bd.tcl source ../common/fmcomms5_bd.tcl
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150.0}] $sys_ps7
# ila (adc) master
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_0
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_0
ad_connect axi_ad9361_0_clk ila_adc_0/clk
ad_connect util_adc_pack_0/dvalid ila_adc_0/probe0
ad_connect util_adc_pack_0/ddata ila_adc_0/probe1

View File

@ -1,8 +1,7 @@
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms5_zc702 adi_project_create fmcomms5_zc702
adi_project_files fmcomms5_zc702 [list \ adi_project_files fmcomms5_zc702 [list \

View File

@ -41,28 +41,28 @@
module system_top ( module system_top (
DDR_addr, ddr_addr,
DDR_ba, ddr_ba,
DDR_cas_n, ddr_cas_n,
DDR_ck_n, ddr_ck_n,
DDR_ck_p, ddr_ck_p,
DDR_cke, ddr_cke,
DDR_cs_n, ddr_cs_n,
DDR_dm, ddr_dm,
DDR_dq, ddr_dq,
DDR_dqs_n, ddr_dqs_n,
DDR_dqs_p, ddr_dqs_p,
DDR_odt, ddr_odt,
DDR_ras_n, ddr_ras_n,
DDR_reset_n, ddr_reset_n,
DDR_we_n, ddr_we_n,
FIXED_IO_ddr_vrn, fixed_io_ddr_vrn,
FIXED_IO_ddr_vrp, fixed_io_ddr_vrp,
FIXED_IO_mio, fixed_io_mio,
FIXED_IO_ps_clk, fixed_io_ps_clk,
FIXED_IO_ps_porb, fixed_io_ps_porb,
FIXED_IO_ps_srstb, fixed_io_ps_srstb,
gpio_bd, gpio_bd,
@ -136,28 +136,28 @@ module system_top (
ref_clk_p, ref_clk_p,
ref_clk_n); ref_clk_n);
inout [ 14:0] DDR_addr; inout [ 14:0] ddr_addr;
inout [ 2:0] DDR_ba; inout [ 2:0] ddr_ba;
inout DDR_cas_n; inout ddr_cas_n;
inout DDR_ck_n; inout ddr_ck_n;
inout DDR_ck_p; inout ddr_ck_p;
inout DDR_cke; inout ddr_cke;
inout DDR_cs_n; inout ddr_cs_n;
inout [ 3:0] DDR_dm; inout [ 3:0] ddr_dm;
inout [ 31:0] DDR_dq; inout [ 31:0] ddr_dq;
inout [ 3:0] DDR_dqs_n; inout [ 3:0] ddr_dqs_n;
inout [ 3:0] DDR_dqs_p; inout [ 3:0] ddr_dqs_p;
inout DDR_odt; inout ddr_odt;
inout DDR_ras_n; inout ddr_ras_n;
inout DDR_reset_n; inout ddr_reset_n;
inout DDR_we_n; inout ddr_we_n;
inout FIXED_IO_ddr_vrn; inout fixed_io_ddr_vrn;
inout FIXED_IO_ddr_vrp; inout fixed_io_ddr_vrp;
inout [ 53:0] FIXED_IO_mio; inout [ 53:0] fixed_io_mio;
inout FIXED_IO_ps_clk; inout fixed_io_ps_clk;
inout FIXED_IO_ps_porb; inout fixed_io_ps_porb;
inout FIXED_IO_ps_srstb; inout fixed_io_ps_srstb;
inout [ 15:0] gpio_bd; inout [ 15:0] gpio_bd;
@ -239,15 +239,21 @@ module system_top (
// internal signals // internal signals
wire sys_100m_resetn; wire sys_100m_resetn;
wire sys_100m_clk;
wire ref_clk_s; wire ref_clk_s;
wire ref_clk; wire ref_clk;
wire [ 63:0] gpio_i; wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o; wire [ 63:0] gpio_o;
wire [ 63:0] gpio_t; wire [ 63:0] gpio_t;
wire [15:0] ps_intrs;
wire gpio_open_45_45; wire gpio_open_45_45;
wire gpio_open_44_44; wire gpio_open_44_44;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
// multi-chip synchronization // multi-chip synchronization
@ -304,31 +310,38 @@ module system_top (
gpio_status_0, // 16 gpio_status_0, // 16
gpio_bd})); // 0 gpio_bd})); // 0
assign spi_ad9361_0 = spi0_csn[0];
assign spi_ad9361_1 = spi0_csn[1];
assign spi_ad5355 = spi0_csn[2];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr), .ddr_addr (ddr_addr),
.DDR_ba (DDR_ba), .ddr_ba (ddr_ba),
.DDR_cas_n (DDR_cas_n), .ddr_cas_n (ddr_cas_n),
.DDR_ck_n (DDR_ck_n), .ddr_ck_n (ddr_ck_n),
.DDR_ck_p (DDR_ck_p), .ddr_ck_p (ddr_ck_p),
.DDR_cke (DDR_cke), .ddr_cke (ddr_cke),
.DDR_cs_n (DDR_cs_n), .ddr_cs_n (ddr_cs_n),
.DDR_dm (DDR_dm), .ddr_dm (ddr_dm),
.DDR_dq (DDR_dq), .ddr_dq (ddr_dq),
.DDR_dqs_n (DDR_dqs_n), .ddr_dqs_n (ddr_dqs_n),
.DDR_dqs_p (DDR_dqs_p), .ddr_dqs_p (ddr_dqs_p),
.DDR_odt (DDR_odt), .ddr_odt (ddr_odt),
.DDR_ras_n (DDR_ras_n), .ddr_ras_n (ddr_ras_n),
.DDR_reset_n (DDR_reset_n), .ddr_reset_n (ddr_reset_n),
.DDR_we_n (DDR_we_n), .ddr_we_n (ddr_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio), .fixed_io_mio (fixed_io_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk), .fixed_io_ps_clk (fixed_io_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb), .fixed_io_ps_porb (fixed_io_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), .fixed_io_ps_srstb (fixed_io_ps_srstb),
.GPIO_I (gpio_i), .gpio_i (gpio_i),
.GPIO_O (gpio_o), .gpio_o (gpio_o),
.GPIO_T (gpio_t), .gpio_t (gpio_t),
.hdmi_data (hdmi_data), .hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e), .hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync), .hdmi_hsync (hdmi_hsync),
@ -336,24 +349,18 @@ module system_top (
.hdmi_vsync (hdmi_vsync), .hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl), .iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda), .iic_main_sda_io (iic_sda),
.ps_intr_0 (ps_intrs[0]), .ps_intr_00 (1'b0),
.ps_intr_1 (ps_intrs[1]), .ps_intr_01 (1'b0),
.ps_intr_10 (ps_intrs[10]), .ps_intr_02 (1'b0),
.ps_intr_11 (ps_intrs[11]), .ps_intr_03 (1'b0),
.ps_intr_12 (ps_intrs[12]), .ps_intr_04 (1'b0),
.ps_intr_13 (ps_intrs[13]), .ps_intr_05 (1'b0),
.ps_intr_2 (ps_intrs[2]), .ps_intr_06 (1'b0),
.ps_intr_3 (ps_intrs[3]), .ps_intr_07 (1'b0),
.ps_intr_4 (ps_intrs[4]), .ps_intr_08 (1'b0),
.ps_intr_5 (ps_intrs[5]), .ps_intr_09 (1'b0),
.ps_intr_6 (ps_intrs[6]), .ps_intr_10 (1'b0),
.ps_intr_7 (ps_intrs[7]), .ps_intr_11 (1'b0),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ad9361_dac_dma_irq (ps_intrs[12]),
.ad9361_adc_dma_irq (ps_intrs[13]),
.fmcomms5_gpio_irq(),
.fmcomms5_spi_irq(),
.rx_clk_in_0_n (rx_clk_in_0_n), .rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p), .rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n), .rx_clk_in_1_n (rx_clk_in_1_n),
@ -367,16 +374,24 @@ module system_top (
.rx_frame_in_1_n (rx_frame_in_1_n), .rx_frame_in_1_n (rx_frame_in_1_n),
.rx_frame_in_1_p (rx_frame_in_1_p), .rx_frame_in_1_p (rx_frame_in_1_p),
.spdif (spdif), .spdif (spdif),
.spi_csn_0_i (1'b1), .spi0_clk_i (spi0_clk),
.spi_csn_0_o (spi_ad9361_0), .spi0_clk_o (spi0_clk),
.spi_csn_1_o (spi_ad9361_1), .spi0_csn_0_o (spi0_csn[0]),
.spi_csn_2_o (spi_ad5355), .spi0_csn_1_o (spi0_csn[1]),
.spi_miso_i (spi_miso), .spi0_csn_2_o (spi0_csn[2]),
.spi_mosi_i (1'b0), .spi0_csn_i (1'b1),
.spi_mosi_o (spi_mosi), .spi0_sdi_i (spi0_miso),
.spi_sclk_i (1'b0), .spi0_sdo_i (spi0_mosi),
.spi_sclk_o (spi_clk), .spi0_sdo_o (spi0_mosi),
.sys_100m_clk (sys_100m_clk), .spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.sys_100m_resetn (sys_100m_resetn), .sys_100m_resetn (sys_100m_resetn),
.tx_clk_out_0_n (tx_clk_out_0_n), .tx_clk_out_0_n (tx_clk_out_0_n),
.tx_clk_out_0_p (tx_clk_out_0_p), .tx_clk_out_0_p (tx_clk_out_0_p),