From e644a99648b5b119c1b5c3405e5b123c95a14801 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Mon, 31 Jul 2017 13:14:09 +0200
Subject: [PATCH] util_axis_fifo: Fix some data width mismatches

Make sure that the right hand side expression of assignments is not wider
than the target signal. This avoids warnings about implicit truncations.

None of these changes affect the behaviour, just fixes some warnings about
implicit signal truncation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/util_axis_fifo/address_gray_pipelined.v | 10 ++++++----
 library/util_axis_fifo/address_sync.v           | 10 +++++-----
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v
index 9bd457028..2d6db974a 100644
--- a/library/util_axis_fifo/address_gray_pipelined.v
+++ b/library/util_axis_fifo/address_gray_pipelined.v
@@ -52,6 +52,8 @@ module fifo_address_gray_pipelined #(
   output reg [ADDRESS_WIDTH:0] s_axis_room
 );
 
+localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
+
 reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
 reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
 wire [ADDRESS_WIDTH:0] _s_axis_raddr;
@@ -66,7 +68,7 @@ assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
 always @(*)
 begin
   if (s_axis_ready && s_axis_valid)
-    _s_axis_waddr_next <= _s_axis_waddr + 1;
+    _s_axis_waddr_next <= _s_axis_waddr + 1'b1;
   else
     _s_axis_waddr_next <= _s_axis_waddr;
 end
@@ -83,7 +85,7 @@ end
 always @(*)
 begin
   if (m_axis_ready && m_axis_valid)
-    _m_axis_raddr_next <= _m_axis_raddr + 1;
+    _m_axis_raddr_next <= _m_axis_raddr + 1'b1;
   else
     _m_axis_raddr_next <= _m_axis_raddr;
 end
@@ -124,12 +126,12 @@ begin
   if (s_axis_aresetn == 1'b0) begin
     s_axis_ready <= 1'b1;
     s_axis_empty <= 1'b1;
-    s_axis_room <= 2**ADDRESS_WIDTH;
+    s_axis_room <= MAX_ROOM;
   end else begin
     s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
       _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
     s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
-    s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
+    s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM;
   end
 end
 
diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v
index a38fe6443..1d9a04472 100644
--- a/library/util_axis_fifo/address_sync.v
+++ b/library/util_axis_fifo/address_sync.v
@@ -51,9 +51,9 @@ module fifo_address_sync #(
   output [ADDRESS_WIDTH:0] s_axis_room
 );
 
-parameter ADDRESS_WIDTH = 4;
+localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
 
-reg [ADDRESS_WIDTH:0] room = 2**ADDRESS_WIDTH;
+reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
 reg [ADDRESS_WIDTH:0] level = 'h00;
 reg [ADDRESS_WIDTH:0] level_next;
 
@@ -92,13 +92,13 @@ begin
     m_axis_valid <= 1'b0;
     s_axis_ready <= 1'b0;
     level <= 'h00;
-    room <= 2**ADDRESS_WIDTH;
+    room <= MAX_ROOM;
     s_axis_empty <= 'h00;
   end else begin
     level <= level_next;
-    room <= 2**ADDRESS_WIDTH - level_next;
+    room <= MAX_ROOM - level_next;
     m_axis_valid <= level_next != 0;
-    s_axis_ready <= level_next != 2**ADDRESS_WIDTH;
+    s_axis_ready <= level_next != MAX_ROOM;
     s_axis_empty <= level_next == 0;
   end
 end