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axi_ad7616: Change the DMA interface type to Write FIFO

main
Istvan Csomortani 2016-06-29 14:11:02 +03:00
parent 64633e519c
commit e6494b9a74
5 changed files with 237 additions and 125 deletions
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179
library/axi_ad7616/axi_ad7616.v
View File

@ -82,12 +82,11 @@ module axi_ad7616 (
s_axi_rdata,
s_axi_rready,
// AXI-Stream Master
// Write FIFO interface
m_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_xfer_req,
adc_valid,
adc_data,
adc_sync,
irq
);
@ -96,11 +95,9 @@ module axi_ad7616 (
parameter ID = 0;
parameter IF_TYPE = 1;
parameter M_AXIS_READY_ENABLE = 0;
// local parameters
localparam DATA_WIDTH = 8;
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
localparam PARALLEL = 1;
@ -109,50 +106,53 @@ module axi_ad7616 (
// IO definitions
output sclk;
output cs_n;
output sdo;
input sdi_0;
input sdi_1;
output sclk;
output cs_n;
output sdo;
input sdi_0;
input sdi_1;
output [15:0] db_o;
input [15:0] db_i;
output db_t;
output rd_n;
output wr_n;
output [15:0] db_o;
input [15:0] db_i;
output db_t;
output rd_n;
output wr_n;
output cnvst;
input busy;
output cnvst;
input busy;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
output [(NUM_OF_SDI * DATA_WIDTH-1):0] m_axis_tdata;
input m_axis_tready;
output m_axis_tvalid;
input m_axis_xfer_req;
output adc_valid;
output [15:0] adc_data;
output adc_sync;
output irq;
output irq;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
// internal signals
wire up_clk;
@ -180,12 +180,10 @@ module axi_ad7616 (
wire rd_valid_s;
wire m_axis_ready_s;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
wire [15:0] adc_data_s;
// defaults
@ -207,8 +205,6 @@ module axi_ad7616 (
end
end
assign m_axis_ready_s = (M_AXIS_READY_ENABLE) ? m_axis_tready : 1'b1;
generate if (IF_TYPE == SERIAL) begin
// ground all parallel interface signals
@ -225,10 +221,10 @@ module axi_ad7616 (
wire [15:0] s0_cmd_data_s;
wire s0_sdo_data_ready_s;
wire s0_sdo_data_valid_s;
wire [(DATA_WIDTH-1):0] s0_sdo_data_s;
wire [ 7:0] s0_sdo_data_s;
wire s0_sdi_data_ready_s;
wire s0_sdi_data_valid_s;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data_s;
wire [15:0] s0_sdi_data_s;
wire s0_sync_ready_s;
wire s0_sync_valid_s;
wire [ 7:0] s0_sync_s;
@ -237,10 +233,10 @@ module axi_ad7616 (
wire [15:0] s1_cmd_data_s;
wire s1_sdo_data_ready_s;
wire s1_sdo_data_valid_s;
wire [(DATA_WIDTH-1):0] s1_sdo_data_s;
wire [ 7:0] s1_sdo_data_s;
wire s1_sdi_data_ready_s;
wire s1_sdi_data_valid_s;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data_s;
wire [15:0] s1_sdi_data_s;
wire s1_sync_ready_s;
wire s1_sync_valid_s;
wire [ 7:0] s1_sync_s;
@ -249,28 +245,28 @@ module axi_ad7616 (
wire [15:0] m_cmd_data_s;
wire m_sdo_data_ready_s;
wire m_sdo_data_valid_s;
wire [(DATA_WIDTH-1):0] m_sdo_data_s;
wire [7:0] m_sdo_data_s;
wire m_sdi_data_ready_s;
wire m_sdi_data_valid_s;
wire [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data_s;
wire [15:0] m_sdi_data_s;
wire m_sync_ready_s;
wire m_sync_valid_s;
wire [ 7:0] m_sync_s;
wire offload0_cmd_wr_en_s;
wire [15:0] offload0_cmd_wr_data_s;
wire offload0_sdo_wr_en_s;
wire [(DATA_WIDTH-1):0] offload0_sdo_wr_data_s;
wire [ 7:0] offload0_sdo_wr_data_s;
wire offload0_mem_reset_s;
wire offload0_enable_s;
wire offload0_enabled_s;
axi_spi_engine #(
.DATA_WIDTH (DATA_WIDTH),
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OFFLOAD(1),
.MM_IF_TYPE(1),
.UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
) i_axi_spi_engine(
) i_axi_spi_engine (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
@ -305,9 +301,9 @@ module axi_ad7616 (
.offload0_enabled(offload0_enabled_s));
spi_engine_offload #(
.DATA_WIDTH (DATA_WIDTH),
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_offload(
) i_spi_engine_offload (
.ctrl_clk (up_clk),
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
@ -331,12 +327,12 @@ module axi_ad7616 (
.sync_valid (s1_sync_valid_s),
.sync_ready (s1_sync_ready_s),
.sync_data (s1_sync_s),
.offload_sdi_valid (m_axis_tvalid),
.offload_sdi_valid (m_axis_valid_s),
.offload_sdi_ready (m_axis_ready_s),
.offload_sdi_data (m_axis_tdata));
.offload_sdi_data (m_axis_data_s));
spi_engine_interconnect #(
.DATA_WIDTH (DATA_WIDTH),
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_interconnect (
.clk (up_clk),
@ -379,7 +375,7 @@ module axi_ad7616 (
.s1_sync (s1_sync_s));
spi_engine_execution #(
.DATA_WIDTH (DATA_WIDTH),
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_execution (
.clk (up_clk),
@ -407,8 +403,21 @@ module axi_ad7616 (
.cs (cs_n),
.three_wire ());
end
axi_ad7616_maxis2wrfifo #(
.DATA_WIDTH(16)
) i_maxis2wrfifo (
.clk(up_clk),
.rstn(up_rstn),
.sync_in(trigger_s),
.m_axis_data(m_axis_data_s),
.m_axis_ready(m_axis_ready_s),
.m_axis_valid(m_axis_valid_s),
.fifo_wr_en(adc_valid),
.fifo_wr_data(adc_data_s),
.fifo_wr_sync(adc_sync)
);
end
endgenerate
generate if (IF_TYPE == PARALLEL) begin
@ -422,23 +431,23 @@ module axi_ad7616 (
assign up_rdata_if_s = 1'h0;
axi_ad7616_pif i_ad7616_parallel_interface (
.cs_n(cs_n),
.db_o(db_o),
.db_i(db_i),
.db_t(db_t),
.rd_n(rd_n),
.wr_n(wr_n),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_xfer_req(m_axis_xfer_req),
.end_of_conv(trigger_s),
.clk(up_clk),
.rstn(up_rstn),
.rd_req(rd_req_s),
.wr_req(wr_req_s),
.wr_data(wr_data_s),
.rd_data(rd_data_s),
.rd_valid(rd_valid_s)
.cs_n (cs_n),
.db_o (db_o),
.db_i (db_i),
.db_t (db_t),
.rd_n (rd_n),
.wr_n (wr_n),
.adc_data (adc_data_s),
.adc_valid (adc_valid),
.adc_sync (adc_sync),
.end_of_conv (trigger_s),
.clk (up_clk),
.rstn (up_rstn),
.rd_req (rd_req_s),
.wr_req (wr_req_s),
.wr_data (wr_data_s),
.rd_data (rd_data_s),
.rd_valid (rd_valid_s)
);
end
@ -467,6 +476,8 @@ module axi_ad7616 (
.up_rdata (up_rdata_cntrl_s),
.up_rack (up_rack_cntrl_s));
assign adc_data = adc_data_s;
// up bus interface
up_axi #(

7
library/axi_ad7616/axi_ad7616_ip.tcl
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@ -5,11 +5,12 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad7616
adi_ip_files axi_ad7616 [list \
"axi_ad7616.v" \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad7616_control.v" \
"axi_ad7616_pif.v" \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/common/up_axi.v"]
"axi_ad7616_maxis2wrfifo.v" \
"axi_ad7616.v" ]
adi_ip_properties axi_ad7616

107
library/axi_ad7616/axi_ad7616_maxis2wrfifo.v Normal file
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@ -0,0 +1,107 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_maxis2wrfifo (
clk,
rstn,
sync_in,
// m_axis interface
m_axis_data,
m_axis_ready,
m_axis_valid,
m_axis_xfer_req,
// write fifo interface
fifo_wr_en,
fifo_wr_data,
fifo_wr_sync,
fifo_wr_xfer_req
);
parameter DATA_WIDTH = 16;
input clk;
input rstn;
input sync_in;
input [DATA_WIDTH-1:0] m_axis_data;
output m_axis_ready;
input m_axis_valid;
output m_axis_xfer_req;
output fifo_wr_en;
output [DATA_WIDTH-1:0] fifo_wr_data;
output fifo_wr_sync;
input fifo_wr_xfer_req;
reg m_axis_ready = 1'b0;
reg m_axis_xfer_req = 1'b0;
reg fifo_wr_en = 1'b0;
reg [DATA_WIDTH-1:0] fifo_wr_data = 'b0;
reg fifo_wr_sync = 1'b0;
always @(posedge clk) begin
if (rstn == 1'b0) begin
m_axis_ready <= 1'b0;
m_axis_xfer_req <= 1'b0;
fifo_wr_data <= 'b0;
fifo_wr_en <= 1'b0;
fifo_wr_sync <= 1'b0;
end else begin
m_axis_ready <= 1'b1;
m_axis_xfer_req <= fifo_wr_xfer_req;
fifo_wr_data <= m_axis_data;
fifo_wr_en <= m_axis_valid;
if (sync_in == 1'b1) begin
fifo_wr_sync <= 1'b1;
end else if ((m_axis_valid == 1'b1) &&
(fifo_wr_sync == 1'b1)) begin
fifo_wr_sync <= 1'b0;
end
end
end
endmodule

59
library/axi_ad7616/axi_ad7616_pif.v
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@ -50,11 +50,11 @@ module axi_ad7616_pif (
rd_n,
wr_n,
// axi stream master
// FIFO interface
m_axis_tdata,
m_axis_tvalid,
m_axis_xfer_req,
adc_data,
adc_valid,
adc_sync,
// end of convertion
@ -92,9 +92,9 @@ module axi_ad7616_pif (
output [15:0] rd_data;
output rd_valid;
output [31:0] m_axis_tdata;
output m_axis_tvalid;
input m_axis_xfer_req;
output [15:0] adc_data;
output adc_valid;
output adc_sync;
// state registers
@ -118,15 +118,15 @@ module axi_ad7616_pif (
reg xfer_req_d = 1'h0;
reg [15:0] data_out_a = 16'h0;
reg [15:0] data_out_b = 16'h0;
reg rd_db_valid_div2 = 1'h0;
reg adc_sync = 1'h0;
reg rd_valid = 1'h0;
reg rd_valid_d = 1'h0;
reg [15:0] rd_data = 16'h0;
// internal wires
wire start_transfer;
wire rd_db_valid;
wire start_transfer_s;
wire rd_valid_s;
// FSM state register
@ -140,7 +140,7 @@ module axi_ad7616_pif (
// counters to control the RD_N and WR_N lines
assign start_transfer = end_of_conv | rd_req | wr_req;
assign start_transfer_s = end_of_conv | rd_req | wr_req;
always @(posedge clk) begin
if (rstn == 1'b0) begin
@ -167,7 +167,7 @@ module axi_ad7616_pif (
always @(*) begin
case (transfer_state)
IDLE : begin
transfer_state_next <= (start_transfer == 1'b1) ? CS_LOW : IDLE;
transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE;
end
CS_LOW : begin
transfer_state_next <= CNTRL0_LOW;
@ -196,28 +196,21 @@ module axi_ad7616_pif (
// data valid for the register access and m_axis interface
assign rd_db_valid = ((transfer_state == CS_HIGH) &&
assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) &&
((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (cs_n) begin
rd_db_valid_div2 <= 1'h0;
end else begin
rd_db_valid_div2 <= (rd_db_valid) ? ~rd_db_valid_div2 : rd_db_valid_div2;
end
end
// FSM output logic
assign db_o = wr_data;
always @(posedge clk) begin
data_out_a <= (transfer_state == CNTRL0_HIGH) ? db_i : data_out_a;
data_out_b <= (transfer_state == CNTRL1_HIGH) ? db_i : data_out_b;
rd_valid <= rd_db_valid;
rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data;
rd_valid_d <= rd_valid_s;
rd_valid <= rd_valid_s & ~rd_valid_d;
end
assign rd_data = data_out_a;
assign adc_valid = rd_valid;
assign adc_data = rd_data;
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
assign db_t = ~wr_req_d;
@ -225,17 +218,15 @@ module axi_ad7616_pif (
(transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
// Master AXI stream output logic with additional xfer_req signal
// The first valid data is ALWAYS the first sample of a convertion
// sync will be asserted at the first valid data right after the convertion start
always @(negedge clk) begin
always @(posedge clk) begin
if (end_of_conv == 1'b1) begin
xfer_req_d <= m_axis_xfer_req;
adc_sync <= 1'b1;
end else if (rd_valid == 1'b1) begin
adc_sync <= 1'b0;
end
end
assign m_axis_tdata = {data_out_b, data_out_a};
assign m_axis_tvalid = xfer_req_d & rd_valid & rd_db_valid_div2;
endmodule

10
projects/ad7616_sdz/common/ad7616_bd.tcl
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@ -26,7 +26,7 @@ set axi_ad7616 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad7616:1.0 axi
set_property -dict [list CONFIG.IF_TYPE $ad7616_if] $axi_ad7616
set axi_ad7616_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad7616_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad7616_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad7616_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad7616_dma
@ -59,9 +59,11 @@ if {$ad7616_if == 0} {
}
ad_connect sys_cpu_clk axi_ad7616_dma/s_axis_aclk
ad_connect axi_ad7616/m_axis axi_ad7616_dma/s_axis
ad_connect axi_ad7616/m_axis_xfer_req axi_ad7616_dma/s_axis_xfer_req
ad_connect sys_cpu_clk axi_ad7616_dma/s_axi_aclk
ad_connect sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync
# interconnect