From e650253013ee214cfeb97a3c95e2b7a7e762735b Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 24 Jun 2014 14:22:05 -0400 Subject: [PATCH] library: register map changes and for mathworks --- library/axi_ad9361/axi_ad9361.v | 316 +++++++------------- library/axi_ad9361/axi_ad9361_dev_if.v | 153 ++++------ library/axi_ad9361/axi_ad9361_ip.tcl | 6 +- library/axi_ad9361/axi_ad9361_rx.v | 321 ++++++-------------- library/axi_ad9361/axi_ad9361_rx_channel.v | 52 ++-- library/axi_ad9361/axi_ad9361_rx_pnmon.v | 281 +++++++++++++----- library/axi_ad9361/axi_ad9361_tx.v | 312 +++++++------------- library/axi_ad9361/axi_ad9361_tx_channel.v | 323 ++++++++++++++++++--- library/axi_ad9361/axi_ad9361_tx_dds.v | 16 - 9 files changed, 869 insertions(+), 911 deletions(-) diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 94eeca9d5..4cd836e47 100755 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -61,45 +61,47 @@ module axi_ad9361 ( // transmit master/slave - dac_enable_in, - dac_enable_out, + dac_sync_in, + dac_sync_out, // delay clock delay_clk, - // dma interface + // master interface l_clk, clk, - adc_chan_i1, - adc_enable_0, - adc_valid_0, - adc_chan_q1, - adc_enable_1, - adc_valid_1, - adc_chan_i2, - adc_enable_2, - adc_valid_2, - adc_chan_q2, - adc_enable_3, - adc_valid_3, + // dma interface + + adc_enable_i0, + adc_valid_i0, + adc_data_i0, + adc_enable_q0, + adc_valid_q0, + adc_data_q0, + adc_enable_i1, + adc_valid_i1, + adc_data_i1, + adc_enable_q1, + adc_valid_q1, + adc_data_q1, adc_dovf, adc_dunf, - dac_data_0, - dac_enable_0, - dac_drd_0, - dac_data_1, - dac_enable_1, - dac_drd_1, - dac_data_2, - dac_enable_2, - dac_drd_2, - dac_data_3, - dac_enable_3, - dac_drd_3, + dac_enable_i0, + dac_valid_i0, + dac_data_i0, + dac_enable_q0, + dac_valid_q0, + dac_data_q0, + dac_enable_i1, + dac_valid_i1, + dac_data_i1, + dac_enable_q1, + dac_valid_q1, + dac_data_q1, dac_dovf, dac_dunf, @@ -125,11 +127,6 @@ module axi_ad9361 ( s_axi_rresp, s_axi_rready, - // monitor signals - - adc_mon_valid, - adc_mon_data, - // chipscope signals dev_dbg_data, @@ -143,8 +140,8 @@ module axi_ad9361 ( parameter PCORE_DAC_DP_DISABLE = 0; parameter PCORE_ADC_DP_DISABLE = 0; parameter C_S_AXI_MIN_SIZE = 32'hffff; - parameter C_BASEADDR = 32'hffffffff; - parameter C_HIGHADDR = 32'h00000000; + parameter C_HIGHADDR = 32'hffffffff; + parameter C_BASEADDR = 32'h00000000; // physical interface (receive) @@ -166,46 +163,47 @@ module axi_ad9361 ( // master/slave - input dac_enable_in; - output dac_enable_out; + input dac_sync_in; + output dac_sync_out; // delay clock input delay_clk; - // dma interface + // master interface output l_clk; - input clk; - output [15:0] adc_chan_i1; - output adc_enable_0; - output adc_valid_0; - output [15:0] adc_chan_q1; - output adc_enable_1; - output adc_valid_1; - output [15:0] adc_chan_i2; - output adc_enable_2; - output adc_valid_2; - output [15:0] adc_chan_q2; - output adc_enable_3; - output adc_valid_3; + // dma interface + + output adc_enable_i0; + output adc_valid_i0; + output [15:0] adc_data_i0; + output adc_enable_q0; + output adc_valid_q0; + output [15:0] adc_data_q0; + output adc_enable_i1; + output adc_valid_i1; + output [15:0] adc_data_i1; + output adc_enable_q1; + output adc_valid_q1; + output [15:0] adc_data_q1; input adc_dovf; input adc_dunf; - input [15:0] dac_data_0; - output dac_enable_0; - output dac_drd_0; - input [15:0] dac_data_1; - output dac_enable_1; - output dac_drd_1; - input [15:0] dac_data_2; - output dac_enable_2; - output dac_drd_2; - input [15:0] dac_data_3; - output dac_enable_3; - output dac_drd_3; + output dac_enable_i0; + output dac_valid_i0; + input [15:0] dac_data_i0; + output dac_enable_q0; + output dac_valid_q0; + input [15:0] dac_data_q0; + output dac_enable_i1; + output dac_valid_i1; + input [15:0] dac_data_i1; + output dac_enable_q1; + output dac_valid_q1; + input [15:0] dac_data_q1; input dac_dovf; input dac_dunf; @@ -231,11 +229,6 @@ module axi_ad9361 ( output [ 1:0] s_axi_rresp; input s_axi_rready; - // monitor interface - - output adc_mon_valid; - output [47:0] adc_mon_data; - // chipscope signals output [111:0] dev_dbg_data; @@ -255,17 +248,11 @@ module axi_ad9361 ( // internal signals wire adc_valid_s; - wire [11:0] adc_data_i1_s; - wire [11:0] adc_data_q1_s; - wire [11:0] adc_data_i2_s; - wire [11:0] adc_data_q2_s; + wire [47:0] adc_data_s; wire adc_status_s; wire adc_r1_mode_s; wire dac_valid_s; - wire [11:0] dac_data_i1_s; - wire [11:0] dac_data_q1_s; - wire [11:0] dac_data_i2_s; - wire [11:0] dac_data_q2_s; + wire [47:0] dac_data_s; wire dac_r1_mode_s; wire delay_sel_s; wire delay_rwn_s; @@ -274,36 +261,6 @@ module axi_ad9361 ( wire [ 4:0] delay_rdata_s; wire delay_ack_t_s; wire delay_locked_s; - wire adc_valid_pl_s; - wire [11:0] adc_data_pl_i1_s; - wire [11:0] adc_data_pl_q1_s; - wire [11:0] adc_data_pl_i2_s; - wire [11:0] adc_data_pl_q2_s; - wire dac_valid_pl_s; - wire [11:0] dac_data_pl_i1_s; - wire [11:0] dac_data_pl_q1_s; - wire [11:0] dac_data_pl_i2_s; - wire [11:0] dac_data_pl_q2_s; - wire dac_lb_enb_i1_s; - wire dac_pn_enb_i1_s; - wire dac_lb_enb_q1_s; - wire dac_pn_enb_q1_s; - wire dac_lb_enb_i2_s; - wire dac_pn_enb_i2_s; - wire dac_lb_enb_q2_s; - wire dac_pn_enb_q2_s; - wire adc_lb_enb_i1_s; - wire adc_pn_oos_i1_s; - wire adc_pn_err_i1_s; - wire adc_lb_enb_q1_s; - wire adc_pn_oos_q1_s; - wire adc_pn_err_q1_s; - wire adc_lb_enb_i2_s; - wire adc_pn_oos_i2_s; - wire adc_pn_err_i2_s; - wire adc_lb_enb_q2_s; - wire adc_pn_oos_q2_s; - wire adc_pn_err_q2_s; wire up_sel_s; wire up_wr_s; wire [13:0] up_addr_s; @@ -351,17 +308,11 @@ module axi_ad9361 ( .l_clk (l_clk), .clk (clk), .adc_valid (adc_valid_s), - .adc_data_i1 (adc_data_i1_s), - .adc_data_q1 (adc_data_q1_s), - .adc_data_i2 (adc_data_i2_s), - .adc_data_q2 (adc_data_q2_s), + .adc_data (adc_data_s), .adc_status (adc_status_s), .adc_r1_mode (adc_r1_mode_s), .dac_valid (dac_valid_s), - .dac_data_i1 (dac_data_i1_s), - .dac_data_q1 (dac_data_q1_s), - .dac_data_i2 (dac_data_i2_s), - .dac_data_q2 (dac_data_q2_s), + .dac_data (dac_data_s), .dac_r1_mode (dac_r1_mode_s), .delay_clk (delay_clk), .delay_rst (delay_rst), @@ -375,51 +326,6 @@ module axi_ad9361 ( .dev_dbg_data (dev_dbg_data), .dev_l_dbg_data (dev_l_dbg_data)); - // prbs/loopback interface - - axi_ad9361_pnlb i_pnlb ( - .clk (clk), - .adc_valid_in (adc_valid_s), - .adc_data_in_i1 (adc_data_i1_s), - .adc_data_in_q1 (adc_data_q1_s), - .adc_data_in_i2 (adc_data_i2_s), - .adc_data_in_q2 (adc_data_q2_s), - .dac_valid_in (dac_valid_pl_s), - .dac_data_in_i1 (dac_data_pl_i1_s), - .dac_data_in_q1 (dac_data_pl_q1_s), - .dac_data_in_i2 (dac_data_pl_i2_s), - .dac_data_in_q2 (dac_data_pl_q2_s), - .adc_valid (adc_valid_pl_s), - .adc_data_i1 (adc_data_pl_i1_s), - .adc_data_q1 (adc_data_pl_q1_s), - .adc_data_i2 (adc_data_pl_i2_s), - .adc_data_q2 (adc_data_pl_q2_s), - .dac_valid (dac_valid_s), - .dac_data_i1 (dac_data_i1_s), - .dac_data_q1 (dac_data_q1_s), - .dac_data_i2 (dac_data_i2_s), - .dac_data_q2 (dac_data_q2_s), - .adc_lb_enb_i1 (adc_lb_enb_i1_s), - .dac_lb_enb_i1 (dac_lb_enb_i1_s), - .dac_pn_enb_i1 (dac_pn_enb_i1_s), - .adc_lb_enb_q1 (adc_lb_enb_q1_s), - .dac_lb_enb_q1 (dac_lb_enb_q1_s), - .dac_pn_enb_q1 (dac_pn_enb_q1_s), - .adc_lb_enb_i2 (adc_lb_enb_i2_s), - .dac_lb_enb_i2 (dac_lb_enb_i2_s), - .dac_pn_enb_i2 (dac_pn_enb_i2_s), - .adc_lb_enb_q2 (adc_lb_enb_q2_s), - .dac_lb_enb_q2 (dac_lb_enb_q2_s), - .dac_pn_enb_q2 (dac_pn_enb_q2_s), - .adc_pn_oos_i1 (adc_pn_oos_i1_s), - .adc_pn_err_i1 (adc_pn_err_i1_s), - .adc_pn_oos_q1 (adc_pn_oos_q1_s), - .adc_pn_err_q1 (adc_pn_err_q1_s), - .adc_pn_oos_i2 (adc_pn_oos_i2_s), - .adc_pn_err_i2 (adc_pn_err_i2_s), - .adc_pn_oos_q2 (adc_pn_oos_q2_s), - .adc_pn_err_q2 (adc_pn_err_q2_s)); - // receive axi_ad9361_rx #( @@ -427,25 +333,11 @@ module axi_ad9361 ( .DP_DISABLE (PCORE_ADC_DP_DISABLE)) i_rx ( .adc_clk (clk), - .adc_valid (adc_valid_pl_s), - .adc_data_i1 (adc_data_pl_i1_s), - .adc_data_q1 (adc_data_pl_q1_s), - .adc_data_i2 (adc_data_pl_i2_s), - .adc_data_q2 (adc_data_pl_q2_s), - .adc_lb_enb_i1 (adc_lb_enb_i1_s), - .adc_pn_oos_i1 (adc_pn_oos_i1_s), - .adc_pn_err_i1 (adc_pn_err_i1_s), - .adc_lb_enb_q1 (adc_lb_enb_q1_s), - .adc_pn_oos_q1 (adc_pn_oos_q1_s), - .adc_pn_err_q1 (adc_pn_err_q1_s), - .adc_lb_enb_i2 (adc_lb_enb_i2_s), - .adc_pn_oos_i2 (adc_pn_oos_i2_s), - .adc_pn_err_i2 (adc_pn_err_i2_s), - .adc_lb_enb_q2 (adc_lb_enb_q2_s), - .adc_pn_oos_q2 (adc_pn_oos_q2_s), - .adc_pn_err_q2 (adc_pn_err_q2_s), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), .adc_status (adc_status_s), .adc_r1_mode (adc_r1_mode_s), + .dac_data (dac_data_s), .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_sel (delay_sel_s), @@ -455,20 +347,20 @@ module axi_ad9361 ( .delay_rdata (delay_rdata_s), .delay_ack_t (delay_ack_t_s), .delay_locked (delay_locked_s), - .adc_chan_i1 (adc_chan_i1), - .adc_chan_q1 (adc_chan_q1), - .adc_chan_i2 (adc_chan_i2), - .adc_chan_q2 (adc_chan_q2), + .adc_enable_i0 (adc_enable_i0), + .adc_valid_i0 (adc_valid_i0), + .adc_data_i0 (adc_data_i0), + .adc_enable_q0 (adc_enable_q0), + .adc_valid_q0 (adc_valid_q0), + .adc_data_q0 (adc_data_q0), + .adc_enable_i1 (adc_enable_i1), + .adc_valid_i1 (adc_valid_i1), + .adc_data_i1 (adc_data_i1), + .adc_enable_q1 (adc_enable_q1), + .adc_valid_q1 (adc_valid_q1), + .adc_data_q1 (adc_data_q1), .adc_dovf (adc_dovf), .adc_dunf (adc_dunf), - .adc_enable_0 (adc_enable_0), - .adc_enable_1 (adc_enable_1), - .adc_enable_2 (adc_enable_2), - .adc_enable_3 (adc_enable_3), - .adc_valid_0(adc_valid_0), - .adc_valid_1(adc_valid_1), - .adc_valid_2(adc_valid_2), - .adc_valid_3(adc_valid_3), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel_s), @@ -476,11 +368,7 @@ module axi_ad9361 ( .up_addr (up_addr_s), .up_wdata (up_wdata_s), .up_rdata (up_rdata_rx_s), - .up_ack (up_ack_rx_s), - .adc_mon_valid (adc_mon_valid), - .adc_mon_data (adc_mon_data), - .adc_dbg_trigger (), - .adc_dbg_data ()); + .up_ack (up_ack_rx_s)); // transmit @@ -489,34 +377,24 @@ module axi_ad9361 ( .DP_DISABLE (PCORE_DAC_DP_DISABLE)) i_tx ( .dac_clk (clk), - .dac_valid (dac_valid_pl_s), - .dac_lb_enb_i1 (dac_lb_enb_i1_s), - .dac_pn_enb_i1 (dac_pn_enb_i1_s), - .dac_data_i1 (dac_data_pl_i1_s), - .dac_lb_enb_q1 (dac_lb_enb_q1_s), - .dac_pn_enb_q1 (dac_pn_enb_q1_s), - .dac_data_q1 (dac_data_pl_q1_s), - .dac_lb_enb_i2 (dac_lb_enb_i2_s), - .dac_pn_enb_i2 (dac_pn_enb_i2_s), - .dac_data_i2 (dac_data_pl_i2_s), - .dac_lb_enb_q2 (dac_lb_enb_q2_s), - .dac_pn_enb_q2 (dac_pn_enb_q2_s), - .dac_data_q2 (dac_data_pl_q2_s), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), .dac_r1_mode (dac_r1_mode_s), - .dac_enable_in (dac_enable_in), - .dac_enable_out (dac_enable_out), - .dac_drd_0(dac_drd_0), - .dac_drd_1(dac_drd_1), - .dac_drd_2(dac_drd_2), - .dac_drd_3(dac_drd_3), - .dac_enable_0(dac_enable_0), - .dac_enable_1(dac_enable_1), - .dac_enable_2(dac_enable_2), - .dac_enable_3(dac_enable_3), - .dac_data_0(dac_data_0), - .dac_data_1(dac_data_1), - .dac_data_2(dac_data_2), - .dac_data_3(dac_data_3), + .adc_data (adc_data_s), + .dac_sync_in (dac_sync_in), + .dac_sync_out (dac_sync_out), + .dac_enable_i0 (dac_enable_i0), + .dac_valid_i0 (dac_valid_i0), + .dac_data_i0 (dac_data_i0), + .dac_enable_q0 (dac_enable_q0), + .dac_valid_q0 (dac_valid_q0), + .dac_data_q0 (dac_data_q0), + .dac_enable_i1 (dac_enable_i1), + .dac_valid_i1 (dac_valid_i1), + .dac_data_i1 (dac_data_i1), + .dac_enable_q1 (dac_enable_q1), + .dac_valid_q1 (dac_valid_q1), + .dac_data_q1 (dac_data_q1), .dac_dovf(dac_dovf), .dac_dunf(dac_dunf), .up_rstn (up_rstn), diff --git a/library/axi_ad9361/axi_ad9361_dev_if.v b/library/axi_ad9361/axi_ad9361_dev_if.v index b89a5045c..6662d22fd 100755 --- a/library/axi_ad9361/axi_ad9361_dev_if.v +++ b/library/axi_ad9361/axi_ad9361_dev_if.v @@ -69,20 +69,14 @@ module axi_ad9361_dev_if ( // receive data path interface adc_valid, - adc_data_i1, - adc_data_q1, - adc_data_i2, - adc_data_q2, + adc_data, adc_status, adc_r1_mode, // transmit data path interface dac_valid, - dac_data_i1, - dac_data_q1, - dac_data_i2, - dac_data_q2, + dac_data, dac_r1_mode, // delay control signals @@ -135,20 +129,14 @@ module axi_ad9361_dev_if ( // receive data path interface output adc_valid; - output [11:0] adc_data_i1; - output [11:0] adc_data_q1; - output [11:0] adc_data_i2; - output [11:0] adc_data_q2; + output [47:0] adc_data; output adc_status; input adc_r1_mode; // transmit data path interface input dac_valid; - input [11:0] dac_data_i1; - input [11:0] dac_data_q1; - input [11:0] dac_data_i2; - input [11:0] dac_data_q2; + input [47:0] dac_data; input dac_r1_mode; // delay control signals @@ -178,37 +166,24 @@ module axi_ad9361_dev_if ( reg [ 1:0] rx_frame_d = 'd0; reg rx_error_r1 = 'd0; reg rx_valid_r1 = 'd0; - reg [11:0] rx_data_i_r1 = 'd0; - reg [11:0] rx_data_q_r1 = 'd0; + reg [23:0] rx_data_r1 = 'd0; reg rx_error_r2 = 'd0; reg rx_valid_r2 = 'd0; - reg [11:0] rx_data_i1_r2 = 'd0; - reg [11:0] rx_data_q1_r2 = 'd0; - reg [11:0] rx_data_i2_r2 = 'd0; - reg [11:0] rx_data_q2_r2 = 'd0; + reg [47:0] rx_data_r2 = 'd0; reg adc_p_valid = 'd0; - reg [11:0] adc_p_data_i1 = 'd0; - reg [11:0] adc_p_data_q1 = 'd0; - reg [11:0] adc_p_data_i2 = 'd0; - reg [11:0] adc_p_data_q2 = 'd0; + reg [47:0] adc_p_data = 'd0; reg adc_p_status = 'd0; reg adc_n_valid = 'd0; - reg [11:0] adc_n_data_i1 = 'd0; - reg [11:0] adc_n_data_q1 = 'd0; - reg [11:0] adc_n_data_i2 = 'd0; - reg [11:0] adc_n_data_q2 = 'd0; + reg [47:0] adc_n_data = 'd0; reg adc_n_status = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; reg adc_valid = 'd0; - reg [11:0] adc_data_i1 = 'd0; - reg [11:0] adc_data_q1 = 'd0; - reg [11:0] adc_data_i2 = 'd0; - reg [11:0] adc_data_q2 = 'd0; + reg [47:0] adc_data = 'd0; reg adc_status = 'd0; reg [ 2:0] tx_data_cnt = 'd0; - reg [11:0] tx_data_i1_d = 'd0; - reg [11:0] tx_data_q1_d = 'd0; - reg [11:0] tx_data_i2_d = 'd0; - reg [11:0] tx_data_q2_d = 'd0; + reg [47:0] tx_data = 'd0; reg tx_frame = 'd0; reg [ 5:0] tx_data_p = 'd0; reg [ 5:0] tx_data_n = 'd0; @@ -246,14 +221,14 @@ module axi_ad9361_dev_if ( assign dev_dbg_data[ 5: 0] = tx_data_n; assign dev_dbg_data[ 11: 6] = tx_data_p; - assign dev_dbg_data[ 23: 12] = dac_data_i1; - assign dev_dbg_data[ 35: 24] = dac_data_q1; - assign dev_dbg_data[ 47: 36] = dac_data_i2; - assign dev_dbg_data[ 59: 48] = dac_data_q2; - assign dev_dbg_data[ 71: 60] = adc_data_i1; - assign dev_dbg_data[ 83: 72] = adc_data_q1; - assign dev_dbg_data[ 95: 84] = adc_data_i2; - assign dev_dbg_data[107: 96] = adc_data_q2; + assign dev_dbg_data[ 23: 12] = dac_data[11: 0]; + assign dev_dbg_data[ 35: 24] = dac_data[23:12]; + assign dev_dbg_data[ 47: 36] = dac_data[35:24]; + assign dev_dbg_data[ 59: 48] = dac_data[47:36]; + assign dev_dbg_data[ 71: 60] = adc_data[11: 0]; + assign dev_dbg_data[ 83: 72] = adc_data[23:12]; + assign dev_dbg_data[ 95: 84] = adc_data[35:24]; + assign dev_dbg_data[107: 96] = adc_data[47:36]; assign dev_dbg_data[108:108] = tx_frame; assign dev_dbg_data[109:109] = dac_valid; assign dev_dbg_data[110:110] = adc_status; @@ -261,10 +236,10 @@ module axi_ad9361_dev_if ( assign dev_l_dbg_data[ 5: 0] = tx_p_data_n; assign dev_l_dbg_data[ 11: 6] = tx_p_data_p; - assign dev_l_dbg_data[ 23: 12] = adc_p_data_i1; - assign dev_l_dbg_data[ 35: 24] = adc_p_data_q1; - assign dev_l_dbg_data[ 47: 36] = adc_p_data_i2; - assign dev_l_dbg_data[ 59: 48] = adc_p_data_q2; + assign dev_l_dbg_data[ 23: 12] = adc_p_data[11: 0]; + assign dev_l_dbg_data[ 35: 24] = adc_p_data[23:12]; + assign dev_l_dbg_data[ 47: 36] = adc_p_data[35:24]; + assign dev_l_dbg_data[ 59: 48] = adc_p_data[47:36]; assign dev_l_dbg_data[ 60: 60] = tx_p_frame; assign dev_l_dbg_data[ 61: 61] = adc_p_valid; @@ -287,8 +262,8 @@ module axi_ad9361_dev_if ( rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0; if (rx_frame_s == 4'b1100) begin - rx_data_i_r1 <= {rx_data_d[11:6], rx_data[11:6]}; - rx_data_q_r1 <= {rx_data_d[ 5:0], rx_data[ 5:0]}; + rx_data_r1[11: 0] <= {rx_data_d[11:6], rx_data[11:6]}; + rx_data_r1[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]}; end end @@ -299,12 +274,12 @@ module axi_ad9361_dev_if ( (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0; if (rx_frame_s == 4'b1111) begin - rx_data_i1_r2 <= {rx_data_d[11:6], rx_data[11:6]}; - rx_data_q1_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]}; + rx_data_r2[11: 0] <= {rx_data_d[11:6], rx_data[11:6]}; + rx_data_r2[23:12] <= {rx_data_d[ 5:0], rx_data[ 5:0]}; end if (rx_frame_s == 4'b0000) begin - rx_data_i2_r2 <= {rx_data_d[11:6], rx_data[11:6]}; - rx_data_q2_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]}; + rx_data_r2[35:24] <= {rx_data_d[11:6], rx_data[11:6]}; + rx_data_r2[47:36] <= {rx_data_d[ 5:0], rx_data[ 5:0]}; end end @@ -313,17 +288,11 @@ module axi_ad9361_dev_if ( always @(posedge l_clk) begin if (adc_r1_mode == 1'b1) begin adc_p_valid <= rx_valid_r1; - adc_p_data_i1 <= rx_data_i_r1; - adc_p_data_q1 <= rx_data_q_r1; - adc_p_data_i2 <= 12'd0; - adc_p_data_q2 <= 12'd0; + adc_p_data <= {24'd0, rx_data_r1}; adc_p_status <= ~rx_error_r1; end else begin adc_p_valid <= rx_valid_r2; - adc_p_data_i1 <= rx_data_i1_r2; - adc_p_data_q1 <= rx_data_q1_r2; - adc_p_data_i2 <= rx_data_i2_r2; - adc_p_data_q2 <= rx_data_q2_r2; + adc_p_data <= rx_data_r2; adc_p_status <= ~rx_error_r2; end end @@ -332,20 +301,19 @@ module axi_ad9361_dev_if ( always @(negedge l_clk) begin adc_n_valid <= adc_p_valid; - adc_n_data_i1 <= adc_p_data_i1; - adc_n_data_q1 <= adc_p_data_q1; - adc_n_data_i2 <= adc_p_data_i2; - adc_n_data_q2 <= adc_p_data_q2; + adc_n_data <= adc_p_data; adc_n_status <= adc_p_status; end always @(posedge clk) begin - adc_valid <= adc_n_valid; - adc_data_i1 <= adc_n_data_i1; - adc_data_q1 <= adc_n_data_q1; - adc_data_i2 <= adc_n_data_i2; - adc_data_q2 <= adc_n_data_q2; - adc_status <= adc_n_status; + adc_valid_int <= adc_n_valid; + adc_data_int <= adc_n_data; + adc_status_int <= adc_n_status; + adc_valid <= adc_valid_int; + if (adc_valid_int == 1'b1) begin + adc_data <= adc_data_int; + end + adc_status <= adc_status_int; end // transmit data path mux (reverse of what receive does above) @@ -360,51 +328,48 @@ module axi_ad9361_dev_if ( tx_data_cnt <= tx_data_cnt + 1'b1; end if (dac_valid == 1'b1) begin - tx_data_i1_d <= dac_data_i1; - tx_data_q1_d <= dac_data_q1; - tx_data_i2_d <= dac_data_i2; - tx_data_q2_d <= dac_data_q2; + tx_data <= dac_data; end case (tx_data_sel_s) 4'b1111: begin tx_frame <= 1'b0; - tx_data_p <= tx_data_i1_d[ 5:0]; - tx_data_n <= tx_data_q1_d[ 5:0]; + tx_data_p <= tx_data[ 5: 0]; + tx_data_n <= tx_data[17:12]; end 4'b1110: begin tx_frame <= 1'b1; - tx_data_p <= tx_data_i1_d[11:6]; - tx_data_n <= tx_data_q1_d[11:6]; + tx_data_p <= tx_data[11: 6]; + tx_data_n <= tx_data[23:18]; end 4'b1101: begin tx_frame <= 1'b0; - tx_data_p <= tx_data_i1_d[ 5:0]; - tx_data_n <= tx_data_q1_d[ 5:0]; + tx_data_p <= tx_data[ 5: 0]; + tx_data_n <= tx_data[17:12]; end 4'b1100: begin tx_frame <= 1'b1; - tx_data_p <= tx_data_i1_d[11:6]; - tx_data_n <= tx_data_q1_d[11:6]; + tx_data_p <= tx_data[11: 6]; + tx_data_n <= tx_data[23:18]; end 4'b1011: begin tx_frame <= 1'b0; - tx_data_p <= tx_data_i2_d[ 5:0]; - tx_data_n <= tx_data_q2_d[ 5:0]; + tx_data_p <= tx_data[29:24]; + tx_data_n <= tx_data[41:36]; end 4'b1010: begin tx_frame <= 1'b0; - tx_data_p <= tx_data_i2_d[11:6]; - tx_data_n <= tx_data_q2_d[11:6]; + tx_data_p <= tx_data[35:30]; + tx_data_n <= tx_data[47:42]; end 4'b1001: begin tx_frame <= 1'b1; - tx_data_p <= tx_data_i1_d[ 5:0]; - tx_data_n <= tx_data_q1_d[ 5:0]; + tx_data_p <= tx_data[ 5: 0]; + tx_data_n <= tx_data[17:12]; end 4'b1000: begin tx_frame <= 1'b1; - tx_data_p <= tx_data_i1_d[11:6]; - tx_data_n <= tx_data_q1_d[11:6]; + tx_data_p <= tx_data[11: 6]; + tx_data_n <= tx_data[23:18]; end default: begin tx_frame <= 1'b0; diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index f212e930b..7aaab498a 100755 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -6,7 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9361 adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_mul_u16.v" \ + "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ @@ -24,12 +25,9 @@ adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/up_dac_common.v" \ "$ad_hdl_dir/library/common/up_dac_channel.v" \ "axi_ad9361_dev_if.v" \ - "axi_ad9361_pnlb_1.v" \ - "axi_ad9361_pnlb.v" \ "axi_ad9361_rx_pnmon.v" \ "axi_ad9361_rx_channel.v" \ "axi_ad9361_rx.v" \ - "axi_ad9361_tx_dds.v" \ "axi_ad9361_tx_channel.v" \ "axi_ad9361_tx.v" \ "axi_ad9361.v" ] diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index 3d28e0c01..0f9873358 100755 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -46,24 +46,10 @@ module axi_ad9361_rx ( adc_clk, adc_valid, - adc_data_i1, - adc_data_q1, - adc_data_i2, - adc_data_q2, - adc_lb_enb_i1, - adc_pn_oos_i1, - adc_pn_err_i1, - adc_lb_enb_q1, - adc_pn_oos_q1, - adc_pn_err_q1, - adc_lb_enb_i2, - adc_pn_oos_i2, - adc_pn_err_i2, - adc_lb_enb_q2, - adc_pn_oos_q2, - adc_pn_err_q2, + adc_data, adc_status, adc_r1_mode, + dac_data, // delay interface @@ -79,18 +65,18 @@ module axi_ad9361_rx ( // dma interface - adc_chan_i1, - adc_enable_0, - adc_valid_0, - adc_chan_q1, - adc_enable_1, - adc_valid_1, - adc_chan_i2, - adc_enable_2, - adc_valid_2, - adc_chan_q2, - adc_enable_3, - adc_valid_3, + adc_enable_i0, + adc_valid_i0, + adc_data_i0, + adc_enable_q0, + adc_valid_q0, + adc_data_q0, + adc_enable_i1, + adc_valid_i1, + adc_data_i1, + adc_enable_q1, + adc_valid_q1, + adc_data_q1, adc_dovf, adc_dunf, @@ -103,17 +89,7 @@ module axi_ad9361_rx ( up_addr, up_wdata, up_rdata, - up_ack, - - // monitor signals - - adc_mon_valid, - adc_mon_data, - - // debug signals - - adc_dbg_trigger, - adc_dbg_data); + up_ack); // parameters @@ -124,24 +100,10 @@ module axi_ad9361_rx ( input adc_clk; input adc_valid; - input [11:0] adc_data_i1; - input [11:0] adc_data_q1; - input [11:0] adc_data_i2; - input [11:0] adc_data_q2; - output adc_lb_enb_i1; - input adc_pn_oos_i1; - input adc_pn_err_i1; - output adc_lb_enb_q1; - input adc_pn_oos_q1; - input adc_pn_err_q1; - output adc_lb_enb_i2; - input adc_pn_oos_i2; - input adc_pn_err_i2; - output adc_lb_enb_q2; - input adc_pn_oos_q2; - input adc_pn_err_q2; + input [47:0] adc_data; input adc_status; output adc_r1_mode; + input [47:0] dac_data; // delay interface @@ -157,18 +119,18 @@ module axi_ad9361_rx ( // dma interface - output [15:0] adc_chan_i1; - output adc_enable_0; - output adc_valid_0; - output [15:0] adc_chan_q1; - output adc_enable_1; - output adc_valid_1; - output [15:0] adc_chan_i2; - output adc_enable_2; - output adc_valid_2; - output [15:0] adc_chan_q2; - output adc_enable_3; - output adc_valid_3; + output adc_enable_i0; + output adc_valid_i0; + output [15:0] adc_data_i0; + output adc_enable_q0; + output adc_valid_q0; + output [15:0] adc_data_q0; + output adc_enable_i1; + output adc_valid_i1; + output [15:0] adc_data_i1; + output adc_enable_q1; + output adc_valid_q1; + output [15:0] adc_data_q1; input adc_dovf; input adc_dunf; @@ -183,23 +145,11 @@ module axi_ad9361_rx ( output [31:0] up_rdata; output up_ack; - // monitor signals - - output adc_mon_valid; - output [47:0] adc_mon_data; - - // debug signals - - output [ 1:0] adc_dbg_trigger; - output [116:0] adc_dbg_data; - // internal registers - - reg adc_iqcor_valid = 'd0; - reg up_adc_status_pn_err = 'd0; - reg up_adc_status_pn_oos = 'd0; - reg up_adc_status_or = 'd0; + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; reg [31:0] up_rdata = 'd0; reg up_ack = 'd0; @@ -209,90 +159,31 @@ module axi_ad9361_rx ( // internal signals - wire adc_iqcor_valid_s; wire [15:0] adc_dcfilter_data_out_0_s; - wire adc_pn_oos_out_0_s; - wire adc_pn_err_out_0_s; - wire up_adc_pn_err_0_s; - wire up_adc_pn_oos_0_s; - wire up_adc_or_0_s; - wire [31:0] up_rdata_0_s; - wire up_ack_0_s; wire [15:0] adc_dcfilter_data_out_1_s; - wire up_adc_pn_err_1_s; - wire up_adc_pn_oos_1_s; - wire up_adc_or_1_s; - wire [31:0] up_rdata_1_s; - wire up_ack_1_s; wire [15:0] adc_dcfilter_data_out_2_s; - wire adc_pn_oos_out_2_s; - wire adc_pn_err_out_2_s; - wire up_adc_pn_err_2_s; - wire up_adc_pn_oos_2_s; - wire up_adc_or_2_s; - wire [31:0] up_rdata_2_s; - wire up_ack_2_s; wire [15:0] adc_dcfilter_data_out_3_s; - wire up_adc_pn_err_3_s; - wire up_adc_pn_oos_3_s; - wire up_adc_or_3_s; - wire [31:0] up_rdata_3_s; - wire up_ack_3_s; - wire [31:0] up_rdata_s; - wire up_ack_s; - - // monitor signals - - assign adc_mon_valid = adc_valid; - assign adc_mon_data[11: 0] = adc_data_i1; - assign adc_mon_data[23:12] = adc_data_q1; - assign adc_mon_data[35:24] = adc_data_i2; - assign adc_mon_data[47:36] = adc_data_q2; - - // debug signals - - assign adc_dbg_trigger[0] = adc_iqcor_valid_s; - assign adc_dbg_trigger[1] = adc_valid; - - assign adc_dbg_data[ 15: 0] = adc_chan_i1; - assign adc_dbg_data[ 31: 16] = adc_chan_q1; - assign adc_dbg_data[ 47: 32] = adc_chan_i2; - assign adc_dbg_data[ 63: 48] = adc_chan_q2; - assign adc_dbg_data[ 64: 64] = adc_valid_0; - assign adc_dbg_data[ 65: 65] = adc_valid_1; - assign adc_dbg_data[ 66: 66] = adc_valid_2; - assign adc_dbg_data[ 67: 67] = adc_valid_3; - assign adc_dbg_data[ 79: 68] = adc_data_i1; - assign adc_dbg_data[ 91: 80] = adc_data_q1; - assign adc_dbg_data[103: 92] = adc_data_i2; - assign adc_dbg_data[115:104] = adc_data_q2; - assign adc_dbg_data[116:116] = adc_valid; - - // adc channels - dma interface - - assign adc_iqcor_valid_s = adc_valid_0 & adc_valid_1 & - adc_valid_2 & adc_valid_3; + wire [ 3:0] up_adc_pn_err_s; + wire [ 3:0] up_adc_pn_oos_s; + wire [ 3:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:4]; + wire up_ack_s[0:4]; // processor read interface always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_adc_status_pn_err <= 'd0; - up_adc_status_pn_oos <= 'd0; - up_adc_status_or <= 'd0; + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; up_rdata <= 'd0; up_ack <= 'd0; end else begin - up_adc_status_pn_err <= up_adc_pn_err_0_s | up_adc_pn_err_1_s | - up_adc_pn_err_2_s | up_adc_pn_err_3_s; - up_adc_status_pn_oos <= up_adc_pn_oos_0_s | up_adc_pn_oos_1_s | - up_adc_pn_oos_2_s | up_adc_pn_oos_3_s; - up_adc_status_or <= up_adc_or_0_s | up_adc_or_1_s | - up_adc_or_2_s | up_adc_or_3_s; - up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s | - up_rdata_2_s | up_rdata_3_s; - up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s | - up_ack_2_s | up_ack_3_s; + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4]; + up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2] | up_ack_s[3] | up_ack_s[4]; end end @@ -306,32 +197,26 @@ module axi_ad9361_rx ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_valid (adc_valid), - .adc_pn_oos_pl (adc_pn_oos_i1), - .adc_pn_err_pl (adc_pn_err_i1), - .adc_data (adc_data_i1), - .adc_data_q (adc_data_q1), + .adc_data (adc_data[11:0]), + .adc_data_q (adc_data[23:12]), .adc_or (1'b0), + .dac_data (dac_data[11:0]), .adc_dcfilter_data_out (adc_dcfilter_data_out_0_s), - .adc_pn_oos_out (adc_pn_oos_out_0_s), - .adc_pn_err_out (adc_pn_err_out_0_s), .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s), - .adc_pn_oos_in (1'd0), - .adc_pn_err_in (1'd0), - .adc_iqcor_valid (adc_valid_0), - .adc_iqcor_data (adc_chan_i1), - .adc_enable (adc_enable_0), - .adc_lb_enb (adc_lb_enb_i1), - .up_adc_pn_err (up_adc_pn_err_0_s), - .up_adc_pn_oos (up_adc_pn_oos_0_s), - .up_adc_or (up_adc_or_0_s), + .adc_iqcor_valid (adc_valid_i0), + .adc_iqcor_data (adc_data_i0), + .adc_enable (adc_enable_i0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_0_s), - .up_ack (up_ack_0_s)); + .up_rdata (up_rdata_s[0]), + .up_ack (up_ack_s[0])); // channel 1 (q) @@ -343,32 +228,26 @@ module axi_ad9361_rx ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_valid (adc_valid), - .adc_pn_oos_pl (adc_pn_oos_q1), - .adc_pn_err_pl (adc_pn_err_q1), - .adc_data (adc_data_q1), - .adc_data_q (12'd0), + .adc_data (adc_data[23:12]), + .adc_data_q (adc_data[11:0]), .adc_or (1'b0), + .dac_data (dac_data[23:12]), .adc_dcfilter_data_out (adc_dcfilter_data_out_1_s), - .adc_pn_oos_out (), - .adc_pn_err_out (), .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s), - .adc_pn_oos_in (adc_pn_oos_out_0_s), - .adc_pn_err_in (adc_pn_err_out_0_s), - .adc_iqcor_valid (adc_valid_1), - .adc_iqcor_data (adc_chan_q1), - .adc_enable (adc_enable_1), - .adc_lb_enb (adc_lb_enb_q1), - .up_adc_pn_err (up_adc_pn_err_1_s), - .up_adc_pn_oos (up_adc_pn_oos_1_s), - .up_adc_or (up_adc_or_1_s), + .adc_iqcor_valid (adc_valid_q0), + .adc_iqcor_data (adc_data_q0), + .adc_enable (adc_enable_q0), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_1_s), - .up_ack (up_ack_1_s)); + .up_rdata (up_rdata_s[1]), + .up_ack (up_ack_s[1])); // channel 2 (i) @@ -380,32 +259,26 @@ module axi_ad9361_rx ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_valid (adc_valid), - .adc_pn_oos_pl (adc_pn_oos_i2), - .adc_pn_err_pl (adc_pn_err_i2), - .adc_data (adc_data_i2), - .adc_data_q (adc_data_q2), + .adc_data (adc_data[35:24]), + .adc_data_q (adc_data[47:36]), .adc_or (1'b0), + .dac_data (dac_data[35:24]), .adc_dcfilter_data_out (adc_dcfilter_data_out_2_s), - .adc_pn_oos_out (adc_pn_oos_out_2_s), - .adc_pn_err_out (adc_pn_err_out_2_s), .adc_dcfilter_data_in (adc_dcfilter_data_out_3_s), - .adc_pn_oos_in (1'd0), - .adc_pn_err_in (1'd0), - .adc_iqcor_valid (adc_valid_2), - .adc_iqcor_data (adc_chan_i2), - .adc_enable (adc_enable_2), - .adc_lb_enb (adc_lb_enb_i2), - .up_adc_pn_err (up_adc_pn_err_2_s), - .up_adc_pn_oos (up_adc_pn_oos_2_s), - .up_adc_or (up_adc_or_2_s), + .adc_iqcor_valid (adc_valid_i1), + .adc_iqcor_data (adc_data_i1), + .adc_enable (adc_enable_i1), + .up_adc_pn_err (up_adc_pn_err_s[2]), + .up_adc_pn_oos (up_adc_pn_oos_s[2]), + .up_adc_or (up_adc_or_s[2]), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_2_s), - .up_ack (up_ack_2_s)); + .up_rdata (up_rdata_s[2]), + .up_ack (up_ack_s[2])); // channel 3 (q) @@ -417,32 +290,26 @@ module axi_ad9361_rx ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_valid (adc_valid), - .adc_pn_oos_pl (adc_pn_oos_q2), - .adc_pn_err_pl (adc_pn_err_q2), - .adc_data (adc_data_q2), - .adc_data_q (12'd0), + .adc_data (adc_data[47:36]), + .adc_data_q (adc_data[35:24]), .adc_or (1'b0), + .dac_data (dac_data[47:36]), .adc_dcfilter_data_out (adc_dcfilter_data_out_3_s), - .adc_pn_oos_out (), - .adc_pn_err_out (), .adc_dcfilter_data_in (adc_dcfilter_data_out_2_s), - .adc_pn_oos_in (adc_pn_oos_out_2_s), - .adc_pn_err_in (adc_pn_err_out_2_s), - .adc_iqcor_valid (adc_valid_3), - .adc_iqcor_data (adc_chan_q2), - .adc_enable (adc_enable_3), - .adc_lb_enb (adc_lb_enb_q2), - .up_adc_pn_err (up_adc_pn_err_3_s), - .up_adc_pn_oos (up_adc_pn_oos_3_s), - .up_adc_or (up_adc_or_3_s), + .adc_iqcor_valid (adc_valid_q1), + .adc_iqcor_data (adc_data_q1), + .adc_enable (adc_enable_q1), + .up_adc_pn_err (up_adc_pn_err_s[3]), + .up_adc_pn_oos (up_adc_pn_oos_s[3]), + .up_adc_or (up_adc_or_s[3]), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_3_s), - .up_ack (up_ack_3_s)); + .up_rdata (up_rdata_s[3]), + .up_ack (up_ack_s[3])); // common processor control @@ -454,12 +321,12 @@ module axi_ad9361_rx ( .adc_ddr_edgesel (), .adc_pin_mode (), .adc_status (adc_status), - .adc_status_pn_err (up_adc_status_pn_err), - .adc_status_pn_oos (up_adc_status_pn_oos), - .adc_status_or (up_adc_status_or), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), .adc_clk_ratio (32'd1), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_sel (delay_sel), @@ -486,8 +353,8 @@ module axi_ad9361_rx ( .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_s), - .up_ack (up_ack_s)); + .up_rdata (up_rdata_s[4]), + .up_ack (up_ack_s[4])); endmodule diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v index ce8e2d423..a16bd684e 100755 --- a/library/axi_ad9361/axi_ad9361_rx_channel.v +++ b/library/axi_ad9361/axi_ad9361_rx_channel.v @@ -47,24 +47,18 @@ module axi_ad9361_rx_channel ( adc_clk, adc_rst, adc_valid, - adc_pn_oos_pl, - adc_pn_err_pl, adc_data, adc_data_q, adc_or, + dac_data, // channel interface adc_dcfilter_data_out, - adc_pn_oos_out, - adc_pn_err_out, adc_dcfilter_data_in, - adc_pn_oos_in, - adc_pn_err_in, adc_iqcor_valid, adc_iqcor_data, adc_enable, - adc_lb_enb, up_adc_pn_err, up_adc_pn_oos, up_adc_or, @@ -91,24 +85,18 @@ module axi_ad9361_rx_channel ( input adc_clk; input adc_rst; input adc_valid; - input adc_pn_oos_pl; - input adc_pn_err_pl; input [11:0] adc_data; input [11:0] adc_data_q; input adc_or; + input [11:0] dac_data; // channel interface output [15:0] adc_dcfilter_data_out; - output adc_pn_oos_out; - output adc_pn_err_out; input [15:0] adc_dcfilter_data_in; - input adc_pn_oos_in; - input adc_pn_err_in; output adc_iqcor_valid; output [15:0] adc_iqcor_data; output adc_enable; - output adc_lb_enb; output up_adc_pn_err; output up_adc_pn_oos; output up_adc_or; @@ -126,12 +114,12 @@ module axi_ad9361_rx_channel ( // internal signals + wire [11:0] adc_data_s; wire adc_dfmt_valid_s; wire [15:0] adc_dfmt_data_s; wire adc_dcfilter_valid_s; wire [15:0] adc_dcfilter_data_i_s; wire [15:0] adc_dcfilter_data_q_s; - wire adc_pn_sel_s; wire adc_iqcor_enb_s; wire adc_dcfilt_enb_s; wire adc_dfmt_se_s; @@ -141,40 +129,35 @@ module axi_ad9361_rx_channel ( wire [15:0] adc_dcfilt_coeff_s; wire [15:0] adc_iqcor_coeff_1_s; wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; wire adc_pn_err_s; wire adc_pn_oos_s; // iq correction inputs + assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data; assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out; assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in; - assign adc_pn_oos_s = (adc_pn_sel_s == 1'b1) ? adc_pn_oos_pl : ((IQSEL == 1) ? adc_pn_oos_in : adc_pn_oos_out); - assign adc_pn_err_s = (adc_pn_sel_s == 1'b1) ? adc_pn_err_pl : ((IQSEL == 1) ? adc_pn_err_in : adc_pn_err_out); - generate - if (IQSEL == 1) begin - assign adc_pn_oos_out = 1'b1; - assign adc_pn_err_out = 1'b1; - end else begin - axi_ad9361_rx_pnmon i_rx_pnmon ( + axi_ad9361_rx_pnmon #(.IQSEL (IQSEL), .PRBS_SEL (CHID)) i_rx_pnmon ( .adc_clk (adc_clk), .adc_valid (adc_valid), .adc_data_i (adc_data), .adc_data_q (adc_data_q), - .adc_pn_oos (adc_pn_oos_out), - .adc_pn_err (adc_pn_err_out)); - end - endgenerate + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s)); generate if (DP_DISABLE == 1) begin assign adc_dfmt_valid_s = adc_valid; - assign adc_dfmt_data_s = {4'd0, adc_data}; + assign adc_dfmt_data_s = {4'd0, adc_data_s}; end else begin - ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt ( + ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt ( .clk (adc_clk), .valid (adc_valid), - .data (adc_data), + .data (adc_data_s), .valid_out (adc_dfmt_valid_s), .data_out (adc_dfmt_data_s), .dfmt_enable (adc_dfmt_enable_s), @@ -205,7 +188,7 @@ module axi_ad9361_rx_channel ( assign adc_iqcor_valid = adc_dcfilter_valid_s; assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s; end else begin - ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor ( + ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor ( .clk (adc_clk), .valid (adc_dcfilter_valid_s), .data_i (adc_dcfilter_data_i_s), @@ -218,22 +201,21 @@ module axi_ad9361_rx_channel ( end endgenerate - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + up_adc_channel #(.PCORE_ADC_CHID (CHID)) i_up_adc_channel ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_enable (adc_enable), - .adc_lb_enb (adc_lb_enb), - .adc_pn_sel (adc_pn_sel_s), .adc_iqcor_enb (adc_iqcor_enb_s), .adc_dcfilt_enb (adc_dcfilt_enb_s), .adc_dfmt_se (adc_dfmt_se_s), .adc_dfmt_type (adc_dfmt_type_s), .adc_dfmt_enable (adc_dfmt_enable_s), - .adc_pn_type (), .adc_dcfilt_offset (adc_dcfilt_offset_s), .adc_dcfilt_coeff (adc_dcfilt_coeff_s), .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (adc_data_sel_s), .adc_pn_err (adc_pn_err_s), .adc_pn_oos (adc_pn_oos_s), .adc_or (adc_or), diff --git a/library/axi_ad9361/axi_ad9361_rx_pnmon.v b/library/axi_ad9361/axi_ad9361_rx_pnmon.v index d858310f1..b01868be3 100755 --- a/library/axi_ad9361/axi_ad9361_rx_pnmon.v +++ b/library/axi_ad9361/axi_ad9361_rx_pnmon.v @@ -51,9 +51,19 @@ module axi_ad9361_rx_pnmon ( // pn out of sync and error + adc_pnseq_sel, adc_pn_oos, adc_pn_err); + // parameters + + parameter IQSEL = 0; + parameter PRBS_SEL = 0; + localparam PRBS_P09 = 0; + localparam PRBS_P11 = 1; + localparam PRBS_P15 = 2; + localparam PRBS_P20 = 3; + // adc interface input adc_clk; @@ -63,45 +73,36 @@ module axi_ad9361_rx_pnmon ( // pn out of sync and error + input [ 3:0] adc_pnseq_sel; output adc_pn_oos; output adc_pn_err; // internal registers - reg [15:0] adc_data = 'd0; - reg [15:0] adc_pn_data = 'd0; - reg adc_valid_d = 'd0; - reg adc_iq_match = 'd0; - reg adc_pn_match_d = 'd0; - reg adc_pn_match_z = 'd0; - reg adc_pn_err = 'd0; - reg [ 6:0] adc_pn_oos_count = 'd0; - reg adc_pn_oos = 'd0; + reg adc_pn0_valid = 'd0; + reg [15:0] adc_pn0_data = 'd0; + reg adc_pn0_valid_in = 'd0; + reg [15:0] adc_pn0_data_in = 'd0; + reg [15:0] adc_pn0_data_pn = 'd0; + reg adc_pn1_valid_t = 'd0; + reg [11:0] adc_pn1_data_d = 'd0; + reg adc_pn1_valid_in = 'd0; + reg [23:0] adc_pn1_data_in = 'd0; + reg [23:0] adc_pn1_data_pn = 'd0; + reg adc_pn_valid_in = 'd0; + reg [23:0] adc_pn_data_in = 'd0; + reg [23:0] adc_pn_data_pn = 'd0; // internal signals - wire [11:0] adc_data_i_s; - wire [11:0] adc_data_q_s; - wire [11:0] adc_data_q_rev_s; - wire [15:0] adc_data_s; - wire adc_iq_match_s; - wire [15:0] adc_pn_data_s; - wire adc_pn_match_d_s; - wire adc_pn_match_z_s; - wire adc_pn_match_s; - wire adc_pn_update_s; - wire adc_pn_err_s; - - // prbs function - - function [15:0] pnfn; - input [15:0] din; - reg [15:0] dout; - begin - dout = {din[14:0], ~((^din[15:4]) ^ (^din[2:1]))}; - pnfn = dout; - end - endfunction + wire [11:0] adc_pn0_data_i_s; + wire [11:0] adc_pn0_data_q_s; + wire [11:0] adc_pn0_data_q_rev_s; + wire [15:0] adc_pn0_data_s; + wire adc_pn0_iq_match_s; + wire [15:0] adc_pn0_data_pn_s; + wire adc_pn1_valid_s; + wire [23:0] adc_pn1_data_pn_s; // bit reversal function @@ -125,59 +126,193 @@ module axi_ad9361_rx_pnmon ( end endfunction - // assuming lower nibble is lost- + // device-specific prbs function - assign adc_data_i_s = ~adc_data_i; - assign adc_data_q_s = ~adc_data_q; - assign adc_data_q_rev_s = brfn(adc_data_q_s); - assign adc_data_s = {adc_data_i_s, adc_data_q_rev_s[3:0]}; - assign adc_iq_match_s = (adc_data_i_s[7:0] == adc_data_q_rev_s[11:4]) ? 1'b1 : 1'b0; + function [15:0] pn0fn; + input [15:0] din; + reg [15:0] dout; + begin + dout = {din[14:0], ((^din[15:4]) ^ (^din[2:1]))}; + pn0fn = dout; + end + endfunction - // pn sequence checking algorithm is commonly used in most applications. - // if oos is asserted (pn is out of sync): - // next sequence is generated from the incoming data. - // if 64 sequences match consecutively, oos is cleared (de-asserted). - // if oos is de-asserted (pn is in sync) - // next sequence is generated from the current sequence. - // if 64 sequences mismatch consecutively, oos is set (asserted). - // if oos is de-asserted, any spurious mismatches sets the error register. - // ideally, processor should make sure both oos == 0x0 and err == 0x0. + // standard prbs functions - assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_data_s : adc_pn_data; - assign adc_pn_match_d_s = (adc_data_s == adc_pn_data) ? 1'b1 : 1'b0; - assign adc_pn_match_z_s = (adc_data_s == adc_data) ? 1'b0 : 1'b1; - assign adc_pn_match_s = adc_iq_match & adc_pn_match_d & adc_pn_match_z; - assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s); - assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s); + function [23:0] pn1fn; + input [23:0] din; + reg [23:0] dout; + begin + case (PRBS_SEL) + PRBS_P09: begin + dout[23] = din[ 8] ^ din[ 4]; + dout[22] = din[ 7] ^ din[ 3]; + dout[21] = din[ 6] ^ din[ 2]; + dout[20] = din[ 5] ^ din[ 1]; + dout[19] = din[ 4] ^ din[ 0]; + dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[14] = din[ 8] ^ din[ 0]; + dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + end + PRBS_P11: begin + dout[23] = din[10] ^ din[ 8]; + dout[22] = din[ 9] ^ din[ 7]; + dout[21] = din[ 8] ^ din[ 6]; + dout[20] = din[ 7] ^ din[ 5]; + dout[19] = din[ 6] ^ din[ 4]; + dout[18] = din[ 5] ^ din[ 3]; + dout[17] = din[ 4] ^ din[ 2]; + dout[16] = din[ 3] ^ din[ 1]; + dout[15] = din[ 2] ^ din[ 0]; + dout[14] = din[ 1] ^ din[10] ^ din[ 8]; + dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; + dout[12] = din[10] ^ din[ 6]; + dout[11] = din[ 9] ^ din[ 5]; + dout[10] = din[ 8] ^ din[ 4]; + dout[ 9] = din[ 7] ^ din[ 3]; + dout[ 8] = din[ 6] ^ din[ 2]; + dout[ 7] = din[ 5] ^ din[ 1]; + dout[ 6] = din[ 4] ^ din[ 0]; + dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; + dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; + dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; + dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; + dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + end + PRBS_P15: begin + dout[23] = din[14] ^ din[13]; + dout[22] = din[13] ^ din[12]; + dout[21] = din[12] ^ din[11]; + dout[20] = din[11] ^ din[10]; + dout[19] = din[10] ^ din[ 9]; + dout[18] = din[ 9] ^ din[ 8]; + dout[17] = din[ 8] ^ din[ 7]; + dout[16] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[14] ^ din[13]; + dout[ 8] = din[14] ^ din[12]; + dout[ 7] = din[13] ^ din[11]; + dout[ 6] = din[12] ^ din[10]; + dout[ 5] = din[11] ^ din[ 9]; + dout[ 4] = din[10] ^ din[ 8]; + dout[ 3] = din[ 9] ^ din[ 7]; + dout[ 2] = din[ 8] ^ din[ 6]; + dout[ 1] = din[ 7] ^ din[ 5]; + dout[ 0] = din[ 6] ^ din[ 4]; + end + PRBS_P20: begin + dout[23] = din[19] ^ din[ 2]; + dout[22] = din[18] ^ din[ 1]; + dout[21] = din[17] ^ din[ 0]; + dout[20] = din[16] ^ din[19] ^ din[ 2]; + dout[19] = din[15] ^ din[18] ^ din[ 1]; + dout[18] = din[14] ^ din[17] ^ din[ 0]; + dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + end + endcase + pn1fn = dout; + end + endfunction - // pn oos and counters (64 to clear and set). + // device specific, assuming lower nibble is lost- + + assign adc_pn0_data_i_s = (IQSEL == 1) ? adc_data_q : adc_data_i; + assign adc_pn0_data_q_s = (IQSEL == 1) ? adc_data_i : adc_data_q; + assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s); + assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]}; + assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0; + assign adc_pn0_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn0_data_in : adc_pn0_data_pn; + + always @(posedge adc_clk) begin + adc_pn0_valid <= adc_valid; + adc_pn0_data <= (adc_pn0_iq_match_s == 1'b0) ? 16'hdead : adc_pn0_data_s; + adc_pn0_valid_in <= adc_pn0_valid; + if (adc_pn0_valid == 1'b1) begin + adc_pn0_data_in <= adc_pn0_data; + adc_pn0_data_pn <= pn0fn(adc_pn0_data_pn_s); + end + end + + // standard, runs on 24bit + + assign adc_pn1_valid_s = adc_pn1_valid_t & adc_valid; + assign adc_pn1_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn1_data_in : adc_pn1_data_pn; always @(posedge adc_clk) begin if (adc_valid == 1'b1) begin - adc_data <= adc_data_s; - adc_pn_data <= pnfn(adc_pn_data_s); + adc_pn1_valid_t <= ~adc_pn1_valid_t; + adc_pn1_data_d <= adc_data_i; end - adc_valid_d <= adc_valid; - adc_iq_match <= adc_iq_match_s; - adc_pn_match_d <= adc_pn_match_d_s; - adc_pn_match_z <= adc_pn_match_z_s; - if (adc_valid_d == 1'b1) begin - adc_pn_err <= adc_pn_err_s; - if (adc_pn_update_s == 1'b1) begin - if (adc_pn_oos_count >= 16) begin - adc_pn_oos_count <= 'd0; - adc_pn_oos <= ~adc_pn_oos; - end else begin - adc_pn_oos_count <= adc_pn_oos_count + 1'b1; - adc_pn_oos <= adc_pn_oos; - end - end else begin - adc_pn_oos_count <= 'd0; - adc_pn_oos <= adc_pn_oos; - end + adc_pn1_valid_in <= adc_pn1_valid_s; + if (adc_pn1_valid_s == 1'b1) begin + adc_pn1_data_in <= {adc_pn1_data_d, adc_data_i}; + adc_pn1_data_pn <= pn1fn(adc_pn1_data_pn_s); end end + // pn mux + + always @(posedge adc_clk) begin + if (adc_pnseq_sel == 4'h9) begin + adc_pn_valid_in <= adc_pn1_valid_in; + adc_pn_data_in <= adc_pn1_data_in; + adc_pn_data_pn <= adc_pn1_data_pn; + end else begin + adc_pn_valid_in <= adc_pn0_valid_in; + adc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in}; + adc_pn_data_pn <= {adc_pn0_data_pn[7:0], adc_pn0_data_pn}; + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(24)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_pn_valid_in), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + endmodule // *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index e3ce60e5f..c8b8fd48a 100755 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -45,39 +45,29 @@ module axi_ad9361_tx ( dac_clk, dac_valid, - dac_lb_enb_i1, - dac_pn_enb_i1, - dac_data_i1, - dac_lb_enb_q1, - dac_pn_enb_q1, - dac_data_q1, - dac_lb_enb_i2, - dac_pn_enb_i2, - dac_data_i2, - dac_lb_enb_q2, - dac_pn_enb_q2, - dac_data_q2, + dac_data, dac_r1_mode, + adc_data, // master/slave - dac_enable_in, - dac_enable_out, + dac_sync_in, + dac_sync_out, // dma interface - dac_data_0, - dac_enable_0, - dac_drd_0, - dac_data_1, - dac_enable_1, - dac_drd_1, - dac_data_2, - dac_enable_2, - dac_drd_2, - dac_data_3, - dac_enable_3, - dac_drd_3, + dac_enable_i0, + dac_valid_i0, + dac_data_i0, + dac_enable_q0, + dac_valid_q0, + dac_data_q0, + dac_enable_i1, + dac_valid_i1, + dac_data_i1, + dac_enable_q1, + dac_valid_q1, + dac_data_q1, dac_dovf, dac_dunf, @@ -101,39 +91,29 @@ module axi_ad9361_tx ( input dac_clk; output dac_valid; - output dac_lb_enb_i1; - output dac_pn_enb_i1; - output [11:0] dac_data_i1; - output dac_lb_enb_q1; - output dac_pn_enb_q1; - output [11:0] dac_data_q1; - output dac_lb_enb_i2; - output dac_pn_enb_i2; - output [11:0] dac_data_i2; - output dac_lb_enb_q2; - output dac_pn_enb_q2; - output [11:0] dac_data_q2; + output [47:0] dac_data; output dac_r1_mode; + input [47:0] adc_data; // master/slave - input dac_enable_in; - output dac_enable_out; + input dac_sync_in; + output dac_sync_out; // dma interface - input [15:0] dac_data_0; - output dac_enable_0; - output dac_drd_0; - input [15:0] dac_data_1; - output dac_enable_1; - output dac_drd_1; - input [15:0] dac_data_2; - output dac_enable_2; - output dac_drd_2; - input [15:0] dac_data_3; - output dac_enable_3; - output dac_drd_3; + output dac_enable_i0; + output dac_valid_i0; + input [15:0] dac_data_i0; + output dac_enable_q0; + output dac_valid_q0; + input [15:0] dac_data_q0; + output dac_enable_i1; + output dac_valid_i1; + input [15:0] dac_data_i1; + output dac_enable_q1; + output dac_valid_q1; + input [15:0] dac_data_q1; input dac_dovf; input dac_dunf; @@ -150,22 +130,13 @@ module axi_ad9361_tx ( // internal registers - reg dac_enable = 'd0; + reg dac_data_sync = 'd0; reg [ 7:0] dac_rate_cnt = 'd0; - reg dac_dds_enable = 'd0; - reg dac_dds_data_enable = 'd0; - reg dac_dds_data_enable_toggle = 'd0; - reg dac_drd = 'd0; - reg [63:0] dac_dma_data = 'd0; - reg [15:0] dac_dma_data_0 = 'd0; - reg [15:0] dac_dma_data_1 = 'd0; - reg [15:0] dac_dma_data_2 = 'd0; - reg [15:0] dac_dma_data_3 = 'd0; reg dac_valid = 'd0; - reg [11:0] dac_data_i1 = 'd0; - reg [11:0] dac_data_q1 = 'd0; - reg [11:0] dac_data_i2 = 'd0; - reg [11:0] dac_data_q2 = 'd0; + reg dac_valid_i0 = 'd0; + reg dac_valid_q0 = 'd0; + reg dac_valid_i1 = 'd0; + reg dac_valid_q1 = 'd0; reg [31:0] up_rdata = 'd0; reg up_ack = 'd0; @@ -175,107 +146,39 @@ module axi_ad9361_tx ( // internal signals - wire dac_enable_s; - wire dac_datafmt_s; - wire [ 3:0] dac_datasel_s; + wire dac_data_sync_s; + wire dac_dds_format_s; wire [ 7:0] dac_datarate_s; - wire [15:0] dac_dds_data_0_s; - wire [15:0] dac_dds_data_1_s; - wire [15:0] dac_dds_data_2_s; - wire [15:0] dac_dds_data_3_s; - wire [31:0] up_rdata_0_s; - wire up_ack_0_s; - wire [31:0] up_rdata_1_s; - wire up_ack_1_s; - wire [31:0] up_rdata_2_s; - wire up_ack_2_s; - wire [31:0] up_rdata_3_s; - wire up_ack_3_s; - wire [31:0] up_rdata_s; - wire up_ack_s; + wire [47:0] dac_data_int_s; + wire [31:0] up_rdata_s[0:4]; + wire up_ack_s[0:4]; // master/slave - assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in; - assign dac_drd_0 = dac_drd; - assign dac_drd_1 = dac_drd; - assign dac_drd_2 = dac_drd; - assign dac_drd_3 = dac_drd; - - assign dac_enable_0 = dac_enable_s; - assign dac_enable_1 = dac_enable_s; - assign dac_enable_2 = dac_enable_s; - assign dac_enable_3 = dac_enable_s; + assign dac_data_sync_s = (PCORE_ID == 0) ? dac_sync_out : dac_sync_in; always @(posedge dac_clk) begin - dac_enable <= dac_enable_s; + dac_data_sync <= dac_data_sync_s; end - // dds rate counters, dds phases are updated using data enables + // rate counters and data sync signals always @(posedge dac_clk) begin - if ((dac_enable_s == 1'b0) || (dac_rate_cnt == 8'd0)) begin + if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin dac_rate_cnt <= dac_datarate_s; end else begin dac_rate_cnt <= dac_rate_cnt - 1'b1; end - dac_dds_enable <= dac_enable_s; - if (dac_rate_cnt == 8'd0) begin - dac_dds_data_enable <= 1'b1; - end else begin - dac_dds_data_enable <= 1'b0; - end end // dma interface always @(posedge dac_clk) begin - if (dac_dds_data_enable == 1'b1) begin - dac_dds_data_enable_toggle <= ~dac_dds_data_enable_toggle; - end - if (dac_r1_mode == 1'b1) begin - dac_drd <= dac_dds_data_enable & dac_dds_data_enable_toggle & dac_enable; - end else begin - dac_drd <= dac_dds_data_enable & dac_enable; - end - if (dac_drd == 1'b1) begin - dac_dma_data <= {dac_data_3, dac_data_2, dac_data_1, dac_data_0}; - end - if (dac_dds_data_enable == 1'b1) begin - if (dac_r1_mode == 1'b0) begin - dac_dma_data_0 <= dac_dma_data[15: 0]; - dac_dma_data_1 <= dac_dma_data[31:16]; - dac_dma_data_2 <= dac_dma_data[47:32]; - dac_dma_data_3 <= dac_dma_data[63:48]; - end else if (dac_dds_data_enable_toggle == 1'b1) begin - dac_dma_data_0 <= dac_dma_data[47:32]; - dac_dma_data_1 <= dac_dma_data[63:48]; - dac_dma_data_2 <= 16'd0; - dac_dma_data_3 <= 16'd0; - end else begin - dac_dma_data_0 <= dac_dma_data[15: 0]; - dac_dma_data_1 <= dac_dma_data[31:16]; - dac_dma_data_2 <= 16'd0; - dac_dma_data_3 <= 16'd0; - end - end - end - - // dac outputs - - always @(posedge dac_clk) begin - dac_valid <= dac_dds_data_enable; - if (dac_datasel_s[3:1] == 3'd1) begin - dac_data_i1 <= dac_dma_data_0[15:4]; - dac_data_q1 <= dac_dma_data_1[15:4]; - dac_data_i2 <= dac_dma_data_2[15:4]; - dac_data_q2 <= dac_dma_data_3[15:4]; - end else begin - dac_data_i1 <= dac_dds_data_0_s[15:4]; - dac_data_q1 <= dac_dds_data_1_s[15:4]; - dac_data_i2 <= dac_dds_data_2_s[15:4]; - dac_data_q2 <= dac_dds_data_3_s[15:4]; - end + dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; + dac_valid_i0 <= dac_valid; + dac_valid_q0 <= dac_valid; + dac_valid_i1 <= dac_valid & ~dac_r1_mode; + dac_valid_q1 <= dac_valid & ~dac_r1_mode; end // processor read interface @@ -285,114 +188,118 @@ module axi_ad9361_tx ( up_rdata <= 'd0; up_ack <= 'd0; end else begin - up_rdata <= up_rdata_s | - up_rdata_0_s | - up_rdata_1_s | - up_rdata_2_s | - up_rdata_3_s; - up_ack <= up_ack_s | - up_ack_0_s | - up_ack_1_s | - up_ack_2_s | - up_ack_3_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4]; + up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2] | up_ack_s[3] | up_ack_s[4]; end end // dac channel axi_ad9361_tx_channel #( - .CHID(0), + .CHID (0), + .IQSEL (0), .DP_DISABLE (DP_DISABLE)) i_tx_channel_0 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_dds_data (dac_dds_data_0_s), - .dac_dds_enable (dac_dds_enable), - .dac_dds_data_enable (dac_dds_data_enable), - .dac_dds_format (dac_datafmt_s), - .dac_dds_pattenb (dac_datasel_s[0]), - .dac_lb_enb (dac_lb_enb_i1), - .dac_pn_enb (dac_pn_enb_i1), + .dac_valid (dac_valid), + .dma_data (dac_data_i0), + .adc_data (adc_data[11:0]), + .dac_data (dac_data[11:0]), + .dac_data_out (dac_data_int_s[11:0]), + .dac_data_in (dac_data_int_s[23:12]), + .dac_enable (dac_enable_i0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_0_s), - .up_ack (up_ack_0_s)); + .up_rdata (up_rdata_s[0]), + .up_ack (up_ack_s[0])); // dac channel axi_ad9361_tx_channel #( - .CHID(1), + .CHID (1), + .IQSEL (1), .DP_DISABLE (DP_DISABLE)) i_tx_channel_1 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_dds_data (dac_dds_data_1_s), - .dac_dds_enable (dac_dds_enable), - .dac_dds_data_enable (dac_dds_data_enable), - .dac_dds_format (dac_datafmt_s), - .dac_dds_pattenb (dac_datasel_s[0]), - .dac_lb_enb (dac_lb_enb_q1), - .dac_pn_enb (dac_pn_enb_q1), + .dac_valid (dac_valid), + .dma_data (dac_data_q0), + .adc_data (adc_data[23:12]), + .dac_data (dac_data[23:12]), + .dac_data_out (dac_data_int_s[23:12]), + .dac_data_in (dac_data_int_s[11:0]), + .dac_enable (dac_enable_q0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_1_s), - .up_ack (up_ack_1_s)); + .up_rdata (up_rdata_s[1]), + .up_ack (up_ack_s[1])); // dac channel axi_ad9361_tx_channel #( - .CHID(2), + .CHID (2), + .IQSEL (0), .DP_DISABLE (DP_DISABLE)) i_tx_channel_2 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_dds_data (dac_dds_data_2_s), - .dac_dds_enable (dac_dds_enable), - .dac_dds_data_enable (dac_dds_data_enable), - .dac_dds_format (dac_datafmt_s), - .dac_dds_pattenb (dac_datasel_s[0]), - .dac_lb_enb (dac_lb_enb_i2), - .dac_pn_enb (dac_pn_enb_i2), + .dac_valid (dac_valid), + .dma_data (dac_data_i1), + .adc_data (adc_data[35:24]), + .dac_data (dac_data[35:24]), + .dac_data_out (dac_data_int_s[35:24]), + .dac_data_in (dac_data_int_s[47:36]), + .dac_enable (dac_enable_i1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_2_s), - .up_ack (up_ack_2_s)); + .up_rdata (up_rdata_s[2]), + .up_ack (up_ack_s[2])); // dac channel axi_ad9361_tx_channel #( - .CHID(3), + .CHID (3), + .IQSEL (1), .DP_DISABLE (DP_DISABLE)) i_tx_channel_3 ( .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_dds_data (dac_dds_data_3_s), - .dac_dds_enable (dac_dds_enable), - .dac_dds_data_enable (dac_dds_data_enable), - .dac_dds_format (dac_datafmt_s), - .dac_dds_pattenb (dac_datasel_s[0]), - .dac_lb_enb (dac_lb_enb_q2), - .dac_pn_enb (dac_pn_enb_q2), + .dac_valid (dac_valid), + .dma_data (dac_data_q1), + .adc_data (adc_data[47:36]), + .dac_data (dac_data[47:36]), + .dac_data_out (dac_data_int_s[47:36]), + .dac_data_in (dac_data_int_s[35:24]), + .dac_enable (dac_enable_q1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel), .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_3_s), - .up_ack (up_ack_3_s)); + .up_rdata (up_rdata_s[3]), + .up_ack (up_ack_s[3])); // dac common processor interface @@ -400,13 +307,12 @@ module axi_ad9361_tx ( .mmcm_rst (), .dac_clk (dac_clk), .dac_rst (dac_rst), - .dac_enable (dac_enable_out), + .dac_sync (dac_sync_out), .dac_frame (), .dac_par_type (), .dac_par_enb (), .dac_r1_mode (dac_r1_mode), - .dac_datafmt (dac_datafmt_s), - .dac_datasel (dac_datasel_s), + .dac_datafmt (dac_dds_format_s), .dac_datarate (dac_datarate_s), .dac_status (1'b1), .dac_status_ovf (dac_dovf), @@ -429,8 +335,8 @@ module axi_ad9361_tx ( .up_wr (up_wr), .up_addr (up_addr), .up_wdata (up_wdata), - .up_rdata (up_rdata_s), - .up_ack (up_ack_s)); + .up_rdata (up_rdata_s[4]), + .up_ack (up_ack_s[4])); endmodule diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v index adef6f2a9..52bfe0e80 100755 --- a/library/axi_ad9361/axi_ad9361_tx_channel.v +++ b/library/axi_ad9361/axi_ad9361_tx_channel.v @@ -45,16 +45,18 @@ module axi_ad9361_tx_channel ( dac_clk, dac_rst, - dac_dds_data, + dac_valid, + dma_data, + adc_data, + dac_data, + dac_data_out, + dac_data_in, // processor interface - dac_dds_enable, - dac_dds_data_enable, + dac_enable, + dac_data_sync, dac_dds_format, - dac_dds_pattenb, - dac_lb_enb, - dac_pn_enb, // bus interface @@ -69,23 +71,31 @@ module axi_ad9361_tx_channel ( // parameters - parameter CHID = 32'h0; - parameter DP_DISABLE = 0; + parameter CHID = 32'h0; + parameter IQSEL = 0; + parameter DP_DISABLE = 0; + localparam PRBS_SEL = CHID; + localparam PRBS_P09 = 0; + localparam PRBS_P11 = 1; + localparam PRBS_P15 = 2; + localparam PRBS_P20 = 3; // dac interface input dac_clk; input dac_rst; - output [15:0] dac_dds_data; + input dac_valid; + input [15:0] dma_data; + input [11:0] adc_data; + output [11:0] dac_data; + output [11:0] dac_data_out; + input [11:0] dac_data_in; // processor interface - input dac_dds_enable; - input dac_dds_data_enable; + output dac_enable; + input dac_data_sync; input dac_dds_format; - input dac_dds_pattenb; - output dac_lb_enb; - output dac_pn_enb; // bus interface @@ -98,35 +108,267 @@ module axi_ad9361_tx_channel ( output [31:0] up_rdata; output up_ack; + // internal registers + + reg dac_valid_sel = 'd0; + reg dac_enable = 'd0; + reg [11:0] dac_data = 'd0; + reg [11:0] dac_data_out = 'd0; + reg [23:0] dac_pn_seq = 'd0; + reg [11:0] dac_pn_data = 'd0; + reg [15:0] dac_pat_data = 'd0; + reg [15:0] dac_dds_phase_0 = 'd0; + reg [15:0] dac_dds_phase_1 = 'd0; + reg [15:0] dac_dds_data = 'd0; + // internal signals - wire [15:0] dac_dds_patt_1_s; + wire [11:0] dac_data_i_s; + wire [11:0] dac_data_q_s; + wire dac_iqcor_valid_s; + wire [15:0] dac_iqcor_data_s; + wire [15:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; wire [15:0] dac_dds_init_1_s; wire [15:0] dac_dds_incr_1_s; - wire [15:0] dac_dds_scale_1_s; - wire [15:0] dac_dds_patt_2_s; + wire [15:0] dac_dds_scale_2_s; wire [15:0] dac_dds_init_2_s; wire [15:0] dac_dds_incr_2_s; - wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; - // single channel dds + // standard prbs functions - axi_ad9361_tx_dds #(.DP_DISABLE(DP_DISABLE)) i_tx_dds ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_dds_data (dac_dds_data), - .dac_dds_enable (dac_dds_enable), - .dac_dds_data_enable (dac_dds_data_enable), - .dac_dds_format (dac_dds_format), - .dac_dds_pattenb (dac_dds_pattenb), - .dac_dds_patt_1 (dac_dds_patt_1_s), - .dac_dds_init_1 (dac_dds_init_1_s), - .dac_dds_incr_1 (dac_dds_incr_1_s), - .dac_dds_scale_1 (dac_dds_scale_1_s), - .dac_dds_patt_2 (dac_dds_patt_2_s), - .dac_dds_init_2 (dac_dds_init_2_s), - .dac_dds_incr_2 (dac_dds_incr_2_s), - .dac_dds_scale_2 (dac_dds_scale_2_s)); + function [23:0] pn1fn; + input [23:0] din; + reg [23:0] dout; + begin + case (PRBS_SEL) + PRBS_P09: begin + dout[23] = din[ 8] ^ din[ 4]; + dout[22] = din[ 7] ^ din[ 3]; + dout[21] = din[ 6] ^ din[ 2]; + dout[20] = din[ 5] ^ din[ 1]; + dout[19] = din[ 4] ^ din[ 0]; + dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[14] = din[ 8] ^ din[ 0]; + dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + end + PRBS_P11: begin + dout[23] = din[10] ^ din[ 8]; + dout[22] = din[ 9] ^ din[ 7]; + dout[21] = din[ 8] ^ din[ 6]; + dout[20] = din[ 7] ^ din[ 5]; + dout[19] = din[ 6] ^ din[ 4]; + dout[18] = din[ 5] ^ din[ 3]; + dout[17] = din[ 4] ^ din[ 2]; + dout[16] = din[ 3] ^ din[ 1]; + dout[15] = din[ 2] ^ din[ 0]; + dout[14] = din[ 1] ^ din[10] ^ din[ 8]; + dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; + dout[12] = din[10] ^ din[ 6]; + dout[11] = din[ 9] ^ din[ 5]; + dout[10] = din[ 8] ^ din[ 4]; + dout[ 9] = din[ 7] ^ din[ 3]; + dout[ 8] = din[ 6] ^ din[ 2]; + dout[ 7] = din[ 5] ^ din[ 1]; + dout[ 6] = din[ 4] ^ din[ 0]; + dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; + dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; + dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; + dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; + dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + end + PRBS_P15: begin + dout[23] = din[14] ^ din[13]; + dout[22] = din[13] ^ din[12]; + dout[21] = din[12] ^ din[11]; + dout[20] = din[11] ^ din[10]; + dout[19] = din[10] ^ din[ 9]; + dout[18] = din[ 9] ^ din[ 8]; + dout[17] = din[ 8] ^ din[ 7]; + dout[16] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[14] ^ din[13]; + dout[ 8] = din[14] ^ din[12]; + dout[ 7] = din[13] ^ din[11]; + dout[ 6] = din[12] ^ din[10]; + dout[ 5] = din[11] ^ din[ 9]; + dout[ 4] = din[10] ^ din[ 8]; + dout[ 3] = din[ 9] ^ din[ 7]; + dout[ 2] = din[ 8] ^ din[ 6]; + dout[ 1] = din[ 7] ^ din[ 5]; + dout[ 0] = din[ 6] ^ din[ 4]; + end + PRBS_P20: begin + dout[23] = din[19] ^ din[ 2]; + dout[22] = din[18] ^ din[ 1]; + dout[21] = din[17] ^ din[ 0]; + dout[20] = din[16] ^ din[19] ^ din[ 2]; + dout[19] = din[15] ^ din[18] ^ din[ 1]; + dout[18] = din[14] ^ din[17] ^ din[ 0]; + dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + end + endcase + pn1fn = dout; + end + endfunction + + // global toggle + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_valid_sel <= 1'b0; + end else if (dac_valid == 1'b1) begin + dac_valid_sel <= ~dac_valid_sel; + end + end + + // dac iq correction + + assign dac_data_i_s = (IQSEL == 1) ? dac_data_in : dac_data_out; + assign dac_data_q_s = (IQSEL == 1) ? dac_data_out : dac_data_in; + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + if (dac_iqcor_valid_s == 1'b1) begin + dac_data <= dac_iqcor_data_s[15:4]; + end + end + + generate + if (DP_DISABLE == 1) begin + assign dac_iqcor_valid_s = dac_valid; + assign dac_iqcor_data_s = {dac_data_out, 4'd0}; + end else begin + ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor ( + .clk (dac_clk), + .valid (dac_valid), + .data_i ({dac_data_i_s, 4'd0}), + .data_q ({dac_data_q_s, 4'd0}), + .valid_out (dac_iqcor_valid_s), + .data_out (dac_iqcor_data_s), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + end + endgenerate + + // dac mux + + always @(posedge dac_clk) begin + case (dac_data_sel_s) + 4'h9: dac_data_out <= dac_pn_data; + 4'h8: dac_data_out <= adc_data; + 4'h3: dac_data_out <= 12'd0; + 4'h2: dac_data_out <= dma_data[15:4]; + 4'h1: dac_data_out <= dac_pat_data[15:4]; + default: dac_data_out <= dac_dds_data[15:4]; + endcase + end + + // prbs sequences + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_pn_seq <= 24'hffffff; + dac_pn_data <= 12'd0; + end else if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b1) begin + dac_pn_seq <= pn1fn(dac_pn_seq); + dac_pn_data <= dac_pn_seq[11: 0]; + end else begin + dac_pn_seq <= dac_pn_seq; + dac_pn_data <= dac_pn_seq[23:12]; + end + end + end + + // pattern + + always @(posedge dac_clk) begin + if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b0) begin + dac_pat_data <= dac_pat_data_1_s; + end else begin + dac_pat_data <= dac_pat_data_2_s; + end + end + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_dds_phase_0 <= dac_dds_init_1_s; + dac_dds_phase_1 <= dac_dds_init_2_s; + dac_dds_data <= 16'd0; + end else if (dac_valid == 1'b1) begin + dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_1_s; + dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_2_s; + dac_dds_data <= dac_dds_data_s; + end + end + + // dds + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_s = 16'd0; + end else begin + ad_dds i_dds ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s)); + end + endgenerate // single channel processor @@ -139,11 +381,12 @@ module axi_ad9361_tx_channel ( .dac_dds_scale_2 (dac_dds_scale_2_s), .dac_dds_init_2 (dac_dds_init_2_s), .dac_dds_incr_2 (dac_dds_incr_2_s), - .dac_dds_patt_1 (dac_dds_patt_1_s), - .dac_dds_patt_2 (dac_dds_patt_2_s), - .dac_dds_sel (), - .dac_lb_enb (dac_lb_enb), - .dac_pn_enb (dac_pn_enb), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), .up_usr_datatype_be (), .up_usr_datatype_signed (), .up_usr_datatype_shift (), diff --git a/library/axi_ad9361/axi_ad9361_tx_dds.v b/library/axi_ad9361/axi_ad9361_tx_dds.v index ac34c0f04..b40474ab8 100755 --- a/library/axi_ad9361/axi_ad9361_tx_dds.v +++ b/library/axi_ad9361/axi_ad9361_tx_dds.v @@ -127,22 +127,6 @@ module axi_ad9361_tx_dds ( // dds - generate - if (DP_DISABLE == 1) begin - assign dac_dds_data_s = 16'd0; - end else begin - ad_dds i_dds_0 ( - .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_enable (dac_dds_enable), - .dds_phase_0 (dac_dds_phase_0), - .dds_scale_0 (dac_dds_scale_1), - .dds_phase_1 (dac_dds_phase_1), - .dds_scale_1 (dac_dds_scale_2), - .dds_data (dac_dds_data_s)); - end - endgenerate - endmodule // ***************************************************************************