From e683b5868e68d9ea04c33a4ddb6fdd0ce671f454 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 11 Nov 2014 15:25:35 -0500 Subject: [PATCH] axi_fifo2s: include bus width/clock transfer --- library/axi_fifo2s/axi_fifo2s_constr.xdc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/library/axi_fifo2s/axi_fifo2s_constr.xdc b/library/axi_fifo2s/axi_fifo2s_constr.xdc index 2e760eb84..e7ba7f13f 100644 --- a/library/axi_fifo2s/axi_fifo2s_constr.xdc +++ b/library/axi_fifo2s/axi_fifo2s_constr.xdc @@ -1,6 +1,13 @@ -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_clk]] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports axi_clk]] +set_false_path -from [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] +set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] + +set_false_path -from [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] +set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]