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axi_fifo2s: include bus width/clock transfer

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Rejeesh Kutty 2014-11-11 15:25:35 -05:00
parent 81b4cd532d
commit e683b5868e
1 changed files with 9 additions and 2 deletions
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11
library/axi_fifo2s/axi_fifo2s_constr.xdc
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@ -1,6 +1,13 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports axi_clk]]
set_false_path -from [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]