cn0363/zed: Fix DMAC parameter names
parent
4aa4ffc25f
commit
e6af671bea
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@ -28,17 +28,17 @@ set_property LEFT 34 [get_bd_ports GPIO_T]
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set axi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma]
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set_property -dict [list \
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CONFIG.C_FIFO_SIZE 2 \
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CONFIG.C_DMA_TYPE_SRC 2 \
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CONFIG.C_DMA_TYPE_DEST 0 \
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CONFIG.C_CYCLIC 0 \
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CONFIG.C_SYNC_TRANSFER_START 1 \
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CONFIG.C_AXI_SLICE_SRC 0 \
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CONFIG.C_AXI_SLICE_DEST 0 \
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CONFIG.C_DMA_2D_TRANSFER 0 \
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CONFIG.C_DMA_DATA_WIDTH_SRC 32 \
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CONFIG.C_DMA_DATA_WIDTH_DEST 64 \
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CONFIG.C_DMA_AXI_PROTOCOL_DEST 1 \
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CONFIG.FIFO_SIZE 2 \
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CONFIG.DMA_TYPE_SRC 2 \
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CONFIG.DMA_TYPE_DEST 0 \
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CONFIG.CYCLIC 0 \
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CONFIG.SYNC_TRANSFER_START 1 \
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CONFIG.AXI_SLICE_SRC 0 \
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CONFIG.AXI_SLICE_DEST 0 \
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CONFIG.DMA_2D_TRANSFER 0 \
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CONFIG.DMA_DATA_WIDTH_SRC 32 \
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CONFIG.DMA_DATA_WIDTH_DEST 64 \
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CONFIG.DMA_AXI_PROTOCOL_DEST 1 \
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] $axi_dma
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# Create SPI engine controller with offload
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@ -130,7 +130,7 @@ current_bd_instance /processing
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create_bd_pin -dir O overflow
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create_bd_pin -dir I -from 13 -to 0 channel_enable
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR
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create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync
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create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer
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@ -256,7 +256,7 @@ current_bd_instance /processing
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ad_connect overflow_or/Res overflow
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ad_connect phase_data_sync/sample_has_stat GND
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current_bd_instance /
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ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
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@ -290,8 +290,8 @@ ad_cpu_interconnect 0x43c00000 /axi_adc
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ad_cpu_interconnect 0x44a00000 /spi/axi
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ad_cpu_interconnect 0x44a30000 /axi_dma
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ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
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ad_cpu_interrupt "ps-13" "mb-13" /axi_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_dma/m_dest_axi
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