motor_control: Updated project to Vivado 14.2. Temporary removed XADC
- fixed constraints - updated interrupt system - used ad_iobuf - The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selectedmain
Adrian Costina
parent
a70d27c094
commit
e6e9c0058d
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@ -41,22 +41,26 @@
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set gpo_o [ create_bd_port -dir O -from 7 -to 0 gpo_o ]
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# interrupts
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set motcon1_c_m_1_irq [create_bd_port -dir O motcon1_c_m_1_irq]
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set motcon1_c_m_2_irq [create_bd_port -dir O motcon1_c_m_2_irq]
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set motcon1_s_d_irq [create_bd_port -dir O motcon1_s_d_irq]
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set motcon1_ctrl_irq [create_bd_port -dir O motcon1_ctrl_irq]
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# xadc interface
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set vp_in [ create_bd_port -dir I vp_in ]
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set vn_in [ create_bd_port -dir I vn_in ]
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set vauxp0 [ create_bd_port -dir I vauxp0 ]
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set vauxn0 [ create_bd_port -dir I vauxn0 ]
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set vauxp8 [ create_bd_port -dir I vauxp8 ]
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set vauxn8 [ create_bd_port -dir I vauxn8 ]
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set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ]
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#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
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#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
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#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
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#set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ]
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# additions to default configuration
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set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
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set_property -dict [list CONFIG.NUM_MI {17}] $axi_cpu_interconnect
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set_property -dict [ list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
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set_property -dict [ list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7
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# current monitor 1 peripherals
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@ -109,7 +113,8 @@
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_controller_dma
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# controller ILA
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set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_controller ]
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set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_controller ]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_controller
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set_property -dict [ list CONFIG.C_ADV_TRIGGER {true} ] $ila_controller
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set_property -dict [ list CONFIG.C_DATA_DEPTH {8192} ] $ila_controller
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set_property -dict [ list CONFIG.C_EN_STRG_QUAL {1} ] $ila_controller
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@ -144,16 +149,14 @@
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# xadc
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set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ]
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set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_wiz_1
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set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {false} ] $xadc_wiz_1
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# set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ]
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# set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1
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# set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1
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# set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1
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# set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1
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# set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1
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# set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1
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# set_property -dict [list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0}] $xadc_wiz_1
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# additional interconnect
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@ -164,7 +167,7 @@
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# position
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connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i]
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connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i]
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connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i]
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# current monitor 1
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@ -193,7 +196,7 @@
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# interrupt
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connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_pins sys_concat_intc/In2]
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connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_ports motcon1_c_m_1_irq]
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# current monitor 2
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@ -214,7 +217,7 @@
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#interrupt
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connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_pins sys_concat_intc/In6]
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connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_ports motcon1_c_m_2_irq]
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# speed detector
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@ -229,7 +232,7 @@
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# interrupt
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connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_pins sys_concat_intc/In3]
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connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_ports motcon1_s_d_irq]
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# controller
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@ -314,20 +317,17 @@
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# interrupt
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connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_pins sys_concat_intc/In5]
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connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_ports motcon1_ctrl_irq]
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# xadc
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connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
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# connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
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# connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
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connect_bd_net -net vp_in_1 [get_bd_ports vp_in] [get_bd_pins xadc_wiz_1/vp_in]
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connect_bd_net -net vn_in_1 [get_bd_ports vn_in] [get_bd_pins xadc_wiz_1/vn_in]
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connect_bd_net -net vauxp0_1 [get_bd_ports vauxp0] [get_bd_pins xadc_wiz_1/vauxp0]
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connect_bd_net -net vauxn0_1 [get_bd_ports vauxn0] [get_bd_pins xadc_wiz_1/vauxn0]
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connect_bd_net -net vauxp8_1 [get_bd_ports vauxp8] [get_bd_pins xadc_wiz_1/vauxp8]
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connect_bd_net -net vauxn8_1 [get_bd_ports vauxn8] [get_bd_pins xadc_wiz_1/vauxn8]
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connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
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# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn]
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# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0]
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# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8]
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# connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
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# interconnect (cpu)
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@ -335,7 +335,7 @@
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
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# connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
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@ -441,7 +441,7 @@
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create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
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create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c
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create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
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create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
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# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
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create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c
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create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
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@ -1,20 +1,5 @@
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# Motor Control
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#Test
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#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[27]] ; ## XADC-GIO0
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#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[28]] ; ## XADC-GIO1
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#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[29]] ; ## XADC-GIO2
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#reset_property -dict {PACKAGE_PIN IOSTANDARD } [get_ports gpio_bd[30]] ; ## XADC-GIO3
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set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
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#End Test
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set_property PACKAGE_PIN J16 [get_ports {position_i[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {position_i[0]}]
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set_property PACKAGE_PIN J17 [get_ports {position_i[1]}]
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@ -89,31 +74,13 @@ set_property PACKAGE_PIN E21 [get_ports adc_it_clk_d_o]
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set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o]
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set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}]
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set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}]
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set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}]
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set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}]
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#set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}]
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#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}]
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#set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}]
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#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}]
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#set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}]
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#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}]
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#set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}]
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#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}]
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set_property PACKAGE_PIN E16 [get_ports vauxn0]
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set_property IOSTANDARD LVCMOS25 [get_ports vauxn0]
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set_property PACKAGE_PIN D17 [get_ports vauxn8]
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set_property IOSTANDARD LVCMOS25 [get_ports vauxn8]
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set_property PACKAGE_PIN F16 [get_ports vauxp0]
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set_property IOSTANDARD LVCMOS25 [get_ports vauxp0]
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set_property PACKAGE_PIN D16 [get_ports vauxp8]
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set_property IOSTANDARD LVCMOS25 [get_ports vauxp8]
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set_property PACKAGE_PIN M12 [get_ports vn_in]
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set_property IOSTANDARD LVCMOS25 [get_ports vn_in]
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set_property PACKAGE_PIN L11 [get_ports vp_in]
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set_property IOSTANDARD LVCMOS25 [get_ports vp_in]
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create_clock -name ctrl_clk -period 20.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
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create_clock -name ps7_clk_2 -period 20.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
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set_clock_groups -asynchronous -group {ctrl_clk}
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set_clock_groups -asynchronous -group {ps7_clk_2}
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set_false_path -through [get_pins {i_system_wrapper/system_i/foc_controller/inst*/*/*/*}]
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@ -6,6 +6,7 @@ adi_project_create motcon1_fmc_zed
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adi_project_files motcon1_fmc_zed [list \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
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adi_project_run motcon1_fmc_zed
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@ -97,13 +97,13 @@ module system_top (
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pwm_ch_o,
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pwm_cl_o,
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vauxn0,
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vauxn8,
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vauxp0,
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vauxp8,
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vn_in,
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vp_in,
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muxaddr_out,
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//vauxn0,
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//vauxn8,
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//vauxp0,
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//vauxp8,
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//vn_in,
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//vp_in,
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//muxaddr_out,
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i2s_mclk,
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i2s_bclk,
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@ -176,13 +176,13 @@ module system_top (
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output pwm_ch_o;
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output pwm_cl_o;
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input vauxn0;
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input vauxn8;
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input vauxp0;
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input vauxp8;
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input vn_in;
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input vp_in;
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output [3:0]muxaddr_out;
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//input vauxn0;
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//input vauxn8;
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//input vauxp0;
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//input vauxp8;
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//input vn_in;
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//input vp_in;
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//output [3:0] muxaddr_out;
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output spdif;
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@ -211,24 +211,33 @@ module system_top (
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [15:0] ps_intrs;
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// instantiations
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genvar n;
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generate
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for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd
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IOBUF i_iobuf_gpio_bd (
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.I (gpio_o[n]),
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.O (gpio_i[n]),
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.T (gpio_t[n]),
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.IO (gpio_bd[n]));
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end
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endgenerate
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ad_iobuf #(
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.DATA_WIDTH(32))
|
||||
i_gpio_bd (
|
||||
.dt(gpio_t),
|
||||
.di(gpio_o),
|
||||
.do(gpio_i),
|
||||
.dio(gpio_bd));
|
||||
|
||||
IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0]));
|
||||
IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1]));
|
||||
IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0]));
|
||||
IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1]));
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2))
|
||||
i_iic_mux_scl (
|
||||
.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.di(iic_mux_scl_o_s),
|
||||
.do(iic_mux_scl_i_s),
|
||||
.dio(iic_mux_scl));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2))
|
||||
i_iic_mux_sda (
|
||||
.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.di(iic_mux_sda_o_s),
|
||||
.do(iic_mux_sda_i_s),
|
||||
.dio(iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
|
|
@ -284,13 +293,13 @@ module system_top (
|
|||
.pwm_bl_o(pwm_bl_o),
|
||||
.pwm_ch_o(pwm_ch_o),
|
||||
.pwm_cl_o(pwm_cl_o),
|
||||
.vauxn0(vauxn0),
|
||||
.vauxn8(vauxn8),
|
||||
.vauxp0(vauxp0),
|
||||
.vauxp8(vauxp8),
|
||||
.vn_in(vn_in),
|
||||
.vp_in(vp_in),
|
||||
.muxaddr_out(muxaddr_out),
|
||||
//.Vaux0_v_n(vauxn0),
|
||||
//.Vaux0_v_p(vauxp0),
|
||||
//.vauxn8(vauxn8),
|
||||
//.vauxp8(vauxp8),
|
||||
//.Vp_Vn_v_n(vn_in),
|
||||
//.Vp_Vn_v_p(vp_in),
|
||||
//.muxaddr_out(muxaddr_out),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
|
|
@ -304,6 +313,25 @@ module system_top (
|
|||
.iic_mux_sda_I (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_O (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_T (iic_mux_sda_t_s),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
.ps_intr_5 (ps_intrs[5]),
|
||||
.ps_intr_6 (ps_intrs[6]),
|
||||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.iic_fmc_intr(ps_intrs[11]),
|
||||
.motcon1_c_m_1_irq(ps_intrs[13]),
|
||||
.motcon1_c_m_2_irq(ps_intrs[9]),
|
||||
.motcon1_s_d_irq(ps_intrs[12]),
|
||||
.motcon1_ctrl_irq(ps_intrs[10]),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue