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adi_jesd204: add_instance command must have a version attribute

main
Istvan Csomortani 2019-05-13 13:33:55 +01:00 committed by Adrian Costina
parent 8fd1ad64d6
commit e856a99e49
2 changed files with 40 additions and 22 deletions
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41
library/intel/adi_jesd204/adi_jesd204_hw.tcl
View File

@ -46,6 +46,8 @@ package require qsys
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl source ../../scripts/adi_ip_intel.tcl
set version 19.1
# #
# Wrapper module that instantiates and connects all the components required to # Wrapper module that instantiates and connects all the components required to
# for a JESD204 link. # for a JESD204 link.
@ -132,7 +134,10 @@ ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
} }
proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} { proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
add_instance phy_reset_control altera_xcvr_reset_control
global version
add_instance phy_reset_control altera_xcvr_reset_control $version
set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
@ -160,7 +165,10 @@ proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
} }
proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} { proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} {
add_instance lane_pll altera_xcvr_atx_pll_a10
global version
add_instance lane_pll altera_xcvr_atx_pll_a10 $version
set_instance_property lane_pll SUPPRESS_ALL_INFO_MESSAGES true set_instance_property lane_pll SUPPRESS_ALL_INFO_MESSAGES true
set_instance_parameter_value lane_pll {enable_pll_reconfig} {1} set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1} set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1}
@ -259,6 +267,9 @@ proc jesd204_validate {{quiet false}} {
} }
proc jesd204_compose {} { proc jesd204_compose {} {
global version
set id [get_parameter_value "ID"] set id [get_parameter_value "ID"]
set lane_rate [get_parameter_value "LANE_RATE"] set lane_rate [get_parameter_value "LANE_RATE"]
set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
@ -286,7 +297,7 @@ proc jesd204_compose {} {
set register_inputs 0; set register_inputs 0;
} }
add_instance sys_clock clock_source add_instance sys_clock clock_source 19.2
set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000] set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000]
set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert} set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert}
add_interface sys_clk clock sink add_interface sys_clk clock sink
@ -294,13 +305,13 @@ proc jesd204_compose {} {
add_interface sys_resetn reset sink add_interface sys_resetn reset sink
set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset
add_instance ref_clock altera_clock_bridge add_instance ref_clock altera_clock_bridge $version
set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000] set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000]
add_interface ref_clk clock sink add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF ref_clock.in_clk set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
# FIXME: In phase alignment mode manual re-calibration fails # FIXME: In phase alignment mode manual re-calibration fails
add_instance link_pll altera_xcvr_fpll_a10 add_instance link_pll altera_xcvr_fpll_a10 $version
set_instance_property link_pll SUPPRESS_ALL_WARNINGS true set_instance_property link_pll SUPPRESS_ALL_WARNINGS true
set_instance_property link_pll SUPPRESS_ALL_INFO_MESSAGES true set_instance_property link_pll SUPPRESS_ALL_INFO_MESSAGES true
set_instance_parameter_value link_pll {gui_fpll_mode} {0} set_instance_parameter_value link_pll {gui_fpll_mode} {0}
@ -319,14 +330,13 @@ proc jesd204_compose {} {
## link clock configuration (also known as device clock, which will be used ## link clock configuration (also known as device clock, which will be used
## by the upper layers for the data path, it can come from the PCS or external) ## by the upper layers for the data path, it can come from the PCS or external)
add_instance link_clock altera_clock_bridge add_instance link_clock altera_clock_bridge $version
set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000] set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2 set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2
add_connection link_pll.outclk0 link_clock.in_clk add_connection link_pll.outclk0 link_clock.in_clk
add_interface link_clk clock source add_interface link_clk clock source
add_instance link_reset altera_reset_bridge $version
add_instance link_reset altera_reset_bridge
set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2 set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
add_connection sys_clock.clk link_reset.clk add_connection sys_clock.clk link_reset.clk
add_interface link_reset reset source add_interface link_reset reset source
@ -335,7 +345,7 @@ proc jesd204_compose {} {
add_connection sys_clock.clk_reset link_pll.reconfig_reset0 add_connection sys_clock.clk_reset link_pll.reconfig_reset0
add_connection sys_clock.clk link_pll.reconfig_clk0 add_connection sys_clock.clk link_pll.reconfig_clk0
add_instance axi_xcvr axi_adxcvr add_instance axi_xcvr axi_adxcvr 1.0
set_instance_parameter_value axi_xcvr {ID} $id set_instance_parameter_value axi_xcvr {ID} $id
set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n
set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes
@ -351,7 +361,7 @@ proc jesd204_compose {} {
add_interface link_pll_reconfig avalon slave add_interface link_pll_reconfig avalon slave
set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0 set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0
add_instance link_pll_reset_control altera_xcvr_reset_control add_instance link_pll_reset_control altera_xcvr_reset_control $version
set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1} set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1}
set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000} set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000}
@ -365,7 +375,7 @@ proc jesd204_compose {} {
create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency
add_instance phy jesd204_phy add_instance phy jesd204_phy 1.0
set_instance_parameter_value phy ID $id set_instance_parameter_value phy ID $id
set_instance_parameter_value phy SOFT_PCS $soft_pcs set_instance_parameter_value phy SOFT_PCS $soft_pcs
set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n
@ -385,7 +395,7 @@ proc jesd204_compose {} {
## connect the required device clock ## connect the required device clock
if {$ext_device_clk_en} { if {$ext_device_clk_en} {
add_instance ext_device_clock altera_clock_bridge add_instance ext_device_clock altera_clock_bridge $version
set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000] set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2 set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2
add_interface device_clk clock sink add_interface device_clk clock sink
@ -423,13 +433,16 @@ proc jesd204_compose {} {
add_connection ref_clock.out_clk phy.ref_clk add_connection ref_clock.out_clk phy.ref_clk
} }
add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} 1.0
set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock
add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset
add_instance jesd204_${tx_rx} jesd204_${tx_rx} add_connection link_clock.out_clk_1 axi_jesd204_${tx_rx}.core_clock
add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
add_instance jesd204_${tx_rx} jesd204_${tx_rx} 1.0
set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
if {$ext_device_clk_en} { if {$ext_device_clk_en} {

21
library/intel/jesd204_phy/jesd204_phy_hw.tcl
View File

@ -47,6 +47,8 @@ package require qsys
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
set version 19.2
# #
# Instantiates the Arria 10 native PHY and configures it for JESD204 operation. # Instantiates the Arria 10 native PHY and configures it for JESD204 operation.
# The datapath width is configured for 4 octets per beat. # The datapath width is configured for 4 octets per beat.
@ -57,7 +59,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_phy "ADI JESD204 PHY" ad_ip_create jesd204_phy "ADI JESD204 PHY"
set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback
set_module_property INTERNAL true set_module_property INTERNAL false
# parameters # parameters
@ -73,6 +75,9 @@ ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN false false
ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false
proc jesd204_phy_composition_callback {} { proc jesd204_phy_composition_callback {} {
global version
set soft_pcs [get_parameter_value "SOFT_PCS"] set soft_pcs [get_parameter_value "SOFT_PCS"]
set tx [get_parameter_value "TX_OR_RX_N"] set tx [get_parameter_value "TX_OR_RX_N"]
set lane_rate [get_parameter_value "LANE_RATE"] set lane_rate [get_parameter_value "LANE_RATE"]
@ -86,15 +91,14 @@ proc jesd204_phy_composition_callback {} {
set link_clk_frequency [expr $lane_rate / 40] set link_clk_frequency [expr $lane_rate / 40]
add_instance link_clock clock_source add_instance link_clock clock_source $version
set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000] set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000]
add_interface link_clk clock sink add_interface link_clk clock sink
set_interface_property link_clk EXPORT_OF link_clock.clk_in set_interface_property link_clk EXPORT_OF link_clock.clk_in
add_interface link_reset reset sink add_interface link_reset reset sink
set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset
add_instance native_phy altera_xcvr_native_a10 19.1
add_instance native_phy altera_xcvr_native_a10
set_instance_property native_phy SUPPRESS_ALL_WARNINGS true set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
if {$soft_pcs} { if {$soft_pcs} {
@ -154,7 +158,7 @@ proc jesd204_phy_composition_callback {} {
set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1 set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1
set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0 set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0
add_instance phy_glue jesd204_phy_glue add_instance phy_glue jesd204_phy_glue 1.0
set_instance_parameter_value phy_glue TX_OR_RX_N $tx set_instance_parameter_value phy_glue TX_OR_RX_N $tx
set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs
set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes
@ -168,7 +172,7 @@ proc jesd204_phy_composition_callback {} {
set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset
if {$ext_device_clk_en} { if {$ext_device_clk_en} {
add_instance ext_device_clock altera_clock_bridge add_instance ext_device_clock altera_clock_bridge 19.1
set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $link_clk_frequency*1000000] set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $link_clk_frequency*1000000]
set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 1 set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 1
add_interface device_clk clock sink add_interface device_clk clock sink
@ -215,6 +219,7 @@ proc jesd204_phy_composition_callback {} {
add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv
} }
} else { } else {
add_interface ref_clk clock sink add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0 set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0
@ -250,7 +255,7 @@ proc jesd204_phy_composition_callback {} {
if {$tx} { if {$tx} {
if {$soft_pcs} { if {$soft_pcs} {
add_instance soft_pcs_${i} jesd204_soft_pcs_tx add_instance soft_pcs_${i} jesd204_soft_pcs_tx 1.0
set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \ set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \
[expr ($lane_invert >> $i) & 1] [expr ($lane_invert >> $i) & 1]
if {$ext_device_clk_en} { if {$ext_device_clk_en} {
@ -267,7 +272,7 @@ proc jesd204_phy_composition_callback {} {
} }
} else { } else {
if {$soft_pcs} { if {$soft_pcs} {
add_instance soft_pcs_${i} jesd204_soft_pcs_rx add_instance soft_pcs_${i} jesd204_soft_pcs_rx 1.0
set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs
set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \ set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \
[expr ($lane_invert >> $i) & 1] [expr ($lane_invert >> $i) & 1]