adi_jesd204: add_instance command must have a version attribute
Istvan Csomortani
Adrian Costina
parent
8fd1ad64d6
commit
e856a99e49
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@ -46,6 +46,8 @@ package require qsys
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_intel.tcl
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set version 19.1
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#
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# Wrapper module that instantiates and connects all the components required to
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# for a JESD204 link.
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@ -132,7 +134,10 @@ ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
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}
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proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
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add_instance phy_reset_control altera_xcvr_reset_control
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global version
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add_instance phy_reset_control altera_xcvr_reset_control $version
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set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
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set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
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set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
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@ -160,7 +165,10 @@ proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
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}
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proc create_lane_pll {id pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} {
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add_instance lane_pll altera_xcvr_atx_pll_a10
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global version
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add_instance lane_pll altera_xcvr_atx_pll_a10 $version
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set_instance_property lane_pll SUPPRESS_ALL_INFO_MESSAGES true
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set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
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set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1}
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@ -259,6 +267,9 @@ proc jesd204_validate {{quiet false}} {
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}
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proc jesd204_compose {} {
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global version
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set id [get_parameter_value "ID"]
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set lane_rate [get_parameter_value "LANE_RATE"]
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set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
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@ -286,7 +297,7 @@ proc jesd204_compose {} {
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set register_inputs 0;
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}
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add_instance sys_clock clock_source
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add_instance sys_clock clock_source 19.2
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set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000]
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set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert}
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add_interface sys_clk clock sink
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@ -294,13 +305,13 @@ proc jesd204_compose {} {
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add_interface sys_resetn reset sink
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set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset
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add_instance ref_clock altera_clock_bridge
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add_instance ref_clock altera_clock_bridge $version
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set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000]
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
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# FIXME: In phase alignment mode manual re-calibration fails
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add_instance link_pll altera_xcvr_fpll_a10
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add_instance link_pll altera_xcvr_fpll_a10 $version
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set_instance_property link_pll SUPPRESS_ALL_WARNINGS true
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set_instance_property link_pll SUPPRESS_ALL_INFO_MESSAGES true
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set_instance_parameter_value link_pll {gui_fpll_mode} {0}
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@ -319,14 +330,13 @@ proc jesd204_compose {} {
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## link clock configuration (also known as device clock, which will be used
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## by the upper layers for the data path, it can come from the PCS or external)
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add_instance link_clock altera_clock_bridge
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add_instance link_clock altera_clock_bridge $version
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set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
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set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2
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add_connection link_pll.outclk0 link_clock.in_clk
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add_interface link_clk clock source
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add_instance link_reset altera_reset_bridge
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add_instance link_reset altera_reset_bridge $version
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set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
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add_connection sys_clock.clk link_reset.clk
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add_interface link_reset reset source
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@ -335,7 +345,7 @@ proc jesd204_compose {} {
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add_connection sys_clock.clk_reset link_pll.reconfig_reset0
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add_connection sys_clock.clk link_pll.reconfig_clk0
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add_instance axi_xcvr axi_adxcvr
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add_instance axi_xcvr axi_adxcvr 1.0
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set_instance_parameter_value axi_xcvr {ID} $id
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set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n
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set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes
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@ -351,7 +361,7 @@ proc jesd204_compose {} {
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add_interface link_pll_reconfig avalon slave
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set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0
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add_instance link_pll_reset_control altera_xcvr_reset_control
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add_instance link_pll_reset_control altera_xcvr_reset_control $version
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set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
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set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1}
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set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000}
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@ -365,7 +375,7 @@ proc jesd204_compose {} {
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create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency
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add_instance phy jesd204_phy
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add_instance phy jesd204_phy 1.0
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set_instance_parameter_value phy ID $id
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set_instance_parameter_value phy SOFT_PCS $soft_pcs
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set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n
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@ -385,7 +395,7 @@ proc jesd204_compose {} {
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## connect the required device clock
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if {$ext_device_clk_en} {
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add_instance ext_device_clock altera_clock_bridge
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add_instance ext_device_clock altera_clock_bridge $version
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set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
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set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2
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add_interface device_clk clock sink
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@ -423,13 +433,16 @@ proc jesd204_compose {} {
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add_connection ref_clock.out_clk phy.ref_clk
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}
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add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx}
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add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} 1.0
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set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
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add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock
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add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset
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add_instance jesd204_${tx_rx} jesd204_${tx_rx}
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add_connection link_clock.out_clk_1 axi_jesd204_${tx_rx}.core_clock
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add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
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add_instance jesd204_${tx_rx} jesd204_${tx_rx} 1.0
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set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
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if {$ext_device_clk_en} {
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@ -47,6 +47,8 @@ package require qsys
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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set version 19.2
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#
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# Instantiates the Arria 10 native PHY and configures it for JESD204 operation.
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# The datapath width is configured for 4 octets per beat.
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@ -57,7 +59,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create jesd204_phy "ADI JESD204 PHY"
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set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback
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set_module_property INTERNAL true
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set_module_property INTERNAL false
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# parameters
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@ -73,6 +75,9 @@ ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN false false
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ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false
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proc jesd204_phy_composition_callback {} {
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global version
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set soft_pcs [get_parameter_value "SOFT_PCS"]
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set tx [get_parameter_value "TX_OR_RX_N"]
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set lane_rate [get_parameter_value "LANE_RATE"]
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@ -86,15 +91,14 @@ proc jesd204_phy_composition_callback {} {
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set link_clk_frequency [expr $lane_rate / 40]
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add_instance link_clock clock_source
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add_instance link_clock clock_source $version
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set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000]
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add_interface link_clk clock sink
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set_interface_property link_clk EXPORT_OF link_clock.clk_in
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add_interface link_reset reset sink
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set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset
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add_instance native_phy altera_xcvr_native_a10
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add_instance native_phy altera_xcvr_native_a10 19.1
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set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
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set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
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if {$soft_pcs} {
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@ -154,7 +158,7 @@ proc jesd204_phy_composition_callback {} {
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set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1
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set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0
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add_instance phy_glue jesd204_phy_glue
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add_instance phy_glue jesd204_phy_glue 1.0
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set_instance_parameter_value phy_glue TX_OR_RX_N $tx
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set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs
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set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes
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@ -168,7 +172,7 @@ proc jesd204_phy_composition_callback {} {
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set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset
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if {$ext_device_clk_en} {
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add_instance ext_device_clock altera_clock_bridge
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add_instance ext_device_clock altera_clock_bridge 19.1
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set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $link_clk_frequency*1000000]
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set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 1
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add_interface device_clk clock sink
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@ -215,6 +219,7 @@ proc jesd204_phy_composition_callback {} {
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add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv
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}
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} else {
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0
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@ -250,7 +255,7 @@ proc jesd204_phy_composition_callback {} {
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if {$tx} {
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if {$soft_pcs} {
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add_instance soft_pcs_${i} jesd204_soft_pcs_tx
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add_instance soft_pcs_${i} jesd204_soft_pcs_tx 1.0
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set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \
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[expr ($lane_invert >> $i) & 1]
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if {$ext_device_clk_en} {
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@ -267,7 +272,7 @@ proc jesd204_phy_composition_callback {} {
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}
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} else {
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if {$soft_pcs} {
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add_instance soft_pcs_${i} jesd204_soft_pcs_rx
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add_instance soft_pcs_${i} jesd204_soft_pcs_rx 1.0
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set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs
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set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \
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[expr ($lane_invert >> $i) & 1]
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