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ad6676evb: Parameterize JESD204 configuration values 

Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
main
Dan Hotoleanu 2022-01-20 18:39:51 +00:00 committed by hotoleanudan
parent 318523579f
commit e8ff32d6df
5 changed files with 53 additions and 21 deletions
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32
projects/ad6676evb/common/ad6676evb_bd.tcl
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@ -1,35 +1,42 @@
#
# Parameter description:
# RX_JESD_L : Number of lanes per link
#
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# JESD204B interface configuration parameters
set RX_NUM_OF_LANES 2
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)
set RX_NUM_OF_CONVERTERS 2
set RX_SAMPLES_PER_FRAME 1
set RX_SAMPLE_WIDTH 16
set RX_SAMPLES_PER_CHANNEL [expr ($RX_NUM_OF_LANES*32) / ($RX_NUM_OF_CONVERTERS*$RX_SAMPLE_WIDTH)] ; # (L * 32) / (M * N)
set MAX_RX_NUM_OF_LANES 2
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad6676_xcvr
ad_ip_parameter axi_ad6676_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad6676_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_ad6676_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad6676_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad6676_xcvr CONFIG.LPM_OR_DFE_N 0
ad_ip_parameter axi_ad6676_xcvr CONFIG.SYS_CLK_SEL 0x0
ad_ip_parameter axi_ad6676_xcvr CONFIG.OUT_CLK_SEL 0x4
adi_axi_jesd204_rx_create axi_ad6676_jesd 2
adi_axi_jesd204_rx_create axi_ad6676_jesd $RX_NUM_OF_LANES
#ad_ip_instance axi_ad6676 axi_ad6676_core
adi_tpl_jesd204_rx_create axi_ad6676_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \
ad_ip_instance util_cpack2 axi_ad6676_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance util_cpack2 axi_ad6676_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
ad_ip_instance axi_dmac axi_ad6676_dma
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_TYPE_SRC 2
@ -50,7 +57,7 @@ ad_ip_instance util_adxcvr util_ad6676_xcvr
ad_ip_parameter util_ad6676_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_ad6676_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_ad6676_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_NUM_OF_LANES 2
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_CLK25_DIV 8
ad_ip_parameter util_ad6676_xcvr CONFIG.RX_DFE_LPM_CFG 0x0954
@ -70,7 +77,7 @@ ad_connect $sys_cpu_clk util_ad6676_xcvr/up_clk
# connections (adc)
ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd {} {} {} $MAX_RX_NUM_OF_LANES
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/link_clk
ad_connect util_ad6676_xcvr/rx_out_clk_0 rx_core_clk
ad_connect axi_ad6676_jesd/rx_sof axi_ad6676_core/link_sof
@ -81,7 +88,7 @@ ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/clk
ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/reset
ad_connect axi_ad6676_core/adc_dovf axi_ad6676_cpack/fifo_wr_overflow
ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/fifo_wr_en
for {set i 0} {$i < 2} {incr i} {
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect axi_ad6676_core/adc_enable_${i} axi_ad6676_cpack/enable_${i}
ad_connect axi_ad6676_core/adc_data_${i} axi_ad6676_cpack/fifo_wr_data_${i}
}
@ -110,4 +117,3 @@ ad_connect $sys_dma_resetn axi_ad6676_dma/m_dest_axi_aresetn
ad_cpu_interrupt ps-12 mb-12 axi_ad6676_jesd/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad6676_dma/irq

19
projects/ad6676evb/vc707/system_project.tcl
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@ -1,11 +1,24 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad6676evb_vc707
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=1
# make RX_JESD_L=2
# Parameter description:
# RX_JESD_L : Number of lanes per link
adi_project ad6676evb_vc707 0 [list \
RX_JESD_L [get_env_param RX_JESD_L 2 ] \
]
adi_project_files ad6676evb_vc707 [list \
"system_top.v" \
"system_constr.xdc"\

2
projects/ad6676evb/vc707/system_top.v
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@ -236,7 +236,7 @@ module system_top (
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout));
endmodule

19
projects/ad6676evb/zc706/system_project.tcl
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@ -1,11 +1,24 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad6676evb_zc706
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=1
# make RX_JESD_L=2
# Parameter description:
# RX_JESD_L : Number of lanes per link
adi_project ad6676evb_zc706 0 [list \
RX_JESD_L [get_env_param RX_JESD_L 2 ] \
]
adi_project_files ad6676evb_zc706 [list \
"system_top.v" \
"system_constr.xdc"\

2
projects/ad6676evb/zc706/system_top.v
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@ -114,7 +114,7 @@ module system_top (
wire rx_ref_clk;
wire rx_sync;
wire rx_sysref;
wire rx_clk;
wire rx_clk;
assign gpio_i[63:42]= gpio_o[63:42];
assign gpio_i[31:15]= gpio_o[31:15];