From e9bd4b35120505d7f11f91482cb1b977ae59077a Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 9 Apr 2015 17:58:21 +0300 Subject: [PATCH] axi_dmac: Updated altera core dependency, changed fifo files location --- library/axi_dmac/axi_dmac_hw.tcl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl index 9d8a64667..e9436206c 100755 --- a/library/axi_dmac/axi_dmac_hw.tcl +++ b/library/axi_dmac/axi_dmac_hw.tcl @@ -16,11 +16,11 @@ set_fileset_property quartus_synth TOP_LEVEL axi_dmac add_fileset_file sync_bits.v VERILOG PATH $ad_hdl_dir/library/common/sync_bits.v add_fileset_file sync_gray.v VERILOG PATH $ad_hdl_dir/library/common/sync_gray.v add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v -add_fileset_file axi_fifo.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/axi_fifo.v -add_fileset_file address_gray.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray.v -add_fileset_file address_gray_pipelined.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v -add_fileset_file address_sync.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_sync.v add_fileset_file axi_repack.v VERILOG PATH $ad_hdl_dir/library/util_axis_resize/util_axis_resize.v +add_fileset_file fifo.v VERILOG PATH fifo.v +add_fileset_file address_gray.v VERILOG PATH address_gray.v +add_fileset_file address_gray_pipelined.v VERILOG PATH address_gray_pipelined.v +add_fileset_file address_sync.v VERILOG PATH address_sync.v add_fileset_file inc_id.h VERILOG_INCLUDE PATH inc_id.h add_fileset_file resp.h VERILOG_INCLUDE PATH resp.h add_fileset_file address_generator.v VERILOG PATH address_generator.v