fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
AndreiGrozav
parent
4f0d7bd6eb
commit
e9fe752b7a
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@ -1,613 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags=""
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element adc_pack
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{
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datum _sortIndex
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{
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value = "3";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element axi_ad9361
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element axi_ad9361.s_axi
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{
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datum baseAddress
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{
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value = "131072";
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type = "String";
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}
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}
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element axi_dmac_adc
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{
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datum _sortIndex
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{
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value = "4";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element axi_dmac_adc.s_axi
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{
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datum baseAddress
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{
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value = "0";
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type = "String";
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}
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}
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element axi_dmac_dac
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{
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datum _sortIndex
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{
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value = "6";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element axi_dmac_dac.s_axi
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{
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datum baseAddress
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{
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value = "16384";
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type = "String";
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}
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}
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element dac_upack
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{
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datum _sortIndex
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{
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value = "5";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element sys_clk
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element sys_rst
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="FIFO" />
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<parameter name="device" value="10AS066N3F40E2SGE2" />
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<parameter name="deviceFamily" value="Arria 10" />
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<parameter name="deviceSpeedGrade" value="2" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="2" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="axi_ad9361_delay_clk"
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internal="axi_ad9361.if_delay_clk"
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type="clock"
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dir="end" />
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<interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
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<interface
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name="axi_ad9361_device_if"
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internal="axi_ad9361.device_if"
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type="conduit"
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dir="end" />
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<interface
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name="axi_ad9361_s_axi"
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internal="axi_ad9361.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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name="axi_ad9361_up_enable"
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internal="axi_ad9361.if_up_enable"
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type="conduit"
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dir="end" />
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<interface
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name="axi_ad9361_up_txnrx"
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internal="axi_ad9361.if_up_txnrx"
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type="conduit"
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dir="end" />
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<interface
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name="axi_dmac_adc_fifo_wr_clock"
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internal="axi_dmac_adc.fifo_wr_clock" />
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<interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
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<interface
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name="axi_dmac_adc_intr"
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internal="axi_dmac_adc.interrupt_sender"
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type="interrupt"
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dir="end" />
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<interface
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name="axi_dmac_adc_m_dest_axi"
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internal="axi_dmac_adc.m_dest_axi"
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type="axi4"
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dir="start" />
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<interface
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name="axi_dmac_adc_s_axi"
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internal="axi_dmac_adc.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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name="axi_dmac_dac_fifo_rd_clock"
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internal="axi_dmac_dac.fifo_rd_clock" />
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<interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
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<interface
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name="axi_dmac_dac_intr"
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internal="axi_dmac_dac.interrupt_sender"
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type="interrupt"
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dir="end" />
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<interface
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name="axi_dmac_dac_m_src_axi"
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internal="axi_dmac_dac.m_src_axi"
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type="axi4"
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dir="start" />
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<interface
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name="axi_dmac_dac_s_axi"
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internal="axi_dmac_dac.s_axi"
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type="axi4lite"
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dir="end" />
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<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
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<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
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<module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
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<parameter name="CHANNEL_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
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<parameter name="ADC_DATAPATH_DISABLE" value="0" />
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<parameter name="CMOS_OR_LVDS_N" value="0" />
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<parameter name="DAC_DATAPATH_DISABLE" value="0" />
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<parameter name="DEVICE_FAMILY" value="Arria 10" />
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<parameter name="DEVICE_TYPE" value="0" />
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<parameter name="ID" value="0" />
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</module>
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<module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
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<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
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<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
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<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
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<parameter name="AXI_SLICE_DEST" value="0" />
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<parameter name="AXI_SLICE_SRC" value="0" />
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<parameter name="CYCLIC" value="0" />
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<parameter name="DMA_2D_TRANSFER" value="0" />
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<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
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<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
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<parameter name="DMA_LENGTH_WIDTH" value="24" />
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<parameter name="DMA_TYPE_DEST" value="0" />
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<parameter name="DMA_TYPE_SRC" value="2" />
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<parameter name="FIFO_SIZE" value="4" />
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="1" />
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</module>
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<module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
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<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
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<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
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<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
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<parameter name="AXI_SLICE_DEST" value="0" />
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<parameter name="AXI_SLICE_SRC" value="0" />
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<parameter name="CYCLIC" value="1" />
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<parameter name="DMA_2D_TRANSFER" value="0" />
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<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
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<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
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<parameter name="DMA_LENGTH_WIDTH" value="24" />
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<parameter name="DMA_TYPE_DEST" value="2" />
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<parameter name="DMA_TYPE_SRC" value="0" />
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<parameter name="FIFO_SIZE" value="4" />
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="0" />
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</module>
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<module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
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<parameter name="CHANNEL_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
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<parameter name="DERIVED_CLOCK_RATE" value="0" />
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<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
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<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
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</module>
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<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
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<parameter name="ACTIVE_LOW_RESET" value="0" />
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
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<parameter name="NUM_RESET_OUTPUTS" value="1" />
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<parameter name="SYNCHRONOUS_EDGES" value="none" />
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<parameter name="USE_RESET_REQUEST" value="0" />
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</module>
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="adc_pack.if_adc_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="axi_ad9361.if_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="dac_upack.if_dac_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="axi_dmac_dac.if_fifo_rd_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="axi_dmac_adc.if_fifo_wr_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="sys_clk.out_clk"
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end="axi_dmac_adc.m_dest_axi_clock" />
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<connection
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kind="clock"
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version="15.1"
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start="sys_clk.out_clk"
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end="axi_dmac_dac.m_src_axi_clock" />
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<connection
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kind="clock"
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version="15.1"
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start="sys_clk.out_clk"
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end="axi_ad9361.s_axi_clock" />
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<connection
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kind="clock"
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version="15.1"
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start="sys_clk.out_clk"
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end="axi_dmac_adc.s_axi_clock" />
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<connection
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kind="clock"
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version="15.1"
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start="sys_clk.out_clk"
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end="axi_dmac_dac.s_axi_clock" />
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<connection
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kind="conduit"
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version="15.1"
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start="dac_upack.fifo_ch_0"
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end="axi_ad9361.fifo_ch_0_out">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_0_in"
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end="adc_pack.fifo_ch_0">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_1_in"
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end="adc_pack.fifo_ch_1">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_1_out"
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end="dac_upack.fifo_ch_1">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_2_in"
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end="adc_pack.fifo_ch_2">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_2_out"
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end="dac_upack.fifo_ch_2">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
|
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_3_in"
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end="adc_pack.fifo_ch_3">
|
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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||||
<parameter name="width" value="0" />
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||||
</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.fifo_ch_3_out"
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end="dac_upack.fifo_ch_3">
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<parameter name="endPort" value="" />
|
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<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
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||||
<parameter name="startPortLSB" value="0" />
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||||
<parameter name="width" value="0" />
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||||
</connection>
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<connection
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kind="conduit"
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version="15.1"
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||||
start="adc_pack.if_adc_data"
|
||||
end="axi_dmac_adc.if_fifo_wr_din">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="adc_pack.if_adc_sync"
|
||||
end="axi_dmac_adc.if_fifo_wr_sync">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="adc_pack.if_adc_valid"
|
||||
end="axi_dmac_adc.if_fifo_wr_en">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.if_dac_data"
|
||||
end="axi_dmac_dac.if_fifo_rd_dout">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.if_dma_xfer_in"
|
||||
end="axi_dmac_dac.if_fifo_rd_xfer_req">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_dac.if_fifo_rd_en"
|
||||
end="dac_upack.if_dac_valid">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_dac.if_fifo_rd_underflow"
|
||||
end="axi_ad9361.if_dac_dunf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_adc.if_fifo_wr_overflow"
|
||||
end="axi_ad9361.if_adc_dovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_adc.m_dest_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_dac.m_src_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_ad9361.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_adc.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_dac.s_axi_reset" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_0|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_2|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
</system>
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
|
||||
# fmcomms2
|
||||
|
||||
# ad9361 core
|
||||
|
||||
add_instance axi_ad9361 axi_ad9361 1.0
|
||||
set_instance_parameter_value axi_ad9361 {ID} {0}
|
||||
|
||||
add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9361.s_axi_clock
|
||||
add_connection sys_cpu.data_master axi_ad9361.s_axi
|
||||
add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
|
||||
|
||||
# ad9361-unpack (dac)
|
||||
|
||||
add_instance util_ad9361_dac_upack util_upack 1.0
|
||||
set_instance_parameter_value util_ad9361_dac_upack {CHANNEL_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_ad9361_dac_upack {NUM_OF_CHANNELS} {4}
|
||||
|
||||
add_connection axi_ad9361.if_l_clk util_ad9361_dac_upack.if_dac_clk
|
||||
|
||||
# ad9361-dma (dac)
|
||||
|
||||
add_instance axi_ad9361_dac_dma axi_dmac 1.0
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {DMA_DATA_WIDTH_DEST} {64}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_DEST} {2}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {DMA_TYPE_SRC} {0}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {CYCLIC} {1}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {SYNC_TRANSFER_START} {0}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_ad9361_dac_dma {AXI_SLICE_DEST} {1}
|
||||
|
||||
add_connection sys_clk.clk_reset axi_ad9361_dac_dma.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9361_dac_dma.s_axi_clock
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_dac_dma.m_src_axi_reset
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_dac_dma.m_src_axi_clock
|
||||
add_connection axi_ad9361_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
|
||||
add_connection sys_cpu.irq axi_ad9361_dac_dma.interrupt_sender
|
||||
|
||||
# dac path connections
|
||||
|
||||
add_connection sys_cpu.data_master axi_ad9361_dac_dma.s_axi
|
||||
add_connection util_ad9361_dac_upack.if_dac_valid axi_ad9361_dac_dma.if_fifo_rd_en
|
||||
add_connection util_ad9361_dac_upack.if_dac_data axi_ad9361_dac_dma.if_fifo_rd_dout
|
||||
add_connection axi_ad9361_dac_dma.if_fifo_rd_underflow axi_ad9361.if_dac_dunf
|
||||
add_connection util_ad9361_dac_upack.dac_ch_0 axi_ad9361.dac_ch_0
|
||||
add_connection util_ad9361_dac_upack.dac_ch_1 axi_ad9361.dac_ch_1
|
||||
add_connection util_ad9361_dac_upack.dac_ch_2 axi_ad9361.dac_ch_2
|
||||
add_connection util_ad9361_dac_upack.dac_ch_3 axi_ad9361.dac_ch_3
|
||||
add_connection axi_ad9361.if_l_clk axi_ad9361_dac_dma.if_fifo_rd_clk
|
||||
|
||||
# ad9361-adc-fifo
|
||||
|
||||
add_instance util_ad9361_adc_fifo util_wfifo 1.0
|
||||
set_instance_parameter_value util_ad9361_adc_fifo {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value util_ad9361_adc_fifo {DIN_ADDRESS_WIDTH} {4}
|
||||
set_instance_parameter_value util_ad9361_adc_fifo {DIN_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_ad9361_adc_fifo {DOUT_DATA_WIDTH} {16}
|
||||
|
||||
add_connection axi_ad9361.if_l_clk util_ad9361_adc_fifo.if_din_clk
|
||||
add_connection axi_ad9361.if_rst util_ad9361_adc_fifo.if_din_rst
|
||||
add_connection sys_clk.clk_reset util_ad9361_adc_fifo.if_dout_rstn
|
||||
add_connection sys_clk.clk util_ad9361_adc_fifo.if_dout_clk
|
||||
|
||||
# ad9361-pack (adc)
|
||||
|
||||
add_instance util_ad9361_adc_cpack util_cpack 1.0
|
||||
set_instance_parameter_value util_ad9361_adc_cpack {CHANNEL_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_ad9361_adc_cpack {NUM_OF_CHANNELS} {4}
|
||||
|
||||
add_connection sys_clk.clk util_ad9361_adc_cpack.if_adc_clk
|
||||
add_connection sys_clk.clk_reset util_ad9361_adc_cpack.if_adc_rst
|
||||
|
||||
# ad9361-dma (adc)
|
||||
|
||||
add_instance axi_ad9361_adc_dma axi_dmac 1.0
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {DMA_DATA_WIDTH_SRC} {64}
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {SYNC_TRANSFER_START} {1}
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {CYCLIC} {0}
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_DEST} {0}
|
||||
set_instance_parameter_value axi_ad9361_adc_dma {DMA_TYPE_SRC} {2}
|
||||
|
||||
add_connection sys_clk.clk_reset axi_ad9361_adc_dma.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9361_adc_dma.s_axi_clock
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9361_adc_dma.m_dest_axi_reset
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9361_adc_dma.m_dest_axi_clock
|
||||
add_connection sys_clk.clk axi_ad9361_adc_dma.if_fifo_wr_clk
|
||||
add_connection sys_cpu.irq axi_ad9361_adc_dma.interrupt_sender
|
||||
add_connection axi_ad9361_adc_dma.if_fifo_wr_overflow util_ad9361_adc_fifo.if_dout_ovf
|
||||
add_connection axi_ad9361_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
|
||||
|
||||
# adc path connections
|
||||
|
||||
add_connection axi_ad9361.adc_ch_0 util_ad9361_adc_fifo.din_0
|
||||
add_connection axi_ad9361.adc_ch_1 util_ad9361_adc_fifo.din_1
|
||||
add_connection axi_ad9361.adc_ch_2 util_ad9361_adc_fifo.din_2
|
||||
add_connection axi_ad9361.adc_ch_3 util_ad9361_adc_fifo.din_3
|
||||
add_connection util_ad9361_adc_fifo.if_din_ovf axi_ad9361.if_adc_dovf
|
||||
add_connection util_ad9361_adc_fifo.dout_0 util_ad9361_adc_cpack.adc_ch_0
|
||||
add_connection util_ad9361_adc_fifo.dout_1 util_ad9361_adc_cpack.adc_ch_1
|
||||
add_connection util_ad9361_adc_fifo.dout_2 util_ad9361_adc_cpack.adc_ch_2
|
||||
add_connection util_ad9361_adc_fifo.dout_3 util_ad9361_adc_cpack.adc_ch_3
|
||||
add_connection util_ad9361_adc_cpack.if_adc_valid axi_ad9361_adc_dma.if_fifo_wr_en
|
||||
add_connection util_ad9361_adc_cpack.if_adc_sync axi_ad9361_adc_dma.if_fifo_wr_sync
|
||||
add_connection util_ad9361_adc_cpack.if_adc_data axi_ad9361_adc_dma.if_fifo_wr_din
|
||||
add_connection sys_cpu.data_master axi_ad9361_adc_dma.s_axi
|
||||
add_interface up_enable conduit end
|
||||
add_interface up_txnrx conduit end
|
||||
add_interface delay_clk conduit end
|
||||
|
||||
# setting interface propriety
|
||||
|
||||
set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
|
||||
set_interface_property up_enable EXPORT_OF axi_ad9361.if_up_enable
|
||||
set_interface_property up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
|
||||
set_interface_property delay_clk EXPORT_OF axi_ad9361.if_delay_clk
|
||||
|
||||
# addresses
|
||||
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9361.s_axi baseAddress {0x10000000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9361_dac_dma.s_axi baseAddress {0x10034000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9361_adc_dma.s_axi baseAddress {0x10010000}
|
||||
|
||||
set_connection_parameter_value axi_ad9361_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value axi_ad9361_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
|
||||
|
||||
# interrupts
|
||||
|
||||
set_connection_parameter_value sys_cpu.irq/axi_ad9361_adc_dma.interrupt_sender irqNumber {10}
|
||||
set_connection_parameter_value sys_cpu.irq/axi_ad9361_dac_dma.interrupt_sender irqNumber {11}
|
||||
|
||||
Loading…
Reference in New Issue