zc702: Updated base design to the latest model
Adrian Costina
parent
17d8c1b72b
commit
ea303c6f61
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@ -2,29 +2,66 @@
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# create board design
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# interface ports
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set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
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set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
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set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
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set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
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set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi1_csn_2_o
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create_bd_port -dir O spi1_csn_1_o
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create_bd_port -dir O spi1_csn_0_o
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create_bd_port -dir I spi1_csn_i
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create_bd_port -dir I spi1_clk_i
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create_bd_port -dir O spi1_clk_o
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create_bd_port -dir I spi1_sdo_i
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create_bd_port -dir O spi1_sdo_o
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create_bd_port -dir I spi1_sdi_i
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create_bd_port -dir I -from 63 -to 0 gpio_i
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create_bd_port -dir O -from 63 -to 0 gpio_o
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create_bd_port -dir O -from 63 -to 0 gpio_t
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# hdmi interface
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set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
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set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
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set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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create_bd_port -dir O hdmi_out_clk
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create_bd_port -dir O hdmi_hsync
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create_bd_port -dir O hdmi_vsync
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create_bd_port -dir O hdmi_data_e
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create_bd_port -dir O -from 15 -to 0 hdmi_data
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# spdif audio
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set spdif [create_bd_port -dir O spdif]
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create_bd_port -dir O spdif
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7]
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC702}] $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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@ -35,8 +72,12 @@ set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
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@ -44,10 +85,6 @@ set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
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set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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@ -61,9 +98,6 @@ set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
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# audio peripherals
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
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@ -78,140 +112,102 @@ set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
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# system reset/clock definitions
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set sys_100m_clk_source [get_bd_pins sys_ps7/FCLK_CLK0]
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set sys_200m_clk_source [get_bd_pins sys_ps7/FCLK_CLK1]
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ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
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ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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connect_bd_net -net sys_100m_clk $sys_100m_clk_source
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connect_bd_net -net sys_200m_clk $sys_200m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
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connect_bd_net -net sys_aux_reset [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins sys_ps7/FCLK_RESET0_N]
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set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
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set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
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connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source
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connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source
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# interface connections
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connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR]
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connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I]
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connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
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connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
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connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
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connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_main/iic]
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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ad_connect iic_main axi_iic_main/iic
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ad_connect sys_200m_clk axi_hdmi_clkgen/clk
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source
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# spi connections
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connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
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ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
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ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
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ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
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ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
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ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
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ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
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ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
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ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
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ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
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# hdmi
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
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connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
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connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
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ad_connect sys_cpu_clk axi_hdmi_clkgen/drp_clk
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ad_connect sys_cpu_clk axi_hdmi_core/m_axis_mm2s_clk
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ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
|
||||
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
|
||||
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
|
||||
ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
|
||||
ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync
|
||||
ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e
|
||||
ad_connect axi_hdmi_core/hdmi_16_data hdmi_data
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tvalid axi_hdmi_dma/m_axis_mm2s_tvalid
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tdata axi_hdmi_dma/m_axis_mm2s_tdata
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tkeep axi_hdmi_dma/m_axis_mm2s_tkeep
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tlast axi_hdmi_dma/m_axis_mm2s_tlast
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tready axi_hdmi_dma/m_axis_mm2s_tready
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_dma/mm2s_fsync
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_core/m_axis_mm2s_fsync_ret
|
||||
|
||||
# spdif audio
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN]
|
||||
connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ]
|
||||
connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||
ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
|
||||
ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
|
||||
ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
|
||||
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
|
||||
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
|
||||
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
|
||||
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
|
||||
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
|
||||
ad_connect spdif axi_spdif_tx_core/spdif_tx_o
|
||||
|
||||
# match up interconnects
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
# interrupts
|
||||
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||
|
||||
for {set intc_index 0} {$intc_index < 14} {incr intc_index} {
|
||||
set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}]
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}]
|
||||
}
|
||||
ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
|
||||
ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
|
||||
ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
|
||||
ad_connect sys_concat_intc/In13 ps_intr_13
|
||||
ad_connect sys_concat_intc/In12 ps_intr_12
|
||||
ad_connect sys_concat_intc/In11 ps_intr_11
|
||||
ad_connect sys_concat_intc/In10 ps_intr_10
|
||||
ad_connect sys_concat_intc/In9 ps_intr_09
|
||||
ad_connect sys_concat_intc/In8 ps_intr_08
|
||||
ad_connect sys_concat_intc/In7 ps_intr_07
|
||||
ad_connect sys_concat_intc/In6 ps_intr_06
|
||||
ad_connect sys_concat_intc/In5 ps_intr_05
|
||||
ad_connect sys_concat_intc/In4 ps_intr_04
|
||||
ad_connect sys_concat_intc/In3 ps_intr_03
|
||||
ad_connect sys_concat_intc/In2 ps_intr_02
|
||||
ad_connect sys_concat_intc/In1 ps_intr_01
|
||||
ad_connect sys_concat_intc/In0 ps_intr_00
|
||||
|
||||
# address map
|
||||
|
||||
set sys_zynq 1
|
||||
set sys_mem_size 0x40000000
|
||||
set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_main
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
|
||||
|
||||
ad_cpu_interconnect 0x41600000 axi_iic_main
|
||||
ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
|
||||
ad_cpu_interconnect 0x43000000 axi_hdmi_dma
|
||||
ad_cpu_interconnect 0x70e00000 axi_hdmi_core
|
||||
ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
|
||||
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
|
||||
|
|
|
|||
Loading…
Reference in New Issue