altera- remove default assignments from procedure

2017-06-05 15:25:38 -04:00 · 2017-06-05 15:25:38 -04:00 · eadbf9ae30
parent 0bd22e78d9
commit eadbf9ae30
1 changed files with 0 additions and 6 deletions
--- a/projects/scripts/adi_project_alt.tcl
+++ b/projects/scripts/adi_project_alt.tcl
@ -78,12 +78,6 @@ proc adi_project_create {project_name} {
    system_bd.qsys --synthesis=VERILOG --output-directory=system_bd \
    --family=$family --part=$device

-  # carrier assignments
- 
-  if [regexp "_a10gx$" $project_name] {
-    source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
-  }
-
  # ignored warnings and such

  set_global_assignment -name MESSAGE_DISABLE 17951 ; ## unused RX channels