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axi_ad7768: modified adc_format values and crc_err flag has to be RW1C

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PopPaul2021 2022-11-15 15:35:49 +02:00 committed by PopPaul2021
parent 72313df81f
commit eb663876d7
2 changed files with 69 additions and 61 deletions
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14
library/axi_ad7768/axi_ad7768_if.v
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@ -352,8 +352,8 @@ module axi_ad7768_if #(
// data capturing counter // data capturing counter
assign adc_cnt_value = (adc_format == 'h0 && NUM_CHANNELS == 8 ) ? 'hff : assign adc_cnt_value = (adc_format == 'h1 && NUM_CHANNELS == 8) ? 'hff :
(( adc_format == 'h1 || (adc_format == 'h0 && NUM_CHANNELS == 4 )) ? 'h7f : 'h1f ); (((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) ? 'h7f : 'h1f);
assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0; assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0;
@ -398,7 +398,7 @@ module axi_ad7768_if #(
always @(posedge adc_clk) begin always @(posedge adc_clk) begin
if (adc_valid_p == 1'b1) begin if (adc_valid_p == 1'b1) begin
if( adc_format == 'h0 && NUM_CHANNELS == 8 ) begin // 1 active line if(adc_format == 'h1 && NUM_CHANNELS == 8) begin // 1 active line
adc_data_s[0] <= adc_data_p[((32*7)+31):(32*7)]; adc_data_s[0] <= adc_data_p[((32*7)+31):(32*7)];
adc_data_s[1] <= adc_data_p[((32*6)+31):(32*6)]; adc_data_s[1] <= adc_data_p[((32*6)+31):(32*6)];
adc_data_s[2] <= adc_data_p[((32*5)+31):(32*5)]; adc_data_s[2] <= adc_data_p[((32*5)+31):(32*5)];
@ -407,7 +407,7 @@ module axi_ad7768_if #(
adc_data_s[5] <= adc_data_p[((32*2)+31):(32*2)]; adc_data_s[5] <= adc_data_p[((32*2)+31):(32*2)];
adc_data_s[6] <= adc_data_p[((32*1)+31):(32*1)]; adc_data_s[6] <= adc_data_p[((32*1)+31):(32*1)];
adc_data_s[7] <= adc_data_p[((32*0)+31):(32*0)]; adc_data_s[7] <= adc_data_p[((32*0)+31):(32*0)];
end else if( adc_format == 'h1 || (adc_format == 'h0 && NUM_CHANNELS == 4 )) begin // 2 active lines or 1 for ad7768-4 end else if((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) begin // 2 active lines or 1 for ad7768-4
adc_data_s[0] <= adc_data_p[((32*3)+31):(32*3)]; adc_data_s[0] <= adc_data_p[((32*3)+31):(32*3)];
adc_data_s[1] <= adc_data_p[((32*2)+31):(32*2)]; adc_data_s[1] <= adc_data_p[((32*2)+31):(32*2)];
adc_data_s[2] <= adc_data_p[((32*1)+31):(32*1)]; adc_data_s[2] <= adc_data_p[((32*1)+31):(32*1)];
@ -443,13 +443,13 @@ module axi_ad7768_if #(
// data (individual lanes) // data (individual lanes)
always @(negedge adc_clk) begin always @(negedge adc_clk) begin
if( adc_format == 'h0 && NUM_CHANNELS == 8 ) begin // 1 active line for ad7768 if(adc_format == 'h1 && NUM_CHANNELS == 8) begin // 1 active line for ad7768
if (adc_cnt_p == 'h0) begin if (adc_cnt_p == 'h0) begin
adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]}; adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]};
end else begin end else begin
adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]}; adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]};
end end
end else if( adc_format == 'h1 || (adc_format == 'h0 && NUM_CHANNELS == 4 )) begin // 2 active lines or 1 active lane for ad7768-4 end else if((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) begin // 2 active lines or 1 active lane for ad7768-4
if (adc_cnt_p == 'h0) begin if (adc_cnt_p == 'h0) begin
adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]}; adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]}; adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]};
@ -457,7 +457,7 @@ module axi_ad7768_if #(
adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]}; adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]}; adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]};
end end
end else if( adc_format == 'h2 ) begin // 8 active lines or 4 active lane for ad7768-4 end else begin // 8 active lines or 4 active lane for ad7768-4
if (adc_cnt_p == 'h0) begin if (adc_cnt_p == 'h0) begin
adc_data_p[((32*0)+31):(32*0)] <= {31'd0, data_in[0]}; adc_data_p[((32*0)+31):(32*0)] <= {31'd0, data_in[0]};
adc_data_p[((32*1)+31):(32*1)] <= {31'd0, data_in[1]}; adc_data_p[((32*1)+31):(32*1)] <= {31'd0, data_in[1]};

14
library/common/up_adc_channel.v
View File

@ -69,6 +69,7 @@ module up_adc_channel #(
input [31:0] adc_read_data, input [31:0] adc_read_data,
input [ 7:0] adc_status_header, input [ 7:0] adc_status_header,
input adc_crc_err, input adc_crc_err,
output up_adc_crc_err,
output up_adc_pn_err, output up_adc_pn_err,
output up_adc_pn_oos, output up_adc_pn_oos,
output up_adc_or, output up_adc_or,
@ -116,6 +117,7 @@ module up_adc_channel #(
reg up_adc_dfmt_enable = 'd0; reg up_adc_dfmt_enable = 'd0;
reg up_adc_pn_type = 'd0; reg up_adc_pn_type = 'd0;
reg up_adc_enable = 'd0; reg up_adc_enable = 'd0;
reg up_adc_crc_err_int = 'd0;
reg up_adc_pn_err_int = 'd0; reg up_adc_pn_err_int = 'd0;
reg up_adc_pn_oos_int = 'd0; reg up_adc_pn_oos_int = 'd0;
reg up_adc_or_int = 'd0; reg up_adc_or_int = 'd0;
@ -143,12 +145,12 @@ module up_adc_channel #(
wire up_wreq_s; wire up_wreq_s;
wire up_rreq_s; wire up_rreq_s;
wire up_adc_crc_err_s;
wire up_adc_pn_err_s; wire up_adc_pn_err_s;
wire up_adc_pn_oos_s; wire up_adc_pn_oos_s;
wire up_adc_or_s; wire up_adc_or_s;
wire [31:0] up_adc_read_data_s; wire [31:0] up_adc_read_data_s;
wire [ 7:0] up_adc_status_header_s; wire [ 7:0] up_adc_status_header_s;
wire up_adc_crc_err_s;
// 2's complement function // 2's complement function
@ -166,7 +168,7 @@ module up_adc_channel #(
endfunction endfunction
// up control/status // up control/status
assign up_adc_crc_err = up_adc_crc_err_int;
assign up_adc_pn_err = up_adc_pn_err_int; assign up_adc_pn_err = up_adc_pn_err_int;
assign up_adc_pn_oos = up_adc_pn_oos_int; assign up_adc_pn_oos = up_adc_pn_oos_int;
assign up_adc_or = up_adc_or_int; assign up_adc_or = up_adc_or_int;
@ -265,6 +267,7 @@ module up_adc_channel #(
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_adc_pn_type <= 'd0; up_adc_pn_type <= 'd0;
up_adc_enable <= 'd0; up_adc_enable <= 'd0;
up_adc_crc_err_int <= 'd0;
up_adc_pn_err_int <= 'd0; up_adc_pn_err_int <= 'd0;
up_adc_pn_oos_int <= 'd0; up_adc_pn_oos_int <= 'd0;
up_adc_or_int <= 'd0; up_adc_or_int <= 'd0;
@ -273,6 +276,11 @@ module up_adc_channel #(
up_adc_pn_type <= up_wdata[1]; up_adc_pn_type <= up_wdata[1];
up_adc_enable <= up_wdata[0]; up_adc_enable <= up_wdata[0];
end end
if (up_adc_crc_err_s == 1'b1) begin
up_adc_crc_err_int <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_adc_crc_err_int <= up_adc_crc_err_int & ~up_wdata[12];
end
if (up_adc_pn_err_s == 1'b1) begin if (up_adc_pn_err_s == 1'b1) begin
up_adc_pn_err_int <= 1'b1; up_adc_pn_err_int <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
@ -400,7 +408,7 @@ module up_adc_channel #(
up_adc_iqcor_enb, up_adc_dcfilt_enb, up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable, 1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable}; 2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata_int <= { 19'd0, up_adc_crc_err_s, up_adc_status_header_s, 1'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int}; 4'h1: up_rdata_int <= { 19'd0, up_adc_crc_err_int, up_adc_status_header_s, 1'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int};
4'h2: up_rdata_int <= { up_adc_read_data_s}; 4'h2: up_rdata_int <= { up_adc_read_data_s};
4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff}; 4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2}; 4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};