spi_engine: Update util_axis_fifo instances
parent
5ac728392d
commit
eb7e533d66
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@ -9,6 +9,8 @@ GENERIC_DEPS += ../../common/ad_rst.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += axi_spi_engine.v
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GENERIC_DEPS += axi_spi_engine.v
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XILINX_DEPS += ../../common/ad_rst.v
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XILINX_DEPS += ../../common/up_axi.v
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += axi_spi_engine_constr.ttcl
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XILINX_DEPS += axi_spi_engine_constr.ttcl
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XILINX_DEPS += axi_spi_engine_ip.tcl
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XILINX_DEPS += axi_spi_engine_ip.tcl
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@ -404,9 +404,9 @@ module axi_spi_engine #(
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util_axis_fifo #(
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util_axis_fifo #(
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.DATA_WIDTH(16),
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.DATA_WIDTH(16),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.M_AXIS_REGISTERED(0)
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) i_cmd_fifo (
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) i_cmd_fifo (
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.s_axis_aclk(clk),
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.s_axis_aclk(clk),
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.s_axis_aresetn(up_sw_resetn),
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.s_axis_aresetn(up_sw_resetn),
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@ -414,12 +414,14 @@ module axi_spi_engine #(
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.s_axis_valid(cmd_fifo_in_valid),
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.s_axis_valid(cmd_fifo_in_valid),
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.s_axis_data(cmd_fifo_in_data),
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.s_axis_data(cmd_fifo_in_data),
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.s_axis_room(cmd_fifo_room),
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.s_axis_room(cmd_fifo_room),
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.s_axis_empty(),
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.s_axis_full(),
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.s_axis_room(),
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.m_axis_aclk(spi_clk),
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.m_axis_aclk(spi_clk),
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.m_axis_aresetn(spi_resetn),
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.m_axis_aresetn(spi_resetn),
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.m_axis_ready(cmd_ready),
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.m_axis_ready(cmd_ready),
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.m_axis_valid(cmd_valid),
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.m_axis_valid(cmd_valid),
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.m_axis_data(cmd_data),
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.m_axis_data(cmd_data),
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.m_axis_empty(),
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.m_axis_level()
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.m_axis_level()
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);
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);
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@ -432,7 +434,7 @@ module axi_spi_engine #(
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.DATA_WIDTH(DATA_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.M_AXIS_REGISTERED(0)
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) i_sdo_fifo (
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) i_sdo_fifo (
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.s_axis_aclk(clk),
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.s_axis_aclk(clk),
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.s_axis_aresetn(up_sw_resetn),
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.s_axis_aresetn(up_sw_resetn),
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@ -457,7 +459,7 @@ module axi_spi_engine #(
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.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
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.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.M_AXIS_REGISTERED(0)
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) i_sdi_fifo (
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) i_sdi_fifo (
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.s_axis_aclk(spi_clk),
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.s_axis_aclk(spi_clk),
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.s_axis_aresetn(spi_resetn),
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.s_axis_aresetn(spi_resetn),
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@ -481,7 +483,7 @@ module axi_spi_engine #(
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.DATA_WIDTH(8),
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.DATA_WIDTH(8),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.M_AXIS_REGISTERED(0)
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) i_sync_fifo (
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) i_sync_fifo (
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.s_axis_aclk(spi_clk),
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.s_axis_aclk(spi_clk),
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.s_axis_aresetn(spi_resetn),
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.s_axis_aresetn(spi_resetn),
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@ -506,7 +508,7 @@ module axi_spi_engine #(
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.DATA_WIDTH(16),
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.DATA_WIDTH(16),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.M_AXIS_REGISTERED(0)
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) i_offload_cmd_fifo (
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) i_offload_cmd_fifo (
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.s_axis_aclk(clk),
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.s_axis_aclk(clk),
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.s_axis_aresetn(up_sw_resetn),
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.s_axis_aresetn(up_sw_resetn),
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@ -534,7 +536,7 @@ module axi_spi_engine #(
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.DATA_WIDTH(DATA_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.M_AXIS_REGISTERED(0)
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) i_offload_sdo_fifo (
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) i_offload_sdo_fifo (
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.s_axis_aclk(clk),
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.s_axis_aclk(clk),
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.s_axis_aresetn(up_sw_resetn),
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.s_axis_aresetn(up_sw_resetn),
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@ -559,7 +561,7 @@ module axi_spi_engine #(
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.DATA_WIDTH(8),
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.DATA_WIDTH(8),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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.M_AXIS_REGISTERED(0)
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) i_offload_sync_fifo (
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) i_offload_sync_fifo (
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.s_axis_aclk(spi_clk),
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.s_axis_aclk(spi_clk),
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.s_axis_aresetn(spi_resetn),
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.s_axis_aresetn(spi_resetn),
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