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ad9082_fmca_ebz: Use 9081 system_bd, updated comments

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Laszlo Nagy 2021-05-05 12:47:13 +01:00 committed by Laszlo Nagy
parent 0d9e38bdbe
commit eba3409d78
6 changed files with 23 additions and 172 deletions
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62
projects/ad9082_fmca_ebz/vcu118/system_bd.tcl
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@ -1,63 +1,3 @@
## ADC FIFO depth in samples per converter
set adc_fifo_samples_per_converter [expr 64*1024]
## DAC FIFO depth in samples per converter
set dac_fifo_samples_per_converter [expr 64*1024]
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
if {$ad_project_params(JESD_MODE) == "8B10B"} {
# Parameters for 15.5Gpbs lane rate
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x2b
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x4040
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3002
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2 0x1E9
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x1
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_XMODE_SEL 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3100
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xB00
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2ff
} else {
set_property -dict [list CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {50}] [get_bd_cells axi_ddr_cntrl]
ad_connect /axi_ddr_cntrl/addn_ui_clkout4 jesd204_phy_121/drpclk
ad_connect /axi_ddr_cntrl/addn_ui_clkout4 jesd204_phy_126/drpclk
}
source $ad_hdl_dir/projects/ad9081_fmca_ebz/vcu118/system_bd.tcl

25
projects/ad9082_fmca_ebz/vcu118/system_project.tcl
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@ -9,26 +9,18 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# Use over-writable parameters from the environment.
#
# e.g.
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
# RX_RATE,TX_RATE,REF_CLK_RATE used only in 64B66B mode
#
# Parameter description:
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
# Encoding is:
# 0 - CPLL
# 1 - QPLL0
# 2 - QPLL1
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
@ -37,11 +29,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9082_fmca_ebz_vcu118 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_RATE [get_env_param RX_RATE 10 ] \
RX_PLL_SEL [get_env_param RX_PLL_SEL 1 ] \
TX_RATE [get_env_param TX_RATE 10 ] \
TX_PLL_SEL [get_env_param TX_PLL_SEL 1 ] \
REF_CLK_RATE [get_env_param REF_CLK_RATE 250 ] \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 4 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
@ -52,6 +41,8 @@ adi_project ad9082_fmca_ebz_vcu118 0 [list \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \
TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \
]
adi_project_files ad9082_fmca_ebz_vcu118 [list \

20
projects/ad9082_fmca_ebz/zc706/system_bd.tcl
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@ -1,20 +1,2 @@
## ADC FIFO depth in samples per converter
set adc_fifo_samples_per_converter [expr 32*1024]
## DAC FIFO depth in samples per converter
set dac_fifo_samples_per_converter [expr 32*1024]
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
source $ad_hdl_dir/projects/ad9081_fmca_ebz/zc706/system_bd.tcl

16
projects/ad9082_fmca_ebz/zc706/system_project.tcl
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@ -14,17 +14,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
# Parameter description:
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
# 64B66B - 64b66b link layer defined in JESD 204C
# 8B10B - 8b10b link layer defined in JESD 204B
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
# Encoding is:
# 0 - CPLL
# 1 - QPLL0
# 2 - QPLL1
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
@ -36,6 +30,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9082_fmca_ebz_zc706 0 [list \
JESD_MODE 8B10B \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 4 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \

56
projects/ad9082_fmca_ebz/zcu102/system_bd.tcl
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@ -1,57 +1,3 @@
## ADC FIFO depth in samples per converter
set adc_fifo_samples_per_converter [expr 64*1024]
## DAC FIFO depth in samples per converter
set dac_fifo_samples_per_converter [expr 64*1024]
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
source ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
# Parameters for 15.5Gpbs lane rate
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A
ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868
ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4
ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF
ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF
source $ad_hdl_dir/projects/ad9081_fmca_ebz/zcu102/system_bd.tcl

16
projects/ad9082_fmca_ebz/zcu102/system_project.tcl
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@ -15,17 +15,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
# Parameter description:
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
# 64B66B - 64b66b link layer defined in JESD 204C
# 8B10B - 8b10b link layer defined in JESD 204B
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
# Encoding is:
# 0 - CPLL
# 1 - QPLL0
# 2 - QPLL1
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
@ -37,6 +31,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9082_fmca_ebz_zcu102 0 [list \
JESD_MODE 8B10B \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 4 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \