From ec8db3ee5b46ff092d065e65f91f3bd3c2c160f7 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 7 Jun 2018 13:15:55 +0200 Subject: [PATCH] util_dacfifo: Reduce logic on high fan-out dma_wren_s signal The DMAC implementation guarantees that the expression `dma_valid & dma_xfer_req` is always identical to just dma_valid. When generating the util_dacfifo dma_wren_s signal the optimizer doesn't know of this though and hence will route both signals into the LUT that drives the write enable for the BRAMs. Simplify the expression by removing dma_xfer_req from it. Considering this can be a fairly high fan-out net and is typically the bottleneck for the util_dacfifo timing this helps to improve the timing. Signed-off-by: Lars-Peter Clausen --- library/util_dacfifo/util_dacfifo.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index 62a0e5e36..fac209ccf 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -154,7 +154,7 @@ module util_dacfifo #( // write address generation - assign dma_wren_s = dma_valid & dma_xfer_req & dma_ready; + assign dma_wren_s = dma_valid & dma_ready; always @(posedge dma_clk) begin if(dma_rst == 1'b1) begin