From ecfa6bd19d994cda539a3856f3aab0b50674269a Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 12 Mar 2019 14:41:11 +0000 Subject: [PATCH] axi_logic_analyzer: Add holdoff support --- .../axi_logic_analyzer/axi_logic_analyzer.v | 35 ++++++++++++++++--- .../axi_logic_analyzer_reg.v | 12 ++++++- 2 files changed, 41 insertions(+), 6 deletions(-) diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v index 1575743b8..5340e96a5 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer.v @@ -113,6 +113,7 @@ module axi_logic_analyzer #( reg streaming_on; reg [15:0] adc_data_mn = 'd0; + reg [31:0] trigger_holdoff_counter = 32'd0; // internal signals @@ -149,6 +150,9 @@ module axi_logic_analyzer #( wire [31:0] trigger_delay; wire trigger_out_delayed; + wire [31:0] trigger_holdoff; + wire trigger_out_holdoff; + wire streaming; genvar i; @@ -158,12 +162,12 @@ module axi_logic_analyzer #( assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; - assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on; + assign trigger_out = trigger_delay == 32'h0 ? trigger_out_holdoff | streaming_on : trigger_out_delayed | streaming_on; assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0; always @(posedge clk_out) begin if (trigger_delay == 0) begin - if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin + if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin streaming_on <= 1'b1; end else if (streaming == 1'b0) begin streaming_on <= 1'b0; @@ -177,8 +181,9 @@ module axi_logic_analyzer #( end end + always @(posedge clk_out) begin - if (sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin + if (sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin up_triggered_set <= 1'b1; end else if (up_triggered_reset == 1'b1) begin up_triggered_set <= 1'b0; @@ -297,12 +302,12 @@ module axi_logic_analyzer #( delay_counter <= 32'h0; end else begin if (adc_valid == 1'b1) begin - triggered <= trigger_out_s | triggered; + triggered <= trigger_out_holdoff | triggered; if (delay_counter == 32'h0) begin delay_counter <= trigger_delay; triggered <= 1'b0; end else begin - if(triggered == 1'b1 || trigger_out_s == 1'b1) begin + if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin delay_counter <= delay_counter - 1; end end @@ -310,6 +315,25 @@ module axi_logic_analyzer #( end end + // hold off trigger + assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_s; + assign holdoff_cnt_en = |trigger_holdoff; + + always @(posedge clk) begin + if (reset == 1'b1) begin + trigger_holdoff_counter <= 0; + end else begin + if (trigger_holdoff_counter != 0) begin + trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1; + end else if (trigger_out_holdoff == 1'b1) begin + trigger_holdoff_counter <= trigger_holdoff; + end else begin + trigger_holdoff_counter <= trigger_holdoff_counter; + end + end + end + + axi_logic_analyzer_trigger i_trigger ( .clk (clk_out), .reset (reset), @@ -344,6 +368,7 @@ module axi_logic_analyzer #( .high_level_enable (high_level_enable), .fifo_depth (fifo_depth), .trigger_delay (trigger_delay), + .trigger_holdoff (trigger_holdoff), .trigger_logic (trigger_logic), .clock_select (clock_select), .overwrite_enable (overwrite_enable), diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v index 04efd5ff5..bd5fe509b 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_reg.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer_reg.v @@ -58,6 +58,8 @@ module axi_logic_analyzer_reg ( input [15:0] input_data, output [15:0] od_pp_n, + output [31:0] trigger_holdoff, + input triggered, output streaming, @@ -95,6 +97,7 @@ module axi_logic_analyzer_reg ( reg [15:0] up_overwrite_enable = 0; reg [15:0] up_overwrite_data = 0; reg [15:0] up_od_pp_n = 0; + reg [31:0] up_trigger_holdoff = 32'h0; reg up_triggered = 0; reg up_streaming = 0; @@ -121,6 +124,7 @@ module axi_logic_analyzer_reg ( up_od_pp_n <= 16'h0; up_triggered <= 1'd0; up_streaming <= 1'd0; + up_trigger_holdoff <= 32'h0; end else begin up_wack <= up_wreq; if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin @@ -179,6 +183,9 @@ module axi_logic_analyzer_reg ( if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin up_streaming <= up_wdata[0]; end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin + up_trigger_holdoff <= up_wdata[31:0]; + end end end @@ -212,6 +219,7 @@ module axi_logic_analyzer_reg ( 5'h11: up_rdata <= up_trigger_delay; 5'h12: up_rdata <= {31'h0,up_triggered}; 5'h13: up_rdata <= {31'h0,up_streaming}; + 5'h14: up_rdata <= up_trigger_holdoff; default: up_rdata <= 0; endcase end else begin @@ -222,7 +230,7 @@ module axi_logic_analyzer_reg ( ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset)); - up_xfer_cntrl #(.DATA_WIDTH(291)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(323)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_streaming, // 1 @@ -233,6 +241,7 @@ module axi_logic_analyzer_reg ( up_trigger_logic, // 7 up_fifo_depth, // 32 up_trigger_delay, // 32 + up_trigger_holdoff, // 32 up_high_level_enable, // 18 up_low_level_enable, // 18 up_fall_edge_enable, // 18 @@ -253,6 +262,7 @@ module axi_logic_analyzer_reg ( trigger_logic, // 7 fifo_depth, // 32 trigger_delay, // 32 + trigger_holdoff, // 32 high_level_enable, // 18 low_level_enable, // 18 fall_edge_enable, // 18