axi_logic_analyzer: Add holdoff support
parent
ede19a3b3d
commit
ecfa6bd19d
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@ -113,6 +113,7 @@ module axi_logic_analyzer #(
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reg streaming_on;
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reg streaming_on;
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reg [15:0] adc_data_mn = 'd0;
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reg [15:0] adc_data_mn = 'd0;
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reg [31:0] trigger_holdoff_counter = 32'd0;
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// internal signals
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// internal signals
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@ -149,6 +150,9 @@ module axi_logic_analyzer #(
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wire [31:0] trigger_delay;
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wire [31:0] trigger_delay;
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wire trigger_out_delayed;
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wire trigger_out_delayed;
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wire [31:0] trigger_holdoff;
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wire trigger_out_holdoff;
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wire streaming;
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wire streaming;
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genvar i;
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genvar i;
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@ -158,12 +162,12 @@ module axi_logic_analyzer #(
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assign up_clk = s_axi_aclk;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign up_rstn = s_axi_aresetn;
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assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
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assign trigger_out = trigger_delay == 32'h0 ? trigger_out_holdoff | streaming_on : trigger_out_delayed | streaming_on;
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assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
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assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
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always @(posedge clk_out) begin
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always @(posedge clk_out) begin
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if (trigger_delay == 0) begin
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if (trigger_delay == 0) begin
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if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
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if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
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streaming_on <= 1'b1;
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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streaming_on <= 1'b0;
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@ -177,8 +181,9 @@ module axi_logic_analyzer #(
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end
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end
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end
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end
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always @(posedge clk_out) begin
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
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if (sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
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up_triggered_set <= 1'b1;
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up_triggered_set <= 1'b1;
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end else if (up_triggered_reset == 1'b1) begin
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end else if (up_triggered_reset == 1'b1) begin
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up_triggered_set <= 1'b0;
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up_triggered_set <= 1'b0;
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@ -297,12 +302,12 @@ module axi_logic_analyzer #(
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delay_counter <= 32'h0;
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delay_counter <= 32'h0;
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end else begin
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end else begin
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if (adc_valid == 1'b1) begin
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if (adc_valid == 1'b1) begin
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triggered <= trigger_out_s | triggered;
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triggered <= trigger_out_holdoff | triggered;
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if (delay_counter == 32'h0) begin
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if (delay_counter == 32'h0) begin
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delay_counter <= trigger_delay;
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delay_counter <= trigger_delay;
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triggered <= 1'b0;
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triggered <= 1'b0;
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end else begin
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end else begin
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if(triggered == 1'b1 || trigger_out_s == 1'b1) begin
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if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin
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delay_counter <= delay_counter - 1;
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delay_counter <= delay_counter - 1;
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end
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end
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end
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end
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@ -310,6 +315,25 @@ module axi_logic_analyzer #(
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end
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end
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end
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end
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// hold off trigger
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assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_s;
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assign holdoff_cnt_en = |trigger_holdoff;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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trigger_holdoff_counter <= 0;
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end else begin
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if (trigger_holdoff_counter != 0) begin
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trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1;
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end else if (trigger_out_holdoff == 1'b1) begin
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trigger_holdoff_counter <= trigger_holdoff;
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end else begin
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trigger_holdoff_counter <= trigger_holdoff_counter;
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end
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end
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end
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axi_logic_analyzer_trigger i_trigger (
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axi_logic_analyzer_trigger i_trigger (
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.clk (clk_out),
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.clk (clk_out),
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.reset (reset),
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.reset (reset),
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@ -344,6 +368,7 @@ module axi_logic_analyzer #(
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.high_level_enable (high_level_enable),
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.high_level_enable (high_level_enable),
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.fifo_depth (fifo_depth),
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.fifo_depth (fifo_depth),
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.trigger_delay (trigger_delay),
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.trigger_delay (trigger_delay),
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.trigger_holdoff (trigger_holdoff),
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.trigger_logic (trigger_logic),
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.trigger_logic (trigger_logic),
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.clock_select (clock_select),
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.clock_select (clock_select),
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.overwrite_enable (overwrite_enable),
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.overwrite_enable (overwrite_enable),
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@ -58,6 +58,8 @@ module axi_logic_analyzer_reg (
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input [15:0] input_data,
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input [15:0] input_data,
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output [15:0] od_pp_n,
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output [15:0] od_pp_n,
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output [31:0] trigger_holdoff,
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input triggered,
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input triggered,
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output streaming,
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output streaming,
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@ -95,6 +97,7 @@ module axi_logic_analyzer_reg (
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reg [15:0] up_overwrite_enable = 0;
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reg [15:0] up_overwrite_enable = 0;
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reg [15:0] up_overwrite_data = 0;
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reg [15:0] up_overwrite_data = 0;
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reg [15:0] up_od_pp_n = 0;
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reg [15:0] up_od_pp_n = 0;
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reg [31:0] up_trigger_holdoff = 32'h0;
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reg up_triggered = 0;
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reg up_triggered = 0;
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reg up_streaming = 0;
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reg up_streaming = 0;
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@ -121,6 +124,7 @@ module axi_logic_analyzer_reg (
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up_od_pp_n <= 16'h0;
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up_od_pp_n <= 16'h0;
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up_triggered <= 1'd0;
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up_triggered <= 1'd0;
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up_streaming <= 1'd0;
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up_streaming <= 1'd0;
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up_trigger_holdoff <= 32'h0;
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end else begin
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end else begin
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up_wack <= up_wreq;
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
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@ -179,6 +183,9 @@ module axi_logic_analyzer_reg (
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
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up_streaming <= up_wdata[0];
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up_streaming <= up_wdata[0];
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end
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
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up_trigger_holdoff <= up_wdata[31:0];
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end
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end
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end
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end
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end
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@ -212,6 +219,7 @@ module axi_logic_analyzer_reg (
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5'h11: up_rdata <= up_trigger_delay;
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5'h11: up_rdata <= up_trigger_delay;
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5'h12: up_rdata <= {31'h0,up_triggered};
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5'h12: up_rdata <= {31'h0,up_triggered};
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5'h13: up_rdata <= {31'h0,up_streaming};
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5'h13: up_rdata <= {31'h0,up_streaming};
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5'h14: up_rdata <= up_trigger_holdoff;
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default: up_rdata <= 0;
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default: up_rdata <= 0;
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endcase
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endcase
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end else begin
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end else begin
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@ -222,7 +230,7 @@ module axi_logic_analyzer_reg (
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ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
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ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
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up_xfer_cntrl #(.DATA_WIDTH(291)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(323)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_streaming, // 1
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.up_data_cntrl ({ up_streaming, // 1
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@ -233,6 +241,7 @@ module axi_logic_analyzer_reg (
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up_trigger_logic, // 7
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up_trigger_logic, // 7
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up_fifo_depth, // 32
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up_fifo_depth, // 32
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up_trigger_delay, // 32
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up_trigger_delay, // 32
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up_trigger_holdoff, // 32
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up_high_level_enable, // 18
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up_high_level_enable, // 18
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up_low_level_enable, // 18
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up_low_level_enable, // 18
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up_fall_edge_enable, // 18
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up_fall_edge_enable, // 18
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@ -253,6 +262,7 @@ module axi_logic_analyzer_reg (
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trigger_logic, // 7
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trigger_logic, // 7
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fifo_depth, // 32
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fifo_depth, // 32
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trigger_delay, // 32
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trigger_delay, // 32
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trigger_holdoff, // 32
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high_level_enable, // 18
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high_level_enable, // 18
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low_level_enable, // 18
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low_level_enable, // 18
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fall_edge_enable, // 18
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fall_edge_enable, // 18
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