arradio: Revert tcl related changes, to fix DDR Bandwidth related issue
Adrian Costina
parent
128be6fb69
commit
ed12efc620
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@ -5,17 +5,82 @@
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####################################################################################
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####################################################################################
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ifeq ($(MMU),)
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MMU := 1
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endif
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export ALT_NIOS_MMU_ENABLED := $(MMU)
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.sdc
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M_DEPS += system_bd.qsys
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M_DEPS += ../common/arradio_bd.qsys
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../common/c5soc/c5soc_system_bd.qsys
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M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
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M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
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M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
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M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
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M_DEPS += ../../../library/axi_dmac/2d_transfer.v
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M_DEPS += ../../../library/axi_dmac/address_generator.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
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M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
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M_DEPS += ../../../library/axi_dmac/data_mover.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
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M_DEPS += ../../../library/axi_dmac/inc_id.h
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M_DEPS += ../../../library/axi_dmac/request_arb.v
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M_DEPS += ../../../library/axi_dmac/request_generator.v
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M_DEPS += ../../../library/axi_dmac/resp.h
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M_DEPS += ../../../library/axi_dmac/response_generator.v
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M_DEPS += ../../../library/axi_dmac/response_handler.v
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M_DEPS += ../../../library/axi_dmac/splitter.v
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M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
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M_DEPS += ../../../library/common/ad_addsub.v
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M_DEPS += ../../../library/common/ad_datafmt.v
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M_DEPS += ../../../library/common/ad_dcfilter.v
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M_DEPS += ../../../library/common/ad_dds.v
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M_DEPS += ../../../library/common/ad_dds_1.v
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M_DEPS += ../../../library/common/ad_dds_sine.v
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M_DEPS += ../../../library/common/ad_iqcor.v
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M_DEPS += ../../../library/altera/common/ad_mul.v
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M_DEPS += ../../../library/common/ad_pnmon.v
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M_DEPS += ../../../library/common/ad_rst.v
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M_DEPS += ../../../library/common/ad_tdd_control.v
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M_DEPS += ../../../library/common/sync_bits.v
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M_DEPS += ../../../library/common/sync_gray.v
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M_DEPS += ../../../library/common/up_adc_channel.v
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M_DEPS += ../../../library/common/up_adc_common.v
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M_DEPS += ../../../library/common/up_axi.v
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M_DEPS += ../../../library/common/up_clock_mon.v
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M_DEPS += ../../../library/common/up_dac_channel.v
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M_DEPS += ../../../library/common/up_dac_common.v
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M_DEPS += ../../../library/common/up_delay_cntrl.v
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M_DEPS += ../../../library/common/up_tdd_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_status.v
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M_DEPS += ../../../library/util_axis_fifo/address_gray.v
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M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
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M_DEPS += ../../../library/util_axis_fifo/address_sync.v
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M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
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M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
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M_DEPS += ../../../library/util_cpack/util_cpack.v
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M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
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M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
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M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
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M_DEPS += ../../../library/util_upack/util_upack.v
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M_DEPS += ../../../library/util_upack/util_upack_dmx.v
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M_DEPS += ../../../library/util_upack/util_upack_dsf.v
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M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
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M_ALTERA := quartus_sh --64bit -t
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@ -34,7 +99,6 @@ M_FLIST += *.sta.*
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M_FLIST += *.qsf
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M_FLIST += *.qpf
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M_FLIST += *.qws
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M_FLIST += *.qsys
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M_FLIST += *.sof
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M_FLIST += *.cdf
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M_FLIST += *.sld
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@ -49,9 +113,6 @@ M_FLIST += reconfig_mif
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M_FLIST += *.sopcinfo
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M_FLIST += *.jdi
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M_FLIST += *.pin
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M_FLIST += *_summary.csv
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M_FLIST += *.dpf
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M_FLIST += system_qsys_script.tcl
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@ -68,7 +129,7 @@ clean-all:
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arradio_c5soc.sof: $(M_DEPS)
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-rm -rf $(M_FLIST)
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rm -rf $(M_FLIST)
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$(M_ALTERA) system_project.tcl >> arradio_c5soc_quartus.log 2>&1
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####################################################################################
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@ -0,0 +1,430 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags=""
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element arradio
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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}
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element arradio.axi_ad9361_s_axi
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{
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datum baseAddress
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{
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value = "131072";
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type = "String";
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}
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}
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element arradio.axi_dmac_adc_s_axi
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{
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datum baseAddress
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{
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value = "0";
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type = "String";
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}
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}
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element arradio.axi_dmac_dac_s_axi
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{
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datum baseAddress
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{
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value = "16384";
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type = "String";
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}
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}
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element arradio.gpio_s1
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{
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datum baseAddress
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{
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value = "36864";
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type = "String";
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}
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}
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element arradio.spi_ad9361_spi_control_port
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{
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datum baseAddress
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{
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value = "32768";
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type = "String";
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}
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}
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element c5soc
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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element sys_clk
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="FIFO" />
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<parameter name="device" value="5CSXFC6D6F31C8ES" />
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<parameter name="deviceFamily" value="Cyclone V" />
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<parameter name="deviceSpeedGrade" value="8_H6" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="2" />
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<parameter name="projectName" value="arradio_c5soc.qpf" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="axi_ad9361_device_clock"
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internal="arradio.axi_ad9361_device_clock" />
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<interface
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name="axi_ad9361_device_if"
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internal="arradio.axi_ad9361_device_if"
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type="conduit"
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dir="end" />
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<interface
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name="axi_ad9361_l_clk"
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internal="arradio.axi_ad9361_l_clk"
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type="clock"
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dir="start" />
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<interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
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<interface
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name="gpio_external_connection"
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internal="arradio.gpio_external_connection"
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type="conduit"
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dir="end" />
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<interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
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<interface
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name="spi_ad9361_external"
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internal="arradio.spi_ad9361_external"
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type="conduit"
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dir="end" />
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<interface
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name="sys_gpio_external_connection"
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internal="c5soc.sys_gpio_external_connection"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_h2f_reset"
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internal="c5soc.sys_hps_h2f_reset"
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type="reset"
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dir="start" />
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<interface
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name="sys_hps_hps_io"
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internal="c5soc.sys_hps_hps_io"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_i2c0"
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internal="c5soc.sys_hps_i2c0"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_i2c0_clk"
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internal="c5soc.sys_hps_i2c0_clk"
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type="clock"
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dir="start" />
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<interface
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name="sys_hps_i2c0_scl_in"
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internal="c5soc.sys_hps_i2c0_scl_in"
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type="clock"
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dir="end" />
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<interface
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name="sys_hps_memory"
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internal="c5soc.sys_hps_memory"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_spim0"
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internal="c5soc.sys_hps_spim0"
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type="conduit"
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dir="end" />
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<interface
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name="sys_hps_spim0_sclk_out"
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internal="c5soc.sys_hps_spim0_sclk_out"
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type="clock"
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dir="start" />
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<interface
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name="vga_clock_video_output_clocked_video"
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internal="c5soc.vga_clock_video_output_clocked_video"
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type="conduit"
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dir="end" />
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<interface
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name="vga_pixel_clock_bridge_out_clk"
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internal="c5soc.vga_pixel_clock_bridge_out_clk"
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type="clock"
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dir="start" />
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<module name="arradio" kind="arradio_bd" version="1.0" enabled="1">
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<parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
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<parameter
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name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
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value="AddressWidth = 32" />
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<parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram2_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
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<parameter
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name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
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value="AddressWidth = 32" />
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<parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="9" />
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<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
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<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="9" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_arradio</parameter>
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</module>
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<module name="c5soc" kind="c5soc_system_bd" version="1.0" enabled="1">
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<parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
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<parameter name="AUTO_GENERATION_ID" value="0" />
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<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
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<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
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<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
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<parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
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<parameter
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name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
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value="AddressWidth = 18" />
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<parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_DOMAIN" value="6" />
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<parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_CLOCK_RATE" value="0" />
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<parameter name="AUTO_SYS_HPS_I2C0_SCL_IN_RESET_DOMAIN" value="6" />
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<parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
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<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
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</module>
|
||||
<module name="sys_clk" kind="clock_source" version="16.0" enabled="1">
|
||||
<parameter name="clockFrequency" value="50000000" />
|
||||
<parameter name="clockFrequencyKnown" value="true" />
|
||||
<parameter name="inputClockFrequency" value="0" />
|
||||
<parameter name="resetSynchronousEdges" value="NONE" />
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="arradio.axi_dmac_adc_m_dest_axi"
|
||||
end="c5soc.sys_mem_interconnect_axi0_s0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="arradio.axi_dmac_dac_m_src_axi"
|
||||
end="c5soc.sys_mem_interconnect_axi1_s0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.axi_ad9361_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00020000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.axi_dmac_adc_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.axi_dmac_dac_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x4000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.gpio_s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x9000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="16.0"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.spi_ad9361_spi_control_port">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x8000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="clock" version="16.0" start="sys_clk.clk" end="c5soc.sys_clk" />
|
||||
<connection kind="clock" version="16.0" start="sys_clk.clk" end="arradio.sys_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="c5soc.mem_clk"
|
||||
end="arradio.mem_clk" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="16.0"
|
||||
start="c5soc.sys_intr"
|
||||
end="arradio.axi_dmac_adc_intr">
|
||||
<parameter name="irqNumber" value="2" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="16.0"
|
||||
start="c5soc.sys_intr"
|
||||
end="arradio.axi_dmac_dac_intr">
|
||||
<parameter name="irqNumber" value="1" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="16.0"
|
||||
start="c5soc.sys_intr"
|
||||
end="arradio.spi_ad9361_irq">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="c5soc.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="arradio.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="c5soc.mem_rst"
|
||||
end="arradio.mem_rst" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_0|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_2|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
</system>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,77 +1,58 @@
|
|||
|
||||
create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
|
||||
create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
|
||||
create_clock -period "20.000 ns" -name clk_50m [get_ports {sys_clk}]
|
||||
create_clock -period "4.000 ns" -name clk_250m [get_ports {rx_clk_in}]
|
||||
create_clock -period "12.500 ns" -name clk_80m [get_pins {i_system_bd|c5soc|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}]
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
set clk_125m [get_clocks {i_system_bd|arradio|axi_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
|
||||
|
||||
set clk_vga [get_clocks {i_system_bd|c5soc|vga_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
|
||||
|
||||
set_false_path -from clk_50m -to clk_80m
|
||||
set_false_path -from clk_50m -to $clk_125m
|
||||
set_false_path -from clk_80m -to clk_50m
|
||||
set_false_path -from clk_80m -to $clk_125m
|
||||
set_false_path -from $clk_125m -to clk_50m
|
||||
set_false_path -from $clk_125m -to clk_80m
|
||||
set_false_path -from clk_50m -to $clk_vga
|
||||
set_false_path -from $clk_vga -to clk_50m
|
||||
|
||||
create_clock -period 4.0 -name v_rx_clk
|
||||
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
|
||||
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
|
||||
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
|
||||
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
|
||||
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[1]}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[2]}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[3]}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[4]}]
|
||||
set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[5]}]
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_frame_in}] -clock_fall -add_delay
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[0]}] -clock_fall -add_delay
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[1]}] -clock_fall -add_delay
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[2]}] -clock_fall -add_delay
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clock_fall -add_delay
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay
|
||||
set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay
|
||||
|
||||
create_generated_clock -name v_tx_clk_reg \
|
||||
-source [get_pins -hierarchical *counter\[0\]*divclk*] \
|
||||
[get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*]
|
||||
|
||||
create_generated_clock -name v_tx_clk \
|
||||
-source [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*] \
|
||||
[get_ports {tx_clk_out}]
|
||||
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
|
||||
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
|
||||
set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
|
||||
set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
|
||||
set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
|
||||
create_generated_clock -source [get_ports {rx_clk_in}] -name v_tx_clk [get_ports {tx_clk_out}] -phase 90
|
||||
|
||||
set_false_path -from clk_250m -to v_tx_clk
|
||||
set_false_path -from v_tx_clk -to clk_250m
|
||||
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_frame_out}]
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[0]}]
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[1]}]
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[2]}]
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[3]}]
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[4]}]
|
||||
set_output_delay -clock {v_tx_clk} -max 1.2 [get_ports {tx_data_out[5]}]
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay
|
||||
set_output_delay -clock {v_tx_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay
|
||||
|
||||
|
|
|
|||
|
|
@ -5,45 +5,16 @@ source ../../scripts/adi_env.tcl
|
|||
project_new arradio_c5soc -overwrite
|
||||
|
||||
source "../../common/c5soc/c5soc_system_assign.tcl"
|
||||
|
||||
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
|
||||
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
|
||||
set_global_assignment -name QSYS_FILE system_bd.qsys
|
||||
|
||||
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
|
||||
set_global_assignment -name VERILOG_FILE system_top.v
|
||||
|
||||
set_global_assignment -name SDC_FILE system_constr.sdc
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY system_top
|
||||
|
||||
set_location_assignment PIN_H15 -to rx_clk_in
|
||||
set_location_assignment PIN_G15 -to "rx_clk_in(n)"
|
||||
set_location_assignment PIN_F13 -to rx_frame_in
|
||||
set_location_assignment PIN_E13 -to "rx_frame_in(n)"
|
||||
set_location_assignment PIN_D11 -to rx_data_in[0]
|
||||
set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
|
||||
set_location_assignment PIN_E12 -to rx_data_in[1]
|
||||
set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
|
||||
set_location_assignment PIN_E9 -to rx_data_in[2]
|
||||
set_location_assignment PIN_D9 -to "rx_data_in[2](n)"
|
||||
set_location_assignment PIN_B6 -to rx_data_in[3]
|
||||
set_location_assignment PIN_B5 -to "rx_data_in[3](n)"
|
||||
set_location_assignment PIN_F11 -to rx_data_in[4]
|
||||
set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
|
||||
set_location_assignment PIN_C13 -to rx_data_in[5]
|
||||
set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
|
||||
set_location_assignment PIN_A11 -to tx_clk_out
|
||||
set_location_assignment PIN_A10 -to "tx_clk_out(n)"
|
||||
set_location_assignment PIN_E3 -to tx_frame_out
|
||||
set_location_assignment PIN_E2 -to "tx_frame_out(n)"
|
||||
set_location_assignment PIN_E1 -to tx_data_out[0]
|
||||
set_location_assignment PIN_D1 -to "tx_data_out[0](n)"
|
||||
set_location_assignment PIN_D2 -to tx_data_out[1]
|
||||
set_location_assignment PIN_C2 -to "tx_data_out[1](n)"
|
||||
set_location_assignment PIN_C3 -to tx_data_out[2]
|
||||
set_location_assignment PIN_B3 -to "tx_data_out[2](n)"
|
||||
set_location_assignment PIN_B2 -to tx_data_out[3]
|
||||
set_location_assignment PIN_B1 -to "tx_data_out[3](n)"
|
||||
set_location_assignment PIN_A4 -to tx_data_out[4]
|
||||
set_location_assignment PIN_A3 -to "tx_data_out[4](n)"
|
||||
set_location_assignment PIN_E4 -to tx_data_out[5]
|
||||
set_location_assignment PIN_D4 -to "tx_data_out[5](n)"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
|
||||
|
|
@ -70,40 +41,73 @@ set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
|
|||
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
|
||||
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
|
||||
|
||||
set_location_assignment PIN_B11 -to enable
|
||||
set_location_assignment PIN_C12 -to txnrx
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to enable
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to txnrx
|
||||
set_location_assignment PIN_H15 -to rx_clk_in
|
||||
set_location_assignment PIN_G15 -to "rx_clk_in(n)"
|
||||
set_location_assignment PIN_F13 -to rx_frame_in
|
||||
set_location_assignment PIN_E13 -to "rx_frame_in(n)"
|
||||
set_location_assignment PIN_D11 -to rx_data_in[0]
|
||||
set_location_assignment PIN_D10 -to "rx_data_in[0](n)"
|
||||
set_location_assignment PIN_E12 -to rx_data_in[1]
|
||||
set_location_assignment PIN_D12 -to "rx_data_in[1](n)"
|
||||
set_location_assignment PIN_E9 -to rx_data_in[2]
|
||||
set_location_assignment PIN_D9 -to "rx_data_in[2](n)"
|
||||
set_location_assignment PIN_B6 -to rx_data_in[3]
|
||||
set_location_assignment PIN_B5 -to "rx_data_in[3](n)"
|
||||
set_location_assignment PIN_F11 -to rx_data_in[4]
|
||||
set_location_assignment PIN_E11 -to "rx_data_in[4](n)"
|
||||
set_location_assignment PIN_C13 -to rx_data_in[5]
|
||||
set_location_assignment PIN_B12 -to "rx_data_in[5](n)"
|
||||
|
||||
set_location_assignment PIN_A11 -to tx_clk_out
|
||||
set_location_assignment PIN_A10 -to "tx_clk_out(n)"
|
||||
set_location_assignment PIN_E3 -to tx_frame_out
|
||||
set_location_assignment PIN_E2 -to "tx_frame_out(n)"
|
||||
set_location_assignment PIN_E1 -to tx_data_out[0]
|
||||
set_location_assignment PIN_D1 -to "tx_data_out[0](n)"
|
||||
set_location_assignment PIN_D2 -to tx_data_out[1]
|
||||
set_location_assignment PIN_C2 -to "tx_data_out[1](n)"
|
||||
set_location_assignment PIN_C3 -to tx_data_out[2]
|
||||
set_location_assignment PIN_B3 -to "tx_data_out[2](n)"
|
||||
set_location_assignment PIN_B2 -to tx_data_out[3]
|
||||
set_location_assignment PIN_B1 -to "tx_data_out[3](n)"
|
||||
set_location_assignment PIN_A4 -to tx_data_out[4]
|
||||
set_location_assignment PIN_A3 -to "tx_data_out[4](n)"
|
||||
set_location_assignment PIN_E4 -to tx_data_out[5]
|
||||
set_location_assignment PIN_D4 -to "tx_data_out[5](n)"
|
||||
|
||||
set_location_assignment PIN_C4 -to ad9361_resetb
|
||||
set_location_assignment PIN_C5 -to ad9361_en_agc
|
||||
set_location_assignment PIN_D5 -to ad9361_sync
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_resetb
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_en_agc
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_sync
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_enable
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_txnrx
|
||||
|
||||
set_location_assignment PIN_A8 -to spi_csn
|
||||
set_location_assignment PIN_H12 -to spi_clk
|
||||
set_location_assignment PIN_H13 -to spi_mosi
|
||||
set_location_assignment PIN_G11 -to spi_miso
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
|
||||
|
||||
set_location_assignment PIN_F15 -to scl
|
||||
set_location_assignment PIN_G13 -to sda
|
||||
set_location_assignment PIN_C7 -to ga0
|
||||
set_location_assignment PIN_H14 -to ga1
|
||||
set_location_assignment PIN_C4 -to ad9361_resetb
|
||||
set_location_assignment PIN_C5 -to ad9361_en_agc
|
||||
set_location_assignment PIN_D5 -to ad9361_sync
|
||||
set_location_assignment PIN_B11 -to ad9361_enable
|
||||
set_location_assignment PIN_C12 -to ad9361_txnrx
|
||||
set_location_assignment PIN_A8 -to spi_csn
|
||||
set_location_assignment PIN_H12 -to spi_clk
|
||||
set_location_assignment PIN_H13 -to spi_mosi
|
||||
set_location_assignment PIN_G11 -to spi_miso
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to scl
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to sda
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ga0
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to ga1
|
||||
|
||||
set_location_assignment PIN_F15 -to scl
|
||||
set_location_assignment PIN_G13 -to sda
|
||||
set_location_assignment PIN_C7 -to ga0
|
||||
set_location_assignment PIN_H14 -to ga1
|
||||
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to scl
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sda
|
||||
|
||||
set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -to * -entity axi_ad9361
|
||||
|
||||
execute_flow -compile
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +0,0 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/c5soc/c5soc_system_qsys.tcl
|
||||
source ../common/arradio_qsys.tcl
|
||||
|
||||
|
||||
|
|
@ -41,124 +41,279 @@ module system_top (
|
|||
|
||||
// clock and resets
|
||||
|
||||
input sys_clk,
|
||||
sys_clk,
|
||||
|
||||
// hps-ddr
|
||||
// hps
|
||||
|
||||
output [ 14:0] ddr3_a,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_ck_p,
|
||||
output ddr3_ck_n,
|
||||
output ddr3_cke,
|
||||
output ddr3_cs_n,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_cas_n,
|
||||
output ddr3_we_n,
|
||||
inout [ 31:0] ddr3_dq,
|
||||
inout [ 3:0] ddr3_dqs_p,
|
||||
inout [ 3:0] ddr3_dqs_n,
|
||||
output [ 3:0] ddr3_dm,
|
||||
output ddr3_odt,
|
||||
input ddr3_rzq,
|
||||
|
||||
// hps-ethernet
|
||||
|
||||
output eth1_tx_clk,
|
||||
output eth1_tx_ctl,
|
||||
output [ 3:0] eth1_tx_d,
|
||||
input eth1_rx_clk,
|
||||
input eth1_rx_ctl,
|
||||
input [ 3:0] eth1_rx_d,
|
||||
output eth1_mdc,
|
||||
inout eth1_mdio,
|
||||
|
||||
// hps-qspi
|
||||
|
||||
output qspi_ss0,
|
||||
output qspi_clk,
|
||||
inout [ 3:0] qspi_io,
|
||||
|
||||
// hps-sdio
|
||||
|
||||
output sdio_clk,
|
||||
inout sdio_cmd,
|
||||
inout [ 3:0] sdio_d,
|
||||
|
||||
// hps-usb
|
||||
|
||||
input usb1_clk,
|
||||
output usb1_stp,
|
||||
input usb1_dir,
|
||||
input usb1_nxt,
|
||||
inout [ 7:0] usb1_d,
|
||||
|
||||
// hps-spim1-lcd
|
||||
|
||||
output spim1_ss0,
|
||||
output spim1_clk,
|
||||
output spim1_mosi,
|
||||
input spim1_miso,
|
||||
|
||||
// iic interface
|
||||
|
||||
inout scl,
|
||||
inout sda,
|
||||
output ga0,
|
||||
output ga1,
|
||||
|
||||
// hps-uart
|
||||
|
||||
input uart0_rx,
|
||||
output uart0_tx,
|
||||
ddr3_a,
|
||||
ddr3_ba,
|
||||
ddr3_ck_p,
|
||||
ddr3_ck_n,
|
||||
ddr3_cke,
|
||||
ddr3_cs_n,
|
||||
ddr3_ras_n,
|
||||
ddr3_cas_n,
|
||||
ddr3_we_n,
|
||||
ddr3_reset_n,
|
||||
ddr3_dq,
|
||||
ddr3_dqs_p,
|
||||
ddr3_dqs_n,
|
||||
ddr3_odt,
|
||||
ddr3_dm,
|
||||
ddr3_oct_rzqin,
|
||||
eth1_tx_clk,
|
||||
eth1_tx_ctl,
|
||||
eth1_txd0,
|
||||
eth1_txd1,
|
||||
eth1_txd2,
|
||||
eth1_txd3,
|
||||
eth1_rx_clk,
|
||||
eth1_rx_ctl,
|
||||
eth1_rxd0,
|
||||
eth1_rxd1,
|
||||
eth1_rxd2,
|
||||
eth1_rxd3,
|
||||
eth1_mdc,
|
||||
eth1_mdio,
|
||||
qspi_ss0,
|
||||
qspi_clk,
|
||||
qspi_io0,
|
||||
qspi_io1,
|
||||
qspi_io2,
|
||||
qspi_io3,
|
||||
sdio_clk,
|
||||
sdio_cmd,
|
||||
sdio_d0,
|
||||
sdio_d1,
|
||||
sdio_d2,
|
||||
sdio_d3,
|
||||
usb1_clk,
|
||||
usb1_stp,
|
||||
usb1_dir,
|
||||
usb1_nxt,
|
||||
usb1_d0,
|
||||
usb1_d1,
|
||||
usb1_d2,
|
||||
usb1_d3,
|
||||
usb1_d4,
|
||||
usb1_d5,
|
||||
usb1_d6,
|
||||
usb1_d7,
|
||||
spim1_ss0,
|
||||
spim1_clk,
|
||||
spim1_mosi,
|
||||
spim1_miso,
|
||||
uart0_rx,
|
||||
uart0_tx,
|
||||
|
||||
// board gpio
|
||||
|
||||
output [ 3:0] gpio_bd_o,
|
||||
input [ 7:0] gpio_bd_i,
|
||||
led,
|
||||
push_buttons,
|
||||
dip_switches,
|
||||
|
||||
// display
|
||||
|
||||
output vga_clk,
|
||||
output vga_blank_n,
|
||||
output vga_sync_n,
|
||||
output vga_hsync,
|
||||
output vga_vsync,
|
||||
output [ 7:0] vga_red,
|
||||
output [ 7:0] vga_grn,
|
||||
output [ 7:0] vga_blu,
|
||||
vga_clk,
|
||||
vga_blank_n,
|
||||
vga_sync_n,
|
||||
vga_hs,
|
||||
vga_vs,
|
||||
vga_r,
|
||||
vga_g,
|
||||
vga_b,
|
||||
|
||||
// ad9361
|
||||
// data interface
|
||||
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [ 5:0] rx_data_in,
|
||||
output tx_clk_out,
|
||||
output tx_frame_out,
|
||||
output [ 5:0] tx_data_out,
|
||||
output enable,
|
||||
output txnrx,
|
||||
rx_clk_in,
|
||||
rx_frame_in,
|
||||
rx_data_in,
|
||||
tx_clk_out,
|
||||
tx_frame_out,
|
||||
tx_data_out,
|
||||
|
||||
// gpio interface
|
||||
|
||||
output ad9361_resetb,
|
||||
output ad9361_en_agc,
|
||||
output ad9361_sync,
|
||||
ad9361_resetb,
|
||||
ad9361_en_agc,
|
||||
ad9361_sync,
|
||||
ad9361_enable,
|
||||
ad9361_txnrx,
|
||||
|
||||
// iic interface
|
||||
|
||||
scl,
|
||||
sda,
|
||||
ga0,
|
||||
ga1,
|
||||
|
||||
// spi
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso);
|
||||
|
||||
// clock and resets
|
||||
|
||||
input sys_clk;
|
||||
|
||||
// hps
|
||||
|
||||
output [ 14:0] ddr3_a;
|
||||
output [ 2:0] ddr3_ba;
|
||||
output ddr3_ck_p;
|
||||
output ddr3_ck_n;
|
||||
output ddr3_cke;
|
||||
output ddr3_cs_n;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_cas_n;
|
||||
output ddr3_we_n;
|
||||
output ddr3_reset_n;
|
||||
inout [ 31:0] ddr3_dq;
|
||||
inout [ 3:0] ddr3_dqs_p;
|
||||
inout [ 3:0] ddr3_dqs_n;
|
||||
output ddr3_odt;
|
||||
output [ 3:0] ddr3_dm;
|
||||
input ddr3_oct_rzqin;
|
||||
output eth1_tx_clk;
|
||||
output eth1_tx_ctl;
|
||||
output eth1_txd0;
|
||||
output eth1_txd1;
|
||||
output eth1_txd2;
|
||||
output eth1_txd3;
|
||||
input eth1_rx_clk;
|
||||
input eth1_rx_ctl;
|
||||
input eth1_rxd0;
|
||||
input eth1_rxd1;
|
||||
input eth1_rxd2;
|
||||
input eth1_rxd3;
|
||||
output eth1_mdc;
|
||||
inout eth1_mdio;
|
||||
output qspi_ss0;
|
||||
output qspi_clk;
|
||||
inout qspi_io0;
|
||||
inout qspi_io1;
|
||||
inout qspi_io2;
|
||||
inout qspi_io3;
|
||||
output sdio_clk;
|
||||
inout sdio_cmd;
|
||||
inout sdio_d0;
|
||||
inout sdio_d1;
|
||||
inout sdio_d2;
|
||||
inout sdio_d3;
|
||||
input usb1_clk;
|
||||
output usb1_stp;
|
||||
input usb1_dir;
|
||||
input usb1_nxt;
|
||||
inout usb1_d0;
|
||||
inout usb1_d1;
|
||||
inout usb1_d2;
|
||||
inout usb1_d3;
|
||||
inout usb1_d4;
|
||||
inout usb1_d5;
|
||||
inout usb1_d6;
|
||||
inout usb1_d7;
|
||||
output spim1_ss0;
|
||||
output spim1_clk;
|
||||
output spim1_mosi;
|
||||
input spim1_miso;
|
||||
input uart0_rx;
|
||||
output uart0_tx;
|
||||
|
||||
// board gpio
|
||||
|
||||
output [ 3:0] led;
|
||||
input [ 3:0] push_buttons;
|
||||
input [ 3:0] dip_switches;
|
||||
|
||||
// display
|
||||
|
||||
output vga_clk;
|
||||
output vga_blank_n;
|
||||
output vga_sync_n;
|
||||
output vga_hs;
|
||||
output vga_vs;
|
||||
output [ 7:0] vga_r;
|
||||
output [ 7:0] vga_g;
|
||||
output [ 7:0] vga_b;
|
||||
|
||||
// data interface
|
||||
|
||||
input rx_clk_in;
|
||||
input rx_frame_in;
|
||||
input [ 5:0] rx_data_in;
|
||||
output tx_clk_out;
|
||||
output tx_frame_out;
|
||||
output [ 5:0] tx_data_out;
|
||||
|
||||
// gpio interface
|
||||
|
||||
output ad9361_resetb;
|
||||
output ad9361_en_agc;
|
||||
output ad9361_sync;
|
||||
output ad9361_enable;
|
||||
output ad9361_txnrx;
|
||||
|
||||
// iic interface
|
||||
|
||||
inout scl;
|
||||
inout sda;
|
||||
output ga0;
|
||||
output ga1;
|
||||
|
||||
|
||||
// spi interface
|
||||
|
||||
output spi_csn,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
output spi_csn;
|
||||
output spi_clk;
|
||||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
// internal clocks and resets
|
||||
|
||||
wire [ 31:0] gpio_open;
|
||||
wire sys_resetn;
|
||||
wire clk;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire sys_resetn;
|
||||
wire [ 31:0] sys_gpio_bd_i;
|
||||
wire [ 31:0] sys_gpio_bd_o;
|
||||
wire [ 31:0] sys_gpio_i;
|
||||
wire [ 31:0] sys_gpio_o;
|
||||
wire adc_enable_i0;
|
||||
wire adc_enable_q0;
|
||||
wire adc_enable_i1;
|
||||
wire adc_enable_q1;
|
||||
wire adc_valid_i0;
|
||||
wire adc_valid_q0;
|
||||
wire adc_valid_i1;
|
||||
wire adc_valid_q1;
|
||||
wire adc_dwr;
|
||||
wire adc_dsync;
|
||||
wire [ 15:0] adc_chan_i0;
|
||||
wire [ 15:0] adc_chan_q0;
|
||||
wire [ 15:0] adc_chan_i1;
|
||||
wire [ 15:0] adc_chan_q1;
|
||||
wire [ 63:0] adc_ddata;
|
||||
wire adc_dovf;
|
||||
wire dac_enable_i0;
|
||||
wire dac_enable_q0;
|
||||
wire dac_enable_i1;
|
||||
wire dac_enable_q1;
|
||||
wire dac_valid_i0;
|
||||
wire dac_valid_q0;
|
||||
wire dac_valid_i1;
|
||||
wire dac_valid_q1;
|
||||
wire [ 15:0] dac_data_i0;
|
||||
wire [ 15:0] dac_data_q0;
|
||||
wire [ 15:0] dac_data_i1;
|
||||
wire [ 15:0] dac_data_q1;
|
||||
wire [ 63:0] dac_ddata;
|
||||
wire dac_dunf;
|
||||
wire dac_rd_en;
|
||||
wire dac_fifo_valid;
|
||||
wire vga_pixel_clock;
|
||||
wire vid_v_sync;
|
||||
wire vid_h_sync;
|
||||
wire [7:0] vid_r,vid_g,vid_b;
|
||||
|
||||
wire i2c0_out_data;
|
||||
wire i2c0_sda;
|
||||
|
|
@ -167,96 +322,48 @@ module system_top (
|
|||
|
||||
// defaults
|
||||
|
||||
assign vga_clk = vga_pixel_clock;
|
||||
assign vga_blank_n = 1'b1;
|
||||
assign vga_sync_n = 1'b0;
|
||||
|
||||
assign gpio_bd_o = sys_gpio_bd_o[3:0];
|
||||
|
||||
assign sys_gpio_bd_i[31:8] = sys_gpio_bd_o[31:8];
|
||||
assign sys_gpio_bd_i[ 7:0] = gpio_bd_i;
|
||||
|
||||
assign ad9361_resetb = sys_gpio_o[4];
|
||||
assign ad9361_en_agc = sys_gpio_o[3];
|
||||
assign ad9361_sync = sys_gpio_o[2];
|
||||
assign vga_hs = vid_h_sync;
|
||||
assign vga_vs = vid_v_sync;
|
||||
assign {vga_b,vga_g,vga_r} = {vid_b,vid_g,vid_r};
|
||||
assign ga0 = 1'b0;
|
||||
assign ga1 = 1'b0;
|
||||
|
||||
ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl));
|
||||
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda));
|
||||
|
||||
ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl)); //
|
||||
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda)); //
|
||||
|
||||
|
||||
// instantiations
|
||||
|
||||
sld_signaltap #(
|
||||
.sld_advanced_trigger_entity ("basic,1,"),
|
||||
.sld_data_bits (64),
|
||||
.sld_data_bit_cntr_bits (7),
|
||||
.sld_enable_advanced_trigger (0),
|
||||
.sld_mem_address_bits (10),
|
||||
.sld_node_crc_bits (32),
|
||||
.sld_node_crc_hiword (13323),
|
||||
.sld_node_crc_loword (24084),
|
||||
.sld_node_info (1076736),
|
||||
.sld_ram_block_type ("AUTO"),
|
||||
.sld_sample_depth (1024),
|
||||
.sld_storage_qualifier_gap_record (0),
|
||||
.sld_storage_qualifier_mode ("OFF"),
|
||||
.sld_trigger_bits (1),
|
||||
.sld_trigger_in_enabled (0),
|
||||
.sld_trigger_level (1),
|
||||
.sld_trigger_level_pipeline (1))
|
||||
i_ila_adc (
|
||||
.acq_clk (clk),
|
||||
.acq_data_in (adc_ddata),
|
||||
.acq_trigger_in (adc_valid_i0));
|
||||
|
||||
system_bd i_system_bd (
|
||||
.axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
|
||||
.axi_ad9361_device_if_rx_clk_in_n (1'd0),
|
||||
.axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
|
||||
.axi_ad9361_device_if_rx_frame_in_n (1'd0),
|
||||
.axi_ad9361_device_if_rx_data_in_p (rx_data_in),
|
||||
.axi_ad9361_device_if_rx_data_in_n (6'd0),
|
||||
.axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
|
||||
.axi_ad9361_device_if_tx_clk_out_n (),
|
||||
.axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
|
||||
.axi_ad9361_device_if_tx_frame_out_n (),
|
||||
.axi_ad9361_device_if_tx_data_out_p (tx_data_out),
|
||||
.axi_ad9361_device_if_tx_data_out_n (),
|
||||
.axi_ad9361_device_if_enable (enable),
|
||||
.axi_ad9361_device_if_txnrx (txnrx),
|
||||
.axi_ad9361_up_enable_up_enable (sys_gpio_o[1]),
|
||||
.axi_ad9361_up_txnrx_up_txnrx (sys_gpio_o[0]),
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_gpio_bd_in_port (sys_gpio_bd_i),
|
||||
.sys_gpio_bd_out_port (sys_gpio_bd_o),
|
||||
.sys_gpio_in_export (sys_gpio_i),
|
||||
.sys_gpio_out_export (sys_gpio_o),
|
||||
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.sys_hps_i2c0_out_data(i2c0_out_data),
|
||||
.sys_hps_i2c0_sda(i2c0_sda),
|
||||
.sys_hps_i2c0_clk_clk(i2c0_out_clk),
|
||||
.sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
|
||||
.clk_clk (sys_clk),
|
||||
.reset_reset_n (sys_resetn),
|
||||
.sys_hps_memory_mem_a (ddr3_a),
|
||||
.sys_hps_memory_mem_ba (ddr3_ba),
|
||||
.sys_hps_memory_mem_ck (ddr3_ck_p),
|
||||
|
|
@ -272,24 +379,96 @@ module system_top (
|
|||
.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_hps_memory_mem_odt (ddr3_odt),
|
||||
.sys_hps_memory_mem_dm (ddr3_dm),
|
||||
.sys_hps_memory_oct_rzqin (ddr3_rzq),
|
||||
.sys_rst_reset_n (sys_resetn),
|
||||
.sys_spi_MISO (spi_miso),
|
||||
.sys_spi_MOSI (spi_mosi),
|
||||
.sys_spi_SCLK (spi_clk),
|
||||
.sys_spi_SS_n (spi_csn),
|
||||
.vga_out_clk_clk (vga_clk),
|
||||
.vga_out_data_vid_clk (vga_clk),
|
||||
.vga_out_data_vid_data ({vga_red, vga_grn, vga_blu}),
|
||||
.vga_out_data_underflow (),
|
||||
.vga_out_data_vid_datavalid (),
|
||||
.vga_out_data_vid_v_sync (vga_vsync),
|
||||
.vga_out_data_vid_h_sync (vga_hsync),
|
||||
.vga_out_data_vid_f (),
|
||||
.vga_out_data_vid_h (),
|
||||
.vga_out_data_vid_v (),
|
||||
.vga_if_vid_v ()
|
||||
);
|
||||
.sys_hps_memory_oct_rzqin (ddr3_oct_rzqin),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
|
||||
.sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d0),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d1),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d2),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d3),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d0),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d1),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d2),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d3),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d4),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d5),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d6),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d7),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.sys_gpio_external_connection_in_port ({16'd0, 4'd0, led, push_buttons, dip_switches}),
|
||||
.sys_gpio_external_connection_out_port ({gpio_open[31:16], gpio_open[15:12], led, gpio_open[7:0]}),
|
||||
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||
.sys_hps_spim0_txd (),
|
||||
.sys_hps_spim0_rxd (),
|
||||
.sys_hps_spim0_ss_in_n (1'b1),
|
||||
.sys_hps_spim0_ssi_oe_n (),
|
||||
.sys_hps_spim0_ss_0_n (),
|
||||
.sys_hps_spim0_ss_1_n (),
|
||||
.sys_hps_spim0_ss_2_n (),
|
||||
.sys_hps_spim0_ss_3_n (),
|
||||
.sys_hps_spim0_sclk_out_clk (),
|
||||
.axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
|
||||
.axi_ad9361_device_if_rx_clk_in_n (1'b0),
|
||||
.axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
|
||||
.axi_ad9361_device_if_rx_frame_in_n (1'b0),
|
||||
.axi_ad9361_device_if_rx_data_in_p (rx_data_in),
|
||||
.axi_ad9361_device_if_rx_data_in_n (6'd0),
|
||||
.axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
|
||||
.axi_ad9361_device_if_tx_clk_out_n (),
|
||||
.axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
|
||||
.axi_ad9361_device_if_tx_frame_out_n (),
|
||||
.axi_ad9361_device_if_tx_data_out_p (tx_data_out),
|
||||
.axi_ad9361_device_if_tx_data_out_n (),
|
||||
.axi_ad9361_l_clk_clk (clk),
|
||||
.spi_ad9361_external_MISO (spi_miso),
|
||||
.spi_ad9361_external_MOSI (spi_mosi),
|
||||
.spi_ad9361_external_SCLK (spi_clk),
|
||||
.spi_ad9361_external_SS_n (spi_csn),
|
||||
.vga_pixel_clock_bridge_out_clk_clk (vga_pixel_clock),
|
||||
.vga_clock_video_output_clocked_video_vid_clk (vga_pixel_clock),
|
||||
.vga_clock_video_output_clocked_video_vid_data ({vid_r,vid_g,vid_b}),
|
||||
.vga_clock_video_output_clocked_video_underflow (),
|
||||
.vga_clock_video_output_clocked_video_vid_datavalid (),
|
||||
.vga_clock_video_output_clocked_video_vid_v_sync (vid_v_sync),
|
||||
.vga_clock_video_output_clocked_video_vid_h_sync (vid_h_sync),
|
||||
.vga_clock_video_output_clocked_video_vid_f (),
|
||||
.vga_clock_video_output_clocked_video_vid_h (),
|
||||
.vga_clock_video_output_clocked_video_vid_v (),
|
||||
.sys_hps_i2c0_out_data(i2c0_out_data),
|
||||
.sys_hps_i2c0_sda(i2c0_sda),
|
||||
.sys_hps_i2c0_clk_clk(i2c0_out_clk),
|
||||
.sys_hps_i2c0_scl_in_clk(i2c0_scl_in_clk),
|
||||
.gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,780 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags=""
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element ad9361_clk_bridge
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "4";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element adc_pack
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_ad9361
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "5";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element axi_ad9361.s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "131072";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_dmac_adc
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "7";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element axi_dmac_adc.s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "0";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_dmac_dac
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element axi_dmac_dac.s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "16384";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element dac_upack
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "8";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element gpio
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "11";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element mem_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element mem_rst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "3";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element spi_ad9361
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "10";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element spi_ad9361.spi_control_port
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "32768";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element sys_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element sys_rst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="5CSXFC6D6F31C8ES" />
|
||||
<parameter name="deviceFamily" value="Cyclone V" />
|
||||
<parameter name="deviceSpeedGrade" value="8_H6" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="false" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="2" />
|
||||
<parameter name="projectName" value="" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
|
||||
<interface
|
||||
name="axi_ad9361_device_if"
|
||||
internal="axi_ad9361.device_if"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_l_clk"
|
||||
internal="ad9361_clk_bridge.out_clk"
|
||||
type="clock"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="axi_ad9361_s_axi"
|
||||
internal="axi_ad9361.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_adc_fifo_wr_clock"
|
||||
internal="axi_dmac_adc.fifo_wr_clock" />
|
||||
<interface name="axi_dmac_adc_fifo_wr_if" internal="axi_dmac_adc.fifo_wr_if" />
|
||||
<interface
|
||||
name="axi_dmac_adc_intr"
|
||||
internal="axi_dmac_adc.interrupt_sender"
|
||||
type="interrupt"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_adc_m_dest_axi"
|
||||
internal="axi_dmac_adc.m_dest_axi"
|
||||
type="axi4"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="axi_dmac_adc_s_axi"
|
||||
internal="axi_dmac_adc.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_dac_fifo_rd_clock"
|
||||
internal="axi_dmac_dac.fifo_rd_clock" />
|
||||
<interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
|
||||
<interface
|
||||
name="axi_dmac_dac_intr"
|
||||
internal="axi_dmac_dac.interrupt_sender"
|
||||
type="interrupt"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_dac_m_src_axi"
|
||||
internal="axi_dmac_dac.m_src_axi"
|
||||
type="axi4"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="axi_dmac_dac_s_axi"
|
||||
internal="axi_dmac_dac.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="gpio_external_connection"
|
||||
internal="gpio.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
|
||||
<interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
|
||||
<interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
|
||||
<interface
|
||||
name="spi_ad9361_external"
|
||||
internal="spi_ad9361.external"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="spi_ad9361_irq"
|
||||
internal="spi_ad9361.irq"
|
||||
type="interrupt"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="spi_ad9361_spi_control_port"
|
||||
internal="spi_ad9361.spi_control_port"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
|
||||
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
|
||||
<module
|
||||
name="ad9361_clk_bridge"
|
||||
kind="altera_clock_bridge"
|
||||
version="16.0"
|
||||
enabled="1">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module name="adc_pack" kind="util_cpack" version="1.0" enabled="1">
|
||||
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
|
||||
<parameter name="ADC_DATAFORMAT_DISABLE" value="0" />
|
||||
<parameter name="ADC_DATAPATH_DISABLE" value="0" />
|
||||
<parameter name="ADC_DCFILTER_DISABLE" value="0" />
|
||||
<parameter name="ADC_IQCORRECTION_DISABLE" value="0" />
|
||||
<parameter name="ADC_USERPORTS_DISABLE" value="0" />
|
||||
<parameter name="CMOS_OR_LVDS_N" value="0" />
|
||||
<parameter name="DAC_DATAPATH_DISABLE" value="0" />
|
||||
<parameter name="DAC_DDS_DISABLE" value="0" />
|
||||
<parameter name="DAC_IODELAY_ENABLE" value="0" />
|
||||
<parameter name="DAC_IQCORRECTION_DISABLE" value="0" />
|
||||
<parameter name="DAC_USERPORTS_DISABLE" value="0" />
|
||||
<parameter name="DEVICE_FAMILY" value="Cyclone V" />
|
||||
<parameter name="DEVICE_TYPE" value="0" />
|
||||
<parameter name="ID" value="0" />
|
||||
<parameter name="IO_DELAY_GROUP" value="dev_if_delay_group" />
|
||||
<parameter name="MODE_1R1T" value="0" />
|
||||
<parameter name="TDD_DISABLE" value="0" />
|
||||
</module>
|
||||
<module name="axi_dmac_adc" kind="axi_dmac" version="1.0" enabled="1">
|
||||
<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
|
||||
<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
|
||||
<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
|
||||
<parameter name="AXI_SLICE_DEST" value="0" />
|
||||
<parameter name="AXI_SLICE_SRC" value="0" />
|
||||
<parameter name="CYCLIC" value="0" />
|
||||
<parameter name="DMA_2D_TRANSFER" value="0" />
|
||||
<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
|
||||
<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
|
||||
<parameter name="DMA_LENGTH_WIDTH" value="24" />
|
||||
<parameter name="DMA_TYPE_DEST" value="0" />
|
||||
<parameter name="DMA_TYPE_SRC" value="2" />
|
||||
<parameter name="FIFO_SIZE" value="4" />
|
||||
<parameter name="ID" value="0" />
|
||||
<parameter name="SYNC_TRANSFER_START" value="1" />
|
||||
</module>
|
||||
<module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
|
||||
<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
|
||||
<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
|
||||
<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
|
||||
<parameter name="AXI_SLICE_DEST" value="0" />
|
||||
<parameter name="AXI_SLICE_SRC" value="0" />
|
||||
<parameter name="CYCLIC" value="1" />
|
||||
<parameter name="DMA_2D_TRANSFER" value="0" />
|
||||
<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
|
||||
<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
|
||||
<parameter name="DMA_LENGTH_WIDTH" value="24" />
|
||||
<parameter name="DMA_TYPE_DEST" value="2" />
|
||||
<parameter name="DMA_TYPE_SRC" value="0" />
|
||||
<parameter name="FIFO_SIZE" value="4" />
|
||||
<parameter name="ID" value="0" />
|
||||
<parameter name="SYNC_TRANSFER_START" value="0" />
|
||||
</module>
|
||||
<module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
|
||||
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<module name="gpio" kind="altera_avalon_pio" version="16.0" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="50000000" />
|
||||
<parameter name="direction" value="Output" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="5" />
|
||||
</module>
|
||||
<module name="mem_clk" kind="altera_clock_bridge" version="16.0" enabled="1">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module name="mem_rst" kind="altera_reset_bridge" version="16.0" enabled="1">
|
||||
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
||||
<parameter name="SYNCHRONOUS_EDGES" value="none" />
|
||||
<parameter name="USE_RESET_REQUEST" value="0" />
|
||||
</module>
|
||||
<module name="spi_ad9361" kind="altera_avalon_spi" version="16.0" enabled="1">
|
||||
<parameter name="avalonSpec" value="2.0" />
|
||||
<parameter name="clockPhase" value="0" />
|
||||
<parameter name="clockPolarity" value="1" />
|
||||
<parameter name="dataWidth" value="8" />
|
||||
<parameter name="disableAvalonFlowControl" value="false" />
|
||||
<parameter name="inputClockRate" value="50000000" />
|
||||
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
|
||||
<parameter name="insertSync" value="false" />
|
||||
<parameter name="lsbOrderedFirst" value="false" />
|
||||
<parameter name="masterSPI" value="true" />
|
||||
<parameter name="numberOfSlaves" value="1" />
|
||||
<parameter name="syncRegDepth" value="2" />
|
||||
<parameter name="targetClockRate" value="50000000" />
|
||||
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
|
||||
</module>
|
||||
<module name="sys_clk" kind="altera_clock_bridge" version="16.0" enabled="1">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module name="sys_rst" kind="altera_reset_bridge" version="16.0" enabled="1">
|
||||
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
||||
<parameter name="SYNCHRONOUS_EDGES" value="none" />
|
||||
<parameter name="USE_RESET_REQUEST" value="0" />
|
||||
</module>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="adc_pack.if_adc_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_ad9361.if_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="dac_upack.if_dac_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_dmac_dac.if_fifo_rd_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_dmac_adc.if_fifo_wr_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="ad9361_clk_bridge.in_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="sys_clk.out_clk"
|
||||
end="spi_ad9361.clk" />
|
||||
<connection kind="clock" version="16.0" start="sys_clk.out_clk" end="gpio.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_ad9361.if_delay_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_dmac_adc.m_dest_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_dmac_dac.m_src_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_ad9361.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_dmac_adc.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="16.0"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_dmac_dac.s_axi_clock" />
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="adc_pack.adc_ch_0"
|
||||
end="axi_ad9361.adc_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_ad9361.adc_ch_1"
|
||||
end="adc_pack.adc_ch_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_ad9361.adc_ch_2"
|
||||
end="adc_pack.adc_ch_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="adc_pack.adc_ch_3"
|
||||
end="axi_ad9361.adc_ch_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_ad9361.dac_ch_0"
|
||||
end="dac_upack.dac_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="dac_upack.dac_ch_1"
|
||||
end="axi_ad9361.dac_ch_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_ad9361.dac_ch_2"
|
||||
end="dac_upack.dac_ch_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="dac_upack.dac_ch_3"
|
||||
end="axi_ad9361.dac_ch_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="adc_pack.if_adc_data"
|
||||
end="axi_dmac_adc.if_fifo_wr_din">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="adc_pack.if_adc_sync"
|
||||
end="axi_dmac_adc.if_fifo_wr_sync">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="adc_pack.if_adc_valid"
|
||||
end="axi_dmac_adc.if_fifo_wr_en">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="dac_upack.if_dac_data"
|
||||
end="axi_dmac_dac.if_fifo_rd_dout">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="dac_upack.if_dma_xfer_in"
|
||||
end="axi_dmac_dac.if_fifo_rd_xfer_req">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_dmac_dac.if_fifo_rd_en"
|
||||
end="dac_upack.if_dac_valid">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_dmac_dac.if_fifo_rd_underflow"
|
||||
end="axi_ad9361.if_dac_dunf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="16.0"
|
||||
start="axi_dmac_adc.if_fifo_wr_overflow"
|
||||
end="axi_ad9361.if_adc_dovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="mem_rst.out_reset"
|
||||
end="adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_dmac_adc.m_dest_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_dmac_dac.m_src_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="spi_ad9361.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="gpio.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_ad9361.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_adc.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="16.0"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_dac.s_axi_reset" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_0|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_2|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
</system>
|
||||
|
|
@ -1,157 +0,0 @@
|
|||
|
||||
# ad9361
|
||||
|
||||
add_instance axi_ad9361 axi_ad9361 1.0
|
||||
set_instance_parameter_value axi_ad9361 {ID} {0}
|
||||
set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
|
||||
set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {1}
|
||||
set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
|
||||
set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
|
||||
set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
|
||||
set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
|
||||
add_interface axi_ad9361_device_if conduit end
|
||||
set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
|
||||
add_interface axi_ad9361_up_enable conduit end
|
||||
set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
|
||||
add_interface axi_ad9361_up_txnrx conduit end
|
||||
set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
|
||||
add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
|
||||
add_connection sys_clk.clk axi_ad9361.if_delay_clk
|
||||
add_connection sys_clk.clk axi_ad9361.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
|
||||
|
||||
# clk division
|
||||
|
||||
add_instance util_clkdiv_ad9361 util_clkdiv 1.0
|
||||
add_connection axi_ad9361.if_l_clk util_clkdiv_ad9361.if_clk
|
||||
add_connection axi_ad9361.if_rst util_clkdiv_ad9361.if_reset
|
||||
|
||||
# adc-wfifo & dac-rfifo
|
||||
|
||||
add_instance util_adc_wfifo util_wfifo 1.0
|
||||
set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
|
||||
add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
|
||||
add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
|
||||
add_connection util_clkdiv_ad9361.if_clk_out util_adc_wfifo.if_dout_clk
|
||||
add_connection util_clkdiv_ad9361.if_reset_out util_adc_wfifo.if_dout_rstn
|
||||
add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
|
||||
add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
|
||||
add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
|
||||
add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
|
||||
add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
|
||||
|
||||
# adc-wfifo & dac-rfifo
|
||||
|
||||
add_instance util_dac_rfifo util_rfifo 1.0
|
||||
set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
|
||||
set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
|
||||
add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
|
||||
add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
|
||||
add_connection util_clkdiv_ad9361.if_clk_out util_dac_rfifo.if_din_clk
|
||||
add_connection util_clkdiv_ad9361.if_reset_out util_dac_rfifo.if_din_rstn
|
||||
add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
|
||||
add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
|
||||
add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
|
||||
add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
|
||||
add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
|
||||
|
||||
# adc-pack & dac-unpack
|
||||
|
||||
add_instance util_adc_pack util_cpack 1.0
|
||||
set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
|
||||
add_connection util_clkdiv_ad9361.if_clk_out util_adc_pack.if_adc_clk
|
||||
add_connection util_clkdiv_ad9361.if_reset_out util_adc_pack.if_adc_rst
|
||||
add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
|
||||
add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
|
||||
add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
|
||||
add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
|
||||
|
||||
# adc-pack & dac-unpack
|
||||
|
||||
add_instance util_dac_upack util_upack 1.0
|
||||
set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
|
||||
set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
|
||||
add_connection util_clkdiv_ad9361.if_clk_out util_dac_upack.if_dac_clk
|
||||
add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
|
||||
add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
|
||||
add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
|
||||
add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
|
||||
|
||||
# adc-dma & dac-dma
|
||||
|
||||
add_instance axi_adc_dma axi_dmac 1.0
|
||||
set_instance_parameter_value axi_adc_dma {ID} {0}
|
||||
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
|
||||
set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
|
||||
set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
|
||||
set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
|
||||
set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
|
||||
set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
|
||||
set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
|
||||
set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
|
||||
set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
|
||||
set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
|
||||
set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
|
||||
add_connection sys_clk.clk axi_adc_dma.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
|
||||
add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
|
||||
add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
|
||||
add_connection util_clkdiv_ad9361.if_clk_out axi_adc_dma.if_fifo_wr_clk
|
||||
add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
|
||||
add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
|
||||
add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
|
||||
add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
|
||||
|
||||
# adc-dma & dac-dma
|
||||
|
||||
add_instance axi_dac_dma axi_dmac 1.0
|
||||
set_instance_parameter_value axi_dac_dma {ID} {0}
|
||||
set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
|
||||
set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
|
||||
set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
|
||||
set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
|
||||
set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
|
||||
set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
|
||||
set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
|
||||
set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
|
||||
set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
|
||||
set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
|
||||
set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
|
||||
set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
|
||||
add_connection sys_clk.clk axi_dac_dma.s_axi_clock
|
||||
add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
|
||||
add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
|
||||
add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
|
||||
add_connection util_clkdiv_ad9361.if_clk_out axi_dac_dma.if_fifo_rd_clk
|
||||
add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
|
||||
add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
|
||||
add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in
|
||||
add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender
|
||||
ad_cpu_interrupt 3 axi_dac_dma.interrupt_sender
|
||||
|
||||
# cpu interconnects
|
||||
|
||||
ad_cpu_interconnect 0x00120000 axi_ad9361.s_axi
|
||||
ad_cpu_interconnect 0x00100000 axi_adc_dma.s_axi
|
||||
ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
|
||||
|
||||
# mem interconnects
|
||||
|
||||
ad_dma_interconnect axi_adc_dma.m_dest_axi 0
|
||||
ad_dma_interconnect axi_dac_dma.m_src_axi 1
|
||||
|
||||
|
|
@ -14,95 +14,95 @@ set_instance_assignment -name IO_STANDARD "1.5 V" -to sys_clk
|
|||
set_location_assignment PIN_W20 -to vga_clk
|
||||
set_location_assignment PIN_AH3 -to vga_blank_n
|
||||
set_location_assignment PIN_AG2 -to vga_sync_n
|
||||
set_location_assignment PIN_AD12 -to vga_hsync
|
||||
set_location_assignment PIN_AC12 -to vga_vsync
|
||||
set_location_assignment PIN_AG5 -to vga_red[0]
|
||||
set_location_assignment PIN_AA12 -to vga_red[1]
|
||||
set_location_assignment PIN_AB12 -to vga_red[2]
|
||||
set_location_assignment PIN_AF6 -to vga_red[3]
|
||||
set_location_assignment PIN_AG6 -to vga_red[4]
|
||||
set_location_assignment PIN_AJ2 -to vga_red[5]
|
||||
set_location_assignment PIN_AH5 -to vga_red[6]
|
||||
set_location_assignment PIN_AJ1 -to vga_red[7]
|
||||
set_location_assignment PIN_Y21 -to vga_grn[0]
|
||||
set_location_assignment PIN_AA25 -to vga_grn[1]
|
||||
set_location_assignment PIN_AB26 -to vga_grn[2]
|
||||
set_location_assignment PIN_AB22 -to vga_grn[3]
|
||||
set_location_assignment PIN_AB23 -to vga_grn[4]
|
||||
set_location_assignment PIN_AA24 -to vga_grn[5]
|
||||
set_location_assignment PIN_AB25 -to vga_grn[6]
|
||||
set_location_assignment PIN_AE27 -to vga_grn[7]
|
||||
set_location_assignment PIN_AE28 -to vga_blu[0]
|
||||
set_location_assignment PIN_Y23 -to vga_blu[1]
|
||||
set_location_assignment PIN_Y24 -to vga_blu[2]
|
||||
set_location_assignment PIN_AG28 -to vga_blu[3]
|
||||
set_location_assignment PIN_AF28 -to vga_blu[4]
|
||||
set_location_assignment PIN_V23 -to vga_blu[5]
|
||||
set_location_assignment PIN_W24 -to vga_blu[6]
|
||||
set_location_assignment PIN_AF29 -to vga_blu[7]
|
||||
|
||||
set_location_assignment PIN_AD12 -to vga_hs
|
||||
set_location_assignment PIN_AC12 -to vga_vs
|
||||
set_location_assignment PIN_AF29 -to vga_b[7]
|
||||
set_location_assignment PIN_AE28 -to vga_b[0]
|
||||
set_location_assignment PIN_Y23 -to vga_b[1]
|
||||
set_location_assignment PIN_Y24 -to vga_b[2]
|
||||
set_location_assignment PIN_AG28 -to vga_b[3]
|
||||
set_location_assignment PIN_AF28 -to vga_b[4]
|
||||
set_location_assignment PIN_V23 -to vga_b[5]
|
||||
set_location_assignment PIN_W24 -to vga_b[6]
|
||||
set_location_assignment PIN_Y21 -to vga_g[0]
|
||||
set_location_assignment PIN_AA25 -to vga_g[1]
|
||||
set_location_assignment PIN_AB26 -to vga_g[2]
|
||||
set_location_assignment PIN_AB22 -to vga_g[3]
|
||||
set_location_assignment PIN_AB23 -to vga_g[4]
|
||||
set_location_assignment PIN_AA24 -to vga_g[5]
|
||||
set_location_assignment PIN_AB25 -to vga_g[6]
|
||||
set_location_assignment PIN_AE27 -to vga_g[7]
|
||||
set_location_assignment PIN_AG5 -to vga_r[0]
|
||||
set_location_assignment PIN_AA12 -to vga_r[1]
|
||||
set_location_assignment PIN_AB12 -to vga_r[2]
|
||||
set_location_assignment PIN_AF6 -to vga_r[3]
|
||||
set_location_assignment PIN_AG6 -to vga_r[4]
|
||||
set_location_assignment PIN_AJ2 -to vga_r[5]
|
||||
set_location_assignment PIN_AH5 -to vga_r[6]
|
||||
set_location_assignment PIN_AJ1 -to vga_r[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blank_n
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_sync_n
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hsync
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vsync
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_red[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_grn[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blu[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[7]
|
||||
|
||||
# led & switches
|
||||
|
||||
set_location_assignment PIN_AD7 -to gpio_bd_o[3]
|
||||
set_location_assignment PIN_AE11 -to gpio_bd_o[2]
|
||||
set_location_assignment PIN_AD10 -to gpio_bd_o[1]
|
||||
set_location_assignment PIN_AF10 -to gpio_bd_o[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_o[0]
|
||||
set_location_assignment PIN_AD7 -to led[3]
|
||||
set_location_assignment PIN_AE11 -to led[2]
|
||||
set_location_assignment PIN_AD10 -to led[1]
|
||||
set_location_assignment PIN_AF10 -to led[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[0]
|
||||
|
||||
set_location_assignment PIN_AD11 -to gpio_bd_i[0]
|
||||
set_location_assignment PIN_AD9 -to gpio_bd_i[1]
|
||||
set_location_assignment PIN_AE12 -to gpio_bd_i[2]
|
||||
set_location_assignment PIN_AE9 -to gpio_bd_i[3]
|
||||
set_location_assignment PIN_AC29 -to gpio_bd_i[4]
|
||||
set_location_assignment PIN_AC28 -to gpio_bd_i[5]
|
||||
set_location_assignment PIN_V25 -to gpio_bd_i[6]
|
||||
set_location_assignment PIN_W25 -to gpio_bd_i[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd_i[3]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7]
|
||||
set_location_assignment PIN_AD11 -to push_buttons[3]
|
||||
set_location_assignment PIN_AD9 -to push_buttons[2]
|
||||
set_location_assignment PIN_AE12 -to push_buttons[1]
|
||||
set_location_assignment PIN_AE9 -to push_buttons[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to push_buttons[0]
|
||||
|
||||
set_location_assignment PIN_AC29 -to dip_switches[3]
|
||||
set_location_assignment PIN_AC28 -to dip_switches[2]
|
||||
set_location_assignment PIN_V25 -to dip_switches[1]
|
||||
set_location_assignment PIN_W25 -to dip_switches[0]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0]
|
||||
|
||||
# uart
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_rx
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_tx
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_rx
|
||||
|
||||
# spim1 (lcd)
|
||||
|
||||
|
|
@ -117,47 +117,47 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk
|
|||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d5
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d6
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d7
|
||||
|
||||
# sdio
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_clk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_cmd
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sdio_d3
|
||||
|
||||
# qspi
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_ss0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io3
|
||||
|
||||
# ethernet
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio
|
||||
|
||||
|
|
@ -320,7 +320,7 @@ set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
|
|||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_rzq
|
||||
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_oct_rzqin
|
||||
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
|
||||
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
|
||||
|
|
@ -444,81 +444,6 @@ set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
|
|||
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
|
||||
|
||||
# ddr3 pin locations (quartus critical warnings)
|
||||
|
||||
set_location_assignment PIN_F26 -to ddr3_a[0]
|
||||
set_location_assignment PIN_G30 -to ddr3_a[1]
|
||||
set_location_assignment PIN_F28 -to ddr3_a[2]
|
||||
set_location_assignment PIN_F30 -to ddr3_a[3]
|
||||
set_location_assignment PIN_J25 -to ddr3_a[4]
|
||||
set_location_assignment PIN_J27 -to ddr3_a[5]
|
||||
set_location_assignment PIN_F29 -to ddr3_a[6]
|
||||
set_location_assignment PIN_E28 -to ddr3_a[7]
|
||||
set_location_assignment PIN_H27 -to ddr3_a[8]
|
||||
set_location_assignment PIN_G26 -to ddr3_a[9]
|
||||
set_location_assignment PIN_D29 -to ddr3_a[10]
|
||||
set_location_assignment PIN_C30 -to ddr3_a[11]
|
||||
set_location_assignment PIN_B30 -to ddr3_a[12]
|
||||
set_location_assignment PIN_C29 -to ddr3_a[13]
|
||||
set_location_assignment PIN_H25 -to ddr3_a[14]
|
||||
set_location_assignment PIN_E29 -to ddr3_ba[0]
|
||||
set_location_assignment PIN_J24 -to ddr3_ba[1]
|
||||
set_location_assignment PIN_J23 -to ddr3_ba[2]
|
||||
set_location_assignment PIN_E27 -to ddr3_cas_n
|
||||
set_location_assignment PIN_M23 -to ddr3_ck_p
|
||||
set_location_assignment PIN_L23 -to ddr3_ck_n
|
||||
set_location_assignment PIN_L29 -to ddr3_cke
|
||||
set_location_assignment PIN_H24 -to ddr3_cs_n
|
||||
set_location_assignment PIN_K28 -to ddr3_dm[0]
|
||||
set_location_assignment PIN_M28 -to ddr3_dm[1]
|
||||
set_location_assignment PIN_R28 -to ddr3_dm[2]
|
||||
set_location_assignment PIN_W30 -to ddr3_dm[3]
|
||||
set_location_assignment PIN_K23 -to ddr3_dq[0]
|
||||
set_location_assignment PIN_K22 -to ddr3_dq[1]
|
||||
set_location_assignment PIN_H30 -to ddr3_dq[2]
|
||||
set_location_assignment PIN_G28 -to ddr3_dq[3]
|
||||
set_location_assignment PIN_L25 -to ddr3_dq[4]
|
||||
set_location_assignment PIN_L24 -to ddr3_dq[5]
|
||||
set_location_assignment PIN_J30 -to ddr3_dq[6]
|
||||
set_location_assignment PIN_J29 -to ddr3_dq[7]
|
||||
set_location_assignment PIN_K26 -to ddr3_dq[8]
|
||||
set_location_assignment PIN_L26 -to ddr3_dq[9]
|
||||
set_location_assignment PIN_K29 -to ddr3_dq[10]
|
||||
set_location_assignment PIN_K27 -to ddr3_dq[11]
|
||||
set_location_assignment PIN_M26 -to ddr3_dq[12]
|
||||
set_location_assignment PIN_M27 -to ddr3_dq[13]
|
||||
set_location_assignment PIN_L28 -to ddr3_dq[14]
|
||||
set_location_assignment PIN_M30 -to ddr3_dq[15]
|
||||
set_location_assignment PIN_U26 -to ddr3_dq[16]
|
||||
set_location_assignment PIN_T26 -to ddr3_dq[17]
|
||||
set_location_assignment PIN_N29 -to ddr3_dq[18]
|
||||
set_location_assignment PIN_N28 -to ddr3_dq[19]
|
||||
set_location_assignment PIN_P26 -to ddr3_dq[20]
|
||||
set_location_assignment PIN_P27 -to ddr3_dq[21]
|
||||
set_location_assignment PIN_N27 -to ddr3_dq[22]
|
||||
set_location_assignment PIN_R29 -to ddr3_dq[23]
|
||||
set_location_assignment PIN_P24 -to ddr3_dq[24]
|
||||
set_location_assignment PIN_P25 -to ddr3_dq[25]
|
||||
set_location_assignment PIN_T29 -to ddr3_dq[26]
|
||||
set_location_assignment PIN_T28 -to ddr3_dq[27]
|
||||
set_location_assignment PIN_R27 -to ddr3_dq[28]
|
||||
set_location_assignment PIN_R26 -to ddr3_dq[29]
|
||||
set_location_assignment PIN_V30 -to ddr3_dq[30]
|
||||
set_location_assignment PIN_W29 -to ddr3_dq[31]
|
||||
set_location_assignment PIN_N18 -to ddr3_dqs_p[0]
|
||||
set_location_assignment PIN_M19 -to ddr3_dqs_n[0]
|
||||
set_location_assignment PIN_N25 -to ddr3_dqs_p[1]
|
||||
set_location_assignment PIN_N24 -to ddr3_dqs_n[1]
|
||||
set_location_assignment PIN_R19 -to ddr3_dqs_p[2]
|
||||
set_location_assignment PIN_R18 -to ddr3_dqs_n[2]
|
||||
set_location_assignment PIN_R22 -to ddr3_dqs_p[3]
|
||||
set_location_assignment PIN_R21 -to ddr3_dqs_n[3]
|
||||
set_location_assignment PIN_H28 -to ddr3_odt
|
||||
set_location_assignment PIN_D30 -to ddr3_ras_n
|
||||
set_location_assignment PIN_P30 -to ddr3_reset_n
|
||||
set_location_assignment PIN_C28 -to ddr3_we_n
|
||||
set_location_assignment PIN_D27 -to ddr3_rzq
|
||||
|
||||
# globals
|
||||
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
|
||||
|
|
@ -536,6 +461,7 @@ set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
|||
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
|
||||
|
||||
# source defaults
|
||||
|
||||
source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
|
|
@ -1,311 +0,0 @@
|
|||
|
||||
package require qsys
|
||||
|
||||
set_module_property NAME {system_bd}
|
||||
set_project_property DEVICE_FAMILY {Cyclone V}
|
||||
set_project_property DEVICE {5CSXFC6D6F31C8ES}
|
||||
|
||||
# system clock
|
||||
|
||||
add_instance sys_clk clock_source 16.0
|
||||
set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
|
||||
set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
|
||||
set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
|
||||
add_interface sys_clk clock sink
|
||||
add_interface sys_rst reset sink
|
||||
set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
|
||||
set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
|
||||
|
||||
# hps
|
||||
|
||||
add_instance sys_hps altera_hps 16.0
|
||||
set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
|
||||
set_instance_parameter_value sys_hps {F2SDRAM_Type} {Avalon-MM\ Bidirectional AXI-3 AXI-3}
|
||||
set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
|
||||
set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
|
||||
set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
|
||||
set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
|
||||
set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
|
||||
set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
|
||||
set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
|
||||
set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
|
||||
set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
|
||||
set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
|
||||
set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
|
||||
set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
|
||||
set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
|
||||
set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
|
||||
set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
|
||||
set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
|
||||
set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
|
||||
set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
|
||||
set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
|
||||
set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
|
||||
set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
|
||||
set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
|
||||
set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
|
||||
set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
|
||||
set_instance_parameter_value sys_hps {MEM_TCL} {11}
|
||||
set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
|
||||
set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
|
||||
set_instance_parameter_value sys_hps {MEM_WTCL} {8}
|
||||
set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
|
||||
set_instance_parameter_value sys_hps {TIMING_TIS} {180}
|
||||
set_instance_parameter_value sys_hps {TIMING_TIH} {140}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDS} {30}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDH} {65}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
|
||||
set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
|
||||
set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
|
||||
set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
|
||||
set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
|
||||
set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
|
||||
set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
|
||||
set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
|
||||
set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
|
||||
set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TWTR} {4}
|
||||
set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
|
||||
set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
|
||||
set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
|
||||
set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
|
||||
add_interface sys_hps_memory conduit end
|
||||
set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
|
||||
add_interface sys_hps_hps_io conduit end
|
||||
set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
|
||||
add_interface sys_hps_h2f_reset reset source
|
||||
set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
|
||||
add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
|
||||
add_connection sys_clk.clk sys_hps.h2f_axi_clock
|
||||
add_connection sys_clk.clk sys_hps.f2h_axi_clock
|
||||
add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
|
||||
add_interface sys_hps_i2c0 conduit end
|
||||
set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
|
||||
add_interface sys_hps_i2c0_clk clock source
|
||||
set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
|
||||
add_interface sys_hps_i2c0_scl_in clock sink
|
||||
set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
|
||||
|
||||
# cpu/hps handling
|
||||
|
||||
proc ad_cpu_interrupt {m_irq m_port} {
|
||||
|
||||
add_connection sys_hps.f2h_irq0 ${m_port}
|
||||
set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
|
||||
}
|
||||
|
||||
proc ad_cpu_interconnect {m_base m_port} {
|
||||
|
||||
add_connection sys_hps.h2f_lw_axi_master ${m_port}
|
||||
set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
|
||||
}
|
||||
|
||||
proc ad_dma_interconnect {m_port m_id} {
|
||||
|
||||
if {${m_id} == 1} {
|
||||
add_connection ${m_port} sys_hps.f2h_sdram1_data
|
||||
set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
|
||||
return
|
||||
}
|
||||
|
||||
add_connection ${m_port} sys_hps.f2h_sdram2_data
|
||||
set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram2_data baseAddress {0x0000}
|
||||
}
|
||||
|
||||
# common dma interfaces
|
||||
|
||||
add_instance sys_dma_clk clock_source 16.0
|
||||
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
|
||||
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
|
||||
add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
|
||||
add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
|
||||
|
||||
# internal memory
|
||||
|
||||
add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
|
||||
set_instance_parameter_value sys_int_mem {dualPort} {0}
|
||||
set_instance_parameter_value sys_int_mem {dataWidth} {64}
|
||||
set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
|
||||
set_instance_parameter_value sys_int_mem {initMemContent} {0}
|
||||
add_connection sys_clk.clk sys_int_mem.clk1
|
||||
add_connection sys_clk.clk_reset sys_int_mem.reset1
|
||||
add_connection sys_hps.h2f_axi_master sys_int_mem.s1
|
||||
set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
|
||||
|
||||
# display (vga-pll)
|
||||
|
||||
add_instance vga_pll altera_pll 16.0
|
||||
set_instance_parameter_value vga_pll {gui_device_speed_grade} {2}
|
||||
set_instance_parameter_value vga_pll {gui_reference_clock_frequency} {50.0}
|
||||
set_instance_parameter_value vga_pll {gui_use_locked} {0}
|
||||
set_instance_parameter_value vga_pll {gui_number_of_clocks} {2}
|
||||
set_instance_parameter_value vga_pll {gui_output_clock_frequency0} {85.5}
|
||||
set_instance_parameter_value vga_pll {gui_output_clock_frequency1} {171.0}
|
||||
add_connection sys_clk.clk vga_pll.refclk
|
||||
add_connection sys_clk.clk_reset vga_pll.reset
|
||||
|
||||
# display (vga-frame-reader)
|
||||
|
||||
add_instance vga_frame_reader alt_vip_vfr 14.0
|
||||
set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
|
||||
set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
|
||||
set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
|
||||
set_instance_parameter_value vga_frame_reader {MAX_IMAGE_WIDTH} {1360}
|
||||
set_instance_parameter_value vga_frame_reader {MAX_IMAGE_HEIGHT} {768}
|
||||
set_instance_parameter_value vga_frame_reader {MEM_PORT_WIDTH} {128}
|
||||
set_instance_parameter_value vga_frame_reader {RMASTER_FIFO_DEPTH} {64}
|
||||
set_instance_parameter_value vga_frame_reader {RMASTER_BURST_TARGET} {32}
|
||||
set_instance_parameter_value vga_frame_reader {CLOCKS_ARE_SEPARATE} {1}
|
||||
add_connection sys_clk.clk vga_frame_reader.clock_master
|
||||
add_connection sys_clk.clk_reset vga_frame_reader.clock_master_reset
|
||||
add_connection vga_frame_reader.avalon_master sys_hps.f2h_sdram0_data
|
||||
set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data baseAddress {0x0000}
|
||||
add_connection vga_pll.outclk0 vga_frame_reader.clock_reset
|
||||
add_connection sys_clk.clk_reset vga_frame_reader.clock_reset_reset
|
||||
|
||||
# display (vga-out-clock)
|
||||
|
||||
add_instance vga_out_clock altera_clock_bridge 16.0
|
||||
set_instance_parameter_value vga_out_clock {NUM_CLOCK_OUTPUTS} {1}
|
||||
add_connection vga_pll.outclk0 vga_out_clock.in_clk
|
||||
add_interface vga_out_clk clock source
|
||||
set_interface_property vga_out_clk EXPORT_OF vga_out_clock.out_clk
|
||||
|
||||
# display (vga-out-data)
|
||||
|
||||
add_instance vga_out_data alt_vip_itc 14.0
|
||||
set_instance_parameter_value vga_out_data {H_ACTIVE_PIXELS} {1360}
|
||||
set_instance_parameter_value vga_out_data {V_ACTIVE_LINES} {768}
|
||||
set_instance_parameter_value vga_out_data {BPS} {8}
|
||||
set_instance_parameter_value vga_out_data {NUMBER_OF_COLOUR_PLANES} {4}
|
||||
set_instance_parameter_value vga_out_data {COLOUR_PLANES_ARE_IN_PARALLEL} {1}
|
||||
set_instance_parameter_value vga_out_data {ACCEPT_COLOURS_IN_SEQ} {0}
|
||||
set_instance_parameter_value vga_out_data {INTERLACED} {0}
|
||||
set_instance_parameter_value vga_out_data {USE_EMBEDDED_SYNCS} {0}
|
||||
set_instance_parameter_value vga_out_data {AP_LINE} {0}
|
||||
set_instance_parameter_value vga_out_data {ANC_LINE} {0}
|
||||
set_instance_parameter_value vga_out_data {H_BLANK} {0}
|
||||
set_instance_parameter_value vga_out_data {V_BLANK} {0}
|
||||
set_instance_parameter_value vga_out_data {H_SYNC_LENGTH} {112}
|
||||
set_instance_parameter_value vga_out_data {H_FRONT_PORCH} {64}
|
||||
set_instance_parameter_value vga_out_data {H_BACK_PORCH} {256}
|
||||
set_instance_parameter_value vga_out_data {V_SYNC_LENGTH} {6}
|
||||
set_instance_parameter_value vga_out_data {V_FRONT_PORCH} {3}
|
||||
set_instance_parameter_value vga_out_data {V_BACK_PORCH} {18}
|
||||
set_instance_parameter_value vga_out_data {F_RISING_EDGE} {0}
|
||||
set_instance_parameter_value vga_out_data {F_FALLING_EDGE} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_RISING_EDGE} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_ANC_LINE} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_BLANK} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_SYNC_LENGTH} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_FRONT_PORCH} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_BACK_PORCH} {0}
|
||||
set_instance_parameter_value vga_out_data {FIFO_DEPTH} {1920}
|
||||
set_instance_parameter_value vga_out_data {THRESHOLD} {1919}
|
||||
set_instance_parameter_value vga_out_data {CLOCKS_ARE_SAME} {0}
|
||||
set_instance_parameter_value vga_out_data {USE_CONTROL} {0}
|
||||
set_instance_parameter_value vga_out_data {GENERATE_SYNC} {0}
|
||||
set_instance_parameter_value vga_out_data {NO_OF_MODES} {1}
|
||||
set_instance_parameter_value vga_out_data {STD_WIDTH} {1}
|
||||
add_connection vga_pll.outclk0 vga_out_data.is_clk_rst
|
||||
add_connection sys_clk.clk_reset vga_out_data.is_clk_rst_reset
|
||||
add_connection vga_frame_reader.avalon_streaming_source vga_out_data.din
|
||||
add_interface vga_out_data conduit end
|
||||
set_interface_property vga_out_data EXPORT_OF vga_out_data.clocked_video
|
||||
|
||||
# id
|
||||
|
||||
add_instance sys_id altera_avalon_sysid_qsys 16.0
|
||||
set_instance_parameter_value sys_id {id} {-1395322110}
|
||||
add_connection sys_clk.clk sys_id.clk
|
||||
add_connection sys_clk.clk_reset sys_id.reset
|
||||
|
||||
# gpio-bd
|
||||
|
||||
add_instance sys_gpio_bd altera_avalon_pio 16.0
|
||||
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
|
||||
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_bd {width} {32}
|
||||
add_connection sys_clk.clk sys_gpio_bd.clk
|
||||
add_connection sys_clk.clk_reset sys_gpio_bd.reset
|
||||
add_interface sys_gpio_bd conduit end
|
||||
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
|
||||
|
||||
# gpio-in
|
||||
|
||||
add_instance sys_gpio_in altera_avalon_pio 16.0
|
||||
set_instance_parameter_value sys_gpio_in {direction} {Input}
|
||||
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_in {width} {32}
|
||||
add_connection sys_clk.clk_reset sys_gpio_in.reset
|
||||
add_connection sys_clk.clk sys_gpio_in.clk
|
||||
add_interface sys_gpio_in conduit end
|
||||
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
|
||||
|
||||
# gpio-out
|
||||
|
||||
add_instance sys_gpio_out altera_avalon_pio 16.0
|
||||
set_instance_parameter_value sys_gpio_out {direction} {Output}
|
||||
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
|
||||
set_instance_parameter_value sys_gpio_out {width} {32}
|
||||
add_connection sys_clk.clk_reset sys_gpio_out.reset
|
||||
add_connection sys_clk.clk sys_gpio_out.clk
|
||||
add_interface sys_gpio_out conduit end
|
||||
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
|
||||
|
||||
# spi
|
||||
|
||||
add_instance sys_spi altera_avalon_spi 16.0
|
||||
set_instance_parameter_value sys_spi {clockPhase} {0}
|
||||
set_instance_parameter_value sys_spi {clockPolarity} {1}
|
||||
set_instance_parameter_value sys_spi {dataWidth} {8}
|
||||
set_instance_parameter_value sys_spi {masterSPI} {1}
|
||||
set_instance_parameter_value sys_spi {numberOfSlaves} {1}
|
||||
set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
|
||||
add_connection sys_clk.clk sys_spi.clk
|
||||
add_connection sys_clk.clk_reset sys_spi.reset
|
||||
add_interface sys_spi conduit end
|
||||
set_interface_property sys_spi EXPORT_OF sys_spi.external
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 0 sys_gpio_bd.irq
|
||||
ad_cpu_interrupt 1 sys_spi.irq
|
||||
ad_cpu_interrupt 4 vga_frame_reader.interrupt_sender
|
||||
|
||||
# cpu interconnects
|
||||
|
||||
ad_cpu_interconnect 0x00108000 sys_spi.spi_control_port
|
||||
ad_cpu_interconnect 0x00009000 vga_frame_reader.avalon_slave
|
||||
ad_cpu_interconnect 0x00010000 sys_id.control_slave
|
||||
ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1
|
||||
ad_cpu_interconnect 0x00010100 sys_gpio_in.s1
|
||||
ad_cpu_interconnect 0x00109000 sys_gpio_out.s1
|
||||
|
||||
Loading…
Reference in New Issue