From ed6bdf66bdcf7d63ea8a0697b98d6c3fff84e17b Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 16 Jul 2015 14:10:49 +0300 Subject: [PATCH] axi_ad9361/tdd: Add new control signals to the TDD data flow control logic Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control. --- library/axi_ad9361/axi_ad9361.v | 16 +++++-- library/axi_ad9361/axi_ad9361_tdd.v | 51 +++++++++++++++++++--- library/common/up_tdd_cntrl.v | 67 ++++++++++++++++++----------- 3 files changed, 100 insertions(+), 34 deletions(-) diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index acb5fb093..ee7169628 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -411,6 +411,14 @@ module axi_ad9361 ( .tdd_tx_valid_q0(dac_valid_q0), .tdd_tx_valid_i1(dac_valid_i1), .tdd_tx_valid_q1(dac_valid_q1), + .rx_valid_i0(adc_valid_i0_s), + .rx_valid_q0(adc_valid_q0_s), + .rx_valid_i1(adc_valid_i1_s), + .rx_valid_q1(adc_valid_q1_s), + .tdd_rx_valid_i0(adc_valid_i0), + .tdd_rx_valid_q0(adc_valid_q0), + .tdd_rx_valid_i1(adc_valid_i1), + .tdd_rx_valid_q1(adc_valid_q1), .up_rstn(up_rstn), .up_clk(up_clk), .up_wreq(up_wreq_s), @@ -446,16 +454,16 @@ module axi_ad9361 ( .delay_rst (delay_rst), .delay_locked (delay_locked_s), .adc_enable_i0 (adc_enable_i0), - .adc_valid_i0 (adc_valid_i0), + .adc_valid_i0 (adc_valid_i0_s), .adc_data_i0 (adc_data_i0), .adc_enable_q0 (adc_enable_q0), - .adc_valid_q0 (adc_valid_q0), + .adc_valid_q0 (adc_valid_q0_s), .adc_data_q0 (adc_data_q0), .adc_enable_i1 (adc_enable_i1), - .adc_valid_i1 (adc_valid_i1), + .adc_valid_i1 (adc_valid_i1_s), .adc_data_i1 (adc_data_i1), .adc_enable_q1 (adc_enable_q1), - .adc_valid_q1 (adc_valid_q1), + .adc_valid_q1 (adc_valid_q1_s), .adc_data_q1 (adc_data_q1), .adc_dovf (adc_dovf), .adc_dunf (adc_dunf), diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v index 40c2e325e..7c8c29215 100644 --- a/library/axi_ad9361/axi_ad9361_tdd.v +++ b/library/axi_ad9361/axi_ad9361_tdd.v @@ -58,7 +58,7 @@ module axi_ad9361_tdd ( tdd_enable, tdd_status, - // tx data flow control + // tx/rx data flow control tx_valid_i0, tx_valid_q0, @@ -70,6 +70,16 @@ module axi_ad9361_tdd ( tdd_tx_valid_i1, tdd_tx_valid_q1, + rx_valid_i0, + rx_valid_q0, + rx_valid_i1, + rx_valid_q1, + + tdd_rx_valid_i0, + tdd_rx_valid_q0, + tdd_rx_valid_i1, + tdd_rx_valid_q1, + // bus interface up_rstn, @@ -111,6 +121,18 @@ module axi_ad9361_tdd ( output tdd_tx_valid_i1; output tdd_tx_valid_q1; + // rx data flow control + + input rx_valid_i0; + input rx_valid_q0; + input rx_valid_i1; + input rx_valid_q1; + + output tdd_rx_valid_i0; + output tdd_rx_valid_q0; + output tdd_rx_valid_i1; + output tdd_rx_valid_q1; + // bus interface input up_rstn; @@ -134,6 +156,8 @@ module axi_ad9361_tdd ( wire [ 7:0] tdd_burst_count_s; wire tdd_rx_only_s; wire tdd_tx_only_s; + wire tdd_gated_rx_dmapath_s; + wire tdd_gated_tx_dmapath_s; wire [23:0] tdd_counter_init_s; wire [23:0] tdd_frame_length_s; wire [23:0] tdd_vco_rx_on_1_s; @@ -164,12 +188,25 @@ module axi_ad9361_tdd ( assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_tx_dp_en_s, tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en}; - // tx data flow control + // tx/rx data flow control - assign tdd_tx_valid_i0 = (tdd_enable_s == 1'b1) ? (tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0; - assign tdd_tx_valid_q0 = (tdd_enable_s == 1'b1) ? (tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0; - assign tdd_tx_valid_i1 = (tdd_enable_s == 1'b1) ? (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1; - assign tdd_tx_valid_q1 = (tdd_enable_s == 1'b1) ? (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1; + assign tdd_tx_valid_i0 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + (tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0; + assign tdd_tx_valid_q0 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + (tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0; + assign tdd_tx_valid_i1 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1; + assign tdd_tx_valid_q1 = ((tdd_enable_s & tdd_gated_tx_dmapath_s) == 1'b1) ? + (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1; + + assign tdd_rx_valid_i0 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + (rx_valid_i0 & tdd_rx_rf_en) : rx_valid_i0; + assign tdd_rx_valid_q0 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + (rx_valid_q0 & tdd_rx_rf_en) : rx_valid_q0; + assign tdd_rx_valid_i1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + (rx_valid_i1 & tdd_rx_rf_en) : rx_valid_i1; + assign tdd_rx_valid_q1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ? + (rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1; assign tdd_enable = tdd_enable_s; @@ -183,6 +220,8 @@ module axi_ad9361_tdd ( .tdd_burst_count(tdd_burst_count_s), .tdd_tx_only(tdd_tx_only_s), .tdd_rx_only(tdd_rx_only_s), + .tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s), + .tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s), .tdd_counter_init(tdd_counter_init_s), .tdd_frame_length(tdd_frame_length_s), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), diff --git a/library/common/up_tdd_cntrl.v b/library/common/up_tdd_cntrl.v index 0bd755668..5f7f179aa 100644 --- a/library/common/up_tdd_cntrl.v +++ b/library/common/up_tdd_cntrl.v @@ -49,6 +49,8 @@ module up_tdd_cntrl ( tdd_secondary, tdd_rx_only, tdd_tx_only, + tdd_gated_rx_dmapath, + tdd_gated_tx_dmapath, tdd_burst_count, tdd_counter_init, tdd_frame_length, @@ -100,6 +102,8 @@ module up_tdd_cntrl ( output tdd_secondary; output tdd_rx_only; output tdd_tx_only; + output tdd_gated_rx_dmapath; + output tdd_gated_tx_dmapath; output [ 7:0] tdd_burst_count; output [23:0] tdd_counter_init; output [23:0] tdd_frame_length; @@ -150,6 +154,8 @@ module up_tdd_cntrl ( reg up_tdd_secondary = 1'h0; reg up_tdd_rx_only = 1'h0; reg up_tdd_tx_only = 1'h0; + reg up_tdd_gated_tx_dmapath = 1'h0; + reg up_tdd_gated_rx_dmapath = 1'h0; reg [ 7:0] up_tdd_burst_count = 8'h0; reg [23:0] up_tdd_counter_init = 24'h0; @@ -198,6 +204,8 @@ module up_tdd_cntrl ( up_tdd_secondary <= 1'h0; up_tdd_rx_only <= 1'h0; up_tdd_tx_only <= 1'h0; + up_tdd_gated_tx_dmapath <= 1'h0; + up_tdd_gated_rx_dmapath <= 1'h0; up_tdd_counter_init <= 24'h0; up_tdd_frame_length <= 24'h0; up_tdd_burst_count <= 8'h0; @@ -226,6 +234,8 @@ module up_tdd_cntrl ( up_tdd_secondary <= up_wdata[1]; up_tdd_rx_only <= up_wdata[2]; up_tdd_tx_only <= up_wdata[3]; + up_tdd_gated_rx_dmapath <= up_wdata[4]; + up_tdd_gated_tx_dmapath <= up_wdata[5]; end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin up_tdd_burst_count <= up_wdata[7:0]; @@ -309,31 +319,36 @@ module up_tdd_cntrl ( up_rack <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[7:0]) - 8'h10: up_rdata <= {28'h0, up_tdd_tx_only, up_tdd_rx_only, up_tdd_secondary, up_tdd_enable}; + 8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath, + up_tdd_gated_rx_dmapath, + up_tdd_tx_only, + up_tdd_rx_only, + up_tdd_secondary, + up_tdd_enable}; 8'h11: up_rdata <= {24'h0, up_tdd_burst_count}; - 8'h12: up_rdata <= {8'h0, up_tdd_counter_init}; - 8'h13: up_rdata <= {8'h0, up_tdd_frame_length}; + 8'h12: up_rdata <= { 8'h0, up_tdd_counter_init}; + 8'h13: up_rdata <= { 8'h0, up_tdd_frame_length}; 8'h18: up_rdata <= {24'h0, up_tdd_status_s}; - 8'h20: up_rdata <= {8'h0, up_tdd_vco_rx_on_1}; - 8'h21: up_rdata <= {8'h0, up_tdd_vco_rx_off_1}; - 8'h22: up_rdata <= {8'h0, up_tdd_vco_tx_on_1}; - 8'h23: up_rdata <= {8'h0, up_tdd_vco_tx_off_1}; - 8'h24: up_rdata <= {8'h0, up_tdd_rx_on_1}; - 8'h25: up_rdata <= {8'h0, up_tdd_rx_off_1}; - 8'h26: up_rdata <= {8'h0, up_tdd_tx_on_1}; - 8'h27: up_rdata <= {8'h0, up_tdd_tx_off_1}; - 8'h28: up_rdata <= {8'h0, up_tdd_tx_dp_on_1}; - 8'h29: up_rdata <= {8'h0, up_tdd_tx_dp_off_1}; - 8'h30: up_rdata <= {8'h0, up_tdd_vco_rx_on_2}; - 8'h31: up_rdata <= {8'h0, up_tdd_vco_rx_off_2}; - 8'h32: up_rdata <= {8'h0, up_tdd_vco_tx_on_2}; - 8'h33: up_rdata <= {8'h0, up_tdd_vco_tx_off_2}; - 8'h34: up_rdata <= {8'h0, up_tdd_rx_on_2}; - 8'h35: up_rdata <= {8'h0, up_tdd_rx_off_2}; - 8'h36: up_rdata <= {8'h0, up_tdd_tx_on_2}; - 8'h37: up_rdata <= {8'h0, up_tdd_tx_off_2}; - 8'h38: up_rdata <= {8'h0, up_tdd_tx_dp_on_2}; - 8'h39: up_rdata <= {8'h0, up_tdd_tx_dp_off_2}; + 8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1}; + 8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1}; + 8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1}; + 8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1}; + 8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1}; + 8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1}; + 8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1}; + 8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1}; + 8'h28: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1}; + 8'h29: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1}; + 8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2}; + 8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2}; + 8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2}; + 8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2}; + 8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2}; + 8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2}; + 8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2}; + 8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2}; + 8'h38: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2}; + 8'h39: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2}; default: up_rdata <= 32'h0; endcase end @@ -342,13 +357,15 @@ module up_tdd_cntrl ( // rf tdd control signal CDC - up_xfer_cntrl #(.DATA_WIDTH(12)) i_tdd_control ( + up_xfer_cntrl #(.DATA_WIDTH(14)) i_tdd_control ( .up_rstn(up_rstn), .up_clk(up_clk), .up_data_cntrl({up_tdd_enable, up_tdd_secondary, up_tdd_rx_only, up_tdd_tx_only, + up_tdd_gated_rx_dmapath, + up_tdd_gated_tx_dmapath, up_tdd_burst_count }), .up_xfer_done(), @@ -358,6 +375,8 @@ module up_tdd_cntrl ( tdd_secondary, tdd_rx_only, tdd_tx_only, + tdd_gated_rx_dmapath, + tdd_gated_tx_dmapath, tdd_burst_count }));