diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl
index 9ced421ff..13ee97701 100644
--- a/projects/m2k/common/m2k_bd.tcl
+++ b/projects/m2k/common/m2k_bd.tcl
@@ -93,7 +93,7 @@ ad_connect data_o     logic_analyzer/data_o
 ad_connect data_t     logic_analyzer/data_t
 
 ad_connect sys_cpu_clk            clk_generator/clk
-#ad_connect logic_analyzer/clk_out clk_generator/clk2
+ad_connect logic_analyzer/clk_out clk_generator/clk2
 
 ad_connect logic_analyzer/clk     clk_generator/clk_0
 
diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc
index ab5624d7c..c656c20d9 100644
--- a/projects/m2k/standalone/system_constr.xdc
+++ b/projects/m2k/standalone/system_constr.xdc
@@ -68,6 +68,15 @@ create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}]
 create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
 create_clock -name clk_fpga_1 -period  5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
 
+set_clock_groups -name exclusive_ -physically_exclusive \
+-group  [get_clocks mmcm_clk_0_s_1] -group  [get_clocks mmcm_clk_0_s_2] -group [get_clocks mmcm_clk_0_s]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {i_system_wrapper/system_i/logic_analyzer/inst/i_registers/i_xfer_cntrl/Q[95]}]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets trigger_bd_IOBUF[0]_inst/O]
+
+set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}]
+set_false_path -from [get_clocks trigger_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/trigger_m1_reg[0]/D}]
+
 set_input_jitter clk_fpga_0 0.3
 set_input_jitter clk_fpga_1 0.15
 
diff --git a/projects/m2k/zed/system_constr.xdc b/projects/m2k/zed/system_constr.xdc
index c5456a764..da50ec963 100644
--- a/projects/m2k/zed/system_constr.xdc
+++ b/projects/m2k/zed/system_constr.xdc
@@ -63,3 +63,8 @@ create_clock -name rx_clk       -period   10.00 [get_ports rx_clk]
 create_clock -name trigger_clk  -period   12.5  [get_ports trigger_bd[0]]
 create_clock -name data_clk     -period   12.5  [get_ports data_bd[0]]
 
+set_clock_groups -name exclusive_ -physically_exclusive \
+-group  [get_clocks mmcm_clk_0_s_1] -group  [get_clocks mmcm_clk_0_s_2] -group [get_clocks mmcm_clk_0_s_3]
+
+set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}]
+set_false_path -from [get_clocks trigger_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/trigger_m1_reg[0]/D}]