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axi_adc_trigger: Add holdoff support 

Add reset pin for holdoff.
main
AndreiGrozav 2019-03-14 07:24:57 +00:00 committed by AndreiGrozav
parent a06c74edc7
commit ede19a3b3d
3 changed files with 45 additions and 8 deletions
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41
library/axi_adc_trigger/axi_adc_trigger.v
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@ -45,6 +45,7 @@ module axi_adc_trigger #(
// interface
input clk,
input reset,
input trigger_in,
@ -127,6 +128,8 @@ module axi_adc_trigger #(
wire [16:0] trigger_out_control;
wire [31:0] trigger_delay;
wire [31:0] trigger_holdoff;
wire signed [DW:0] data_a_cmp;
wire signed [DW:0] data_b_cmp;
wire signed [DW:0] limit_a_cmp;
@ -146,6 +149,8 @@ module axi_adc_trigger #(
wire trigger_b_any_edge;
wire trigger_out_delayed;
wire [ 1:0] trigger_up_o_s;
wire trigger_out_holdoff;
wire holdoff_cnt_en;
wire streaming;
wire trigger_out_s;
wire embedded_trigger;
@ -195,7 +200,8 @@ module axi_adc_trigger #(
reg up_triggered_reset_d1;
reg up_triggered_reset_d2;
reg [31:0] trigger_delay_counter;
reg [31:0] trigger_delay_counter = 32'h0;
reg [31:0] trigger_holdoff_counter = 32'h0;
reg triggered;
reg trigger_out_m1;
reg trigger_out_m2;
@ -299,21 +305,23 @@ module axi_adc_trigger #(
end
assign embedded_trigger = trigger_out_control[16];
assign trigger_out_s = (trigger_delay == 32'h0) ? (trigger_out_mixed | streaming_on) :
(trigger_out_delayed | streaming_on);
assign trigger_out_s = (trigger_delay == 32'h0) ? (trigger_out_holdoff | streaming_on) :
(trigger_out_delayed | streaming_on);
assign trigger_out_delayed = (trigger_delay_counter == 32'h0) ? 1 : 0;
// delay out trigger
always @(posedge clk) begin
if (trigger_delay == 0) begin
trigger_delay_counter <= 32'h0;
end else begin
if (data_valid_a == 1'b1) begin
triggered <= trigger_out_mixed | triggered;
triggered <= trigger_out_holdoff | triggered;
if (trigger_delay_counter == 0) begin
trigger_delay_counter <= trigger_delay;
triggered <= 1'b0;
end else begin
if(triggered == 1'b1 || trigger_out_mixed == 1'b1) begin
if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin
trigger_delay_counter <= trigger_delay_counter - 1;
end
end
@ -321,9 +329,10 @@ module axi_adc_trigger #(
end
end
always @(posedge clk) begin
if (trigger_delay == 0) begin
if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_mixed == 1'b1) begin
if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
@ -337,8 +346,25 @@ module axi_adc_trigger #(
end
end
// hold off trigger
assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_mixed;
always @(posedge clk) begin
if (data_valid_a == 1'b1 && trigger_out_mixed == 1'b1) begin
if (reset == 1'b1) begin
trigger_holdoff_counter <= 0;
end else begin
if (trigger_holdoff_counter != 0) begin
trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1;
end else if (trigger_out_holdoff == 1'b1) begin
trigger_holdoff_counter <= trigger_holdoff;
end else begin
trigger_holdoff_counter <= trigger_holdoff_counter;
end
end
end
always @(posedge clk) begin
if (data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin
up_triggered_set <= 1'b1;
end else if (up_triggered_reset == 1'b1) begin
up_triggered_set <= 1'b0;
@ -522,6 +548,7 @@ module axi_adc_trigger #(
.trigger_out_control(trigger_out_control),
.trigger_delay(trigger_delay),
.trigger_holdoff (trigger_holdoff),
.fifo_depth(fifo_depth),

1
library/axi_adc_trigger/axi_adc_trigger_ip.tcl
View File

@ -15,6 +15,7 @@ adi_ip_files axi_adc_trigger [list \
adi_ip_properties axi_adc_trigger
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]

11
library/axi_adc_trigger/axi_adc_trigger_reg.v
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@ -62,6 +62,7 @@ module axi_adc_trigger_reg (
output [16:0] trigger_out_control,
output [31:0] fifo_depth,
output [31:0] trigger_delay,
output [31:0] trigger_holdoff,
output streaming,
@ -100,6 +101,7 @@ module axi_adc_trigger_reg (
reg [16:0] up_trigger_out_control = 17'h0;
reg [31:0] up_fifo_depth = 32'h0;
reg [31:0] up_trigger_delay = 32'h0;
reg [31:0] up_trigger_holdoff = 32'h0;
reg up_triggered = 1'h0;
reg up_streaming = 1'h0;
@ -129,6 +131,7 @@ module axi_adc_trigger_reg (
up_trigger_out_control <= 'd0;
up_triggered <= 1'd0;
up_streaming <= 1'd0;
up_trigger_holdoff <= 32'h0;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@ -184,6 +187,9 @@ module axi_adc_trigger_reg (
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_streaming <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_trigger_holdoff <= up_wdata[31:0];
end
end
end
@ -215,6 +221,7 @@ module axi_adc_trigger_reg (
5'hf: up_rdata <= {31'h0,up_triggered};
5'h10: up_rdata <= up_trigger_delay;
5'h11: up_rdata <= {31'h0,up_streaming};
5'h12: up_rdata <= up_trigger_holdoff;
default: up_rdata <= 0;
endcase
end else begin
@ -223,7 +230,7 @@ module axi_adc_trigger_reg (
end
end
up_xfer_cntrl #(.DATA_WIDTH(210)) i_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(242)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_streaming, // 1
@ -240,6 +247,7 @@ module axi_adc_trigger_reg (
up_trigger_l_mix_b, // 4
up_trigger_out_control, // 17
up_fifo_depth, // 32
up_trigger_holdoff, // 32
up_trigger_delay}), // 32
.up_xfer_done (),
@ -259,6 +267,7 @@ module axi_adc_trigger_reg (
trigger_l_mix_b, // 4
trigger_out_control,// 17
fifo_depth, // 32
trigger_holdoff, // 32
trigger_delay})); // 32
endmodule