From ee30c6492356ce376a015e10f18e36e2c4209c77 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Fri, 6 May 2022 14:08:39 +0100 Subject: [PATCH] projects/ad4134_fmc: Initial commit add support * Updated reference design: spi trigger, ODR parameters - enabled ext_clk for PWM to use 96 MHz spi clk - mofified PWM channels used: - ch1: ODR - 850 ns period, 130 ns high time ==> max fODR = 1.18 MHz - ch0: trigger - 850 ns period, 30 phase shift ==> 10 ns between falling ODR rising DCLK - spi offload trigger signal: PWM trigger used * Moved mem_interconnect to hp1 * Added dclkio GPIO * Updated bd SPIE hierarchy, see library/spi_engine.tcl Signed-off-by: laurent-19 --- projects/ad4134_fmc/Makefile | 7 + projects/ad4134_fmc/Readme.md | 8 + projects/ad4134_fmc/common/ad4134_bd.tcl | 85 +++++++ projects/ad4134_fmc/zed/Makefile | 30 +++ projects/ad4134_fmc/zed/system_bd.tcl | 20 ++ projects/ad4134_fmc/zed/system_constr.xdc | 33 +++ projects/ad4134_fmc/zed/system_project.tcl | 15 ++ projects/ad4134_fmc/zed/system_top.v | 248 +++++++++++++++++++++ 8 files changed, 446 insertions(+) create mode 100644 projects/ad4134_fmc/Makefile create mode 100644 projects/ad4134_fmc/Readme.md create mode 100644 projects/ad4134_fmc/common/ad4134_bd.tcl create mode 100755 projects/ad4134_fmc/zed/Makefile create mode 100755 projects/ad4134_fmc/zed/system_bd.tcl create mode 100755 projects/ad4134_fmc/zed/system_constr.xdc create mode 100755 projects/ad4134_fmc/zed/system_project.tcl create mode 100755 projects/ad4134_fmc/zed/system_top.v diff --git a/projects/ad4134_fmc/Makefile b/projects/ad4134_fmc/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/ad4134_fmc/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad4134_fmc/Readme.md b/projects/ad4134_fmc/Readme.md new file mode 100644 index 000000000..b286fac9d --- /dev/null +++ b/projects/ad4134_fmc/Readme.md @@ -0,0 +1,8 @@ +# AD4134 HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/AD4134) + * Parts: [24-Bit, 4-Channel Simultaneous Sampling 1.5 MSPS Precision Alias Free ADC](https://www.analog.com/ad4134) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/ad4134 + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad4134/hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all diff --git a/projects/ad4134_fmc/common/ad4134_bd.tcl b/projects/ad4134_fmc/common/ad4134_bd.tcl new file mode 100644 index 000000000..a4166bbcb --- /dev/null +++ b/projects/ad4134_fmc/common/ad4134_bd.tcl @@ -0,0 +1,85 @@ + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad4134_di +create_bd_port -dir O ad4134_odr + +# create a SPI Engine architecture for ADC + +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + +if {$adc_resolution == 16} { + set data_width 24 +} elseif {$adc_resolution == 24} { + set data_width 32 +} elseif {$adc_resolution == 32} { + set data_width 64 +}; + +set async_spi_clk 1 +set num_cs 1 +set num_sdi $adc_num_of_channels +set num_sdo 0 +set sdi_delay 0 +set echo_sclk 0 + +set hier_spi_engine spi_ad4134 + +spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk + +# clkgen + +ad_ip_instance axi_clkgen axi_ad4134_clkgen +ad_ip_parameter axi_ad4134_clkgen CONFIG.VCO_DIV 5 +ad_ip_parameter axi_ad4134_clkgen CONFIG.VCO_MUL 48 +ad_ip_parameter axi_ad4134_clkgen CONFIG.CLK0_DIV 10 + +# dma to receive data stream + +ad_ip_instance axi_dmac axi_ad4134_dma +ad_ip_parameter axi_ad4134_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_ad4134_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad4134_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad4134_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad4134_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $adc_num_of_channels] +ad_ip_parameter axi_ad4134_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +# odr generator + +ad_ip_instance axi_pwm_gen odr_generator +ad_ip_parameter odr_generator CONFIG.N_PWMS 2 +ad_ip_parameter odr_generator CONFIG.PULSE_0_PERIOD 85 +ad_ip_parameter odr_generator CONFIG.PULSE_0_WIDTH 1 +ad_ip_parameter odr_generator CONFIG.PULSE_0_OFFSET 3 +ad_ip_parameter odr_generator CONFIG.PULSE_1_PERIOD 85 +ad_ip_parameter odr_generator CONFIG.PULSE_1_WIDTH 13 + +ad_connect odr_generator/ext_clk axi_ad4134_clkgen/clk_0 +ad_connect odr_generator/pwm_0 $hier_spi_engine/trigger +ad_connect odr_generator/pwm_1 ad4134_odr + +ad_connect axi_ad4134_clkgen/clk_0 $hier_spi_engine/spi_clk +ad_connect $sys_cpu_clk axi_ad4134_clkgen/clk +ad_connect $sys_cpu_clk $hier_spi_engine/clk +ad_connect axi_ad4134_clkgen/clk_0 axi_ad4134_dma/s_axis_aclk +ad_connect sys_cpu_resetn $hier_spi_engine/resetn +ad_connect sys_cpu_resetn axi_ad4134_dma/m_dest_axi_aresetn + +ad_connect $hier_spi_engine/m_spi ad4134_di +ad_connect axi_ad4134_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE + +# AXI address definitions + +ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap +ad_cpu_interconnect 0x44a30000 axi_ad4134_dma +ad_cpu_interconnect 0x44b00000 odr_generator +ad_cpu_interconnect 0x44b10000 axi_ad4134_clkgen + +# interrupts + +ad_cpu_interrupt "ps-13" "mb-13" axi_ad4134_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq + +# memory interconnects + +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_cpu_clk axi_ad4134_dma/m_dest_axi diff --git a/projects/ad4134_fmc/zed/Makefile b/projects/ad4134_fmc/zed/Makefile new file mode 100755 index 000000000..f2f6de174 --- /dev/null +++ b/projects/ad4134_fmc/zed/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad4134_fmc_zed + +M_DEPS += ../common/ad4134_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad4134_fmc/zed/system_bd.tcl b/projects/ad4134_fmc/zed/system_bd.tcl new file mode 100755 index 000000000..6037a77f0 --- /dev/null +++ b/projects/ad4134_fmc/zed/system_bd.tcl @@ -0,0 +1,20 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# specify ADC resolution -- the design supports 16/24/32 bit resolutions + +set adc_resolution 24 + +# ADC number of channels + +set adc_num_of_channels 4 + +source ../common/ad4134_bd.tcl diff --git a/projects/ad4134_fmc/zed/system_constr.xdc b/projects/ad4134_fmc/zed/system_constr.xdc new file mode 100755 index 000000000..1b4f32e92 --- /dev/null +++ b/projects/ad4134_fmc/zed/system_constr.xdc @@ -0,0 +1,33 @@ + +# ad4134 SPI configuration interface + +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdi] ; ## FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sdo] ; ## FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_sclk] ; ## FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports ad4134_spi_cs] ; ## FMC_LPC_LA05_P + +# ad4134 data interface + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad4134_dclk] ; ## FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad4134_din[0]] ; ## FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports ad4134_din[1]] ; ## FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad4134_din[2]] ; ## FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad4134_din[3]] ; ## FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad4134_odr] ; ## FMC_LPC_LA00_CC_P + +# ad4134 GPIO lines + +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports ad4134_resetn] ; ## FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports ad4134_pdn] ; ## FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad4134_mode] ; ## FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio0] ; ## FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio1] ; ## FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio2] ; ## FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio3] ; ## FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio4] ; ## FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio5] ; ## FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio6] ; ## FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports ad4134_gpio7] ; ## FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad4134_pinbspi] ; ## FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports ad4134_dclkio] ; ## FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports ad4134_dclk_mode] ; ## FMC_LPC_LA14_N diff --git a/projects/ad4134_fmc/zed/system_project.tcl b/projects/ad4134_fmc/zed/system_project.tcl new file mode 100755 index 000000000..760947b9c --- /dev/null +++ b/projects/ad4134_fmc/zed/system_project.tcl @@ -0,0 +1,15 @@ + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad4134_fmc_zed + +adi_project_files ad4134_fmc_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run ad4134_fmc_zed + diff --git a/projects/ad4134_fmc/zed/system_top.v b/projects/ad4134_fmc/zed/system_top.v new file mode 100755 index 000000000..6d20e2406 --- /dev/null +++ b/projects/ad4134_fmc/zed/system_top.v @@ -0,0 +1,248 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // ad4134 SPI configuration interface + + input ad4134_spi_sdi, + output ad4134_spi_sdo, + output ad4134_spi_sclk, + output ad4134_spi_cs, + + // ad4134 data interface + + output ad4134_dclk, + input [ 3:0] ad4134_din, + output ad4134_odr, + + // ad4134 GPIO lines + + inout ad4134_resetn, + inout ad4134_pdn, + inout ad4134_mode, + inout ad4134_pinbspi, + inout ad4134_gpio0, + inout ad4134_gpio1, + inout ad4134_gpio2, + inout ad4134_gpio3, + inout ad4134_gpio4, + inout ad4134_gpio5, + inout ad4134_gpio6, + inout ad4134_gpio7, + inout ad4134_dclk_mode, + inout ad4134_dclkio +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] ii_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire ii5c_mux_sda_t_s; + + // instantiations + + assign gpio_i[63:46] = gpio_o[63:46]; + ad_iobuf #( + .DATA_WIDTH(14) + ) i_iobuf_ad4134_gpio ( + .dio_t(gpio_t[45:32]), + .dio_i(gpio_o[45:32]), + .dio_o(gpio_i[45:32]), + .dio_p({ad4134_dclkio, // [45] + ad4134_dclk_mode, // [44] + ad4134_gpio7, // [43] + ad4134_gpio6, // [42] + ad4134_gpio5, // [41] + ad4134_gpio4, // [40] + ad4134_gpio3, // [39] + ad4134_gpio2, // [38] + ad4134_gpio1, // [37] + ad4134_gpio0, // [36] + ad4134_pinbspi, // [35] + ad4134_mode, // [34] + ad4134_pdn, // [33] + ad4134_resetn})); // [32] + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .spi0_clk_i (ad4134_spi_sclk), + .spi0_clk_o (ad4134_spi_sclk), + .spi0_csn_0_o (ad4134_spi_cs), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (ad4134_spi_sdi), + .spi0_sdo_i (ad4134_spi_sdo), + .spi0_sdo_o (ad4134_spi_sdo), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .ad4134_di_sdo (), + .ad4134_di_sdo_t (), + .ad4134_di_sdi (ad4134_din), + .ad4134_di_cs (), + .ad4134_di_sclk (ad4134_dclk), + .ad4134_odr (ad4134_odr), + .ad4134_di_three_wire (), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule