axi_jesd204: Cleanup unused parameter
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a1d31b4913
commit
ee3af4c9c6
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@ -44,9 +44,7 @@
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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module jesd204_up_sysref #(
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module jesd204_up_sysref (
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parameter DATA_PATH_WIDTH_LOG2 = 2
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) (
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input up_clk,
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input up_clk,
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input up_reset,
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input up_reset,
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@ -130,8 +130,6 @@ module axi_jesd204_rx #(
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localparam PCORE_VERSION = 32'h00010761; // 1.07.a
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localparam PCORE_VERSION = 32'h00010761; // 1.07.a
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localparam PCORE_MAGIC = 32'h32303452; // 204R
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localparam PCORE_MAGIC = 32'h32303452; // 204R
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localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
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/* Register interface signals */
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/* Register interface signals */
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reg [31:0] up_rdata = 'h0;
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reg [31:0] up_rdata = 'h0;
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reg up_wack = 1'b0;
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reg up_wack = 1'b0;
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@ -279,9 +277,7 @@ module axi_jesd204_rx #(
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.status_synth_params1(status_synth_params1),
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.status_synth_params1(status_synth_params1),
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.status_synth_params2(status_synth_params2));
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.status_synth_params2(status_synth_params2));
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jesd204_up_sysref #(
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jesd204_up_sysref i_up_sysref (
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.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
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) i_up_sysref (
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.up_clk(s_axi_aclk),
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.up_clk(s_axi_aclk),
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.up_reset(up_reset),
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.up_reset(up_reset),
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@ -304,8 +300,7 @@ module axi_jesd204_rx #(
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jesd204_up_rx #(
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jesd204_up_rx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LANES(NUM_LANES),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
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) i_up_rx (
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) i_up_rx (
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.up_clk(s_axi_aclk),
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.up_clk(s_axi_aclk),
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.up_reset(up_reset),
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.up_reset(up_reset),
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@ -46,8 +46,7 @@
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module jesd204_up_rx #(
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module jesd204_up_rx #(
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parameter NUM_LANES = 1,
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parameter NUM_LANES = 1,
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parameter DATA_PATH_WIDTH = 4,
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parameter DATA_PATH_WIDTH = 4
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parameter DATA_PATH_WIDTH_LOG2 = 2
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) (
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) (
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input up_clk,
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input up_clk,
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input up_reset,
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input up_reset,
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@ -122,8 +122,6 @@ module axi_jesd204_tx #(
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localparam PCORE_VERSION = 32'h00010661; // 1.06.a
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localparam PCORE_VERSION = 32'h00010661; // 1.06.a
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localparam PCORE_MAGIC = 32'h32303454; // 204T
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localparam PCORE_MAGIC = 32'h32303454; // 204T
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localparam DATA_PATH_WIDTH_LOG2 = (DATA_PATH_WIDTH == 8) ? 3 : 2;
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wire up_reset;
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wire up_reset;
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/* Register interface signals */
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/* Register interface signals */
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@ -259,9 +257,7 @@ module axi_jesd204_tx #(
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.status_synth_params1(status_synth_params1),
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.status_synth_params1(status_synth_params1),
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.status_synth_params2(status_synth_params2));
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.status_synth_params2(status_synth_params2));
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jesd204_up_sysref #(
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jesd204_up_sysref i_up_sysref (
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.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2)
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) i_up_sysref (
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.up_clk(s_axi_aclk),
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.up_clk(s_axi_aclk),
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.up_reset(up_reset),
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.up_reset(up_reset),
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