daq1: Initial commit
Istvan Csomortani
parent
a773cc4992
commit
ee752ec08a
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@ -0,0 +1,283 @@
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# daq1
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set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o]
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
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set rx_sync [create_bd_port -dir O rx_sync]
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set rx_sysref [create_bd_port -dir I rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n]
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set adc_clk [create_bd_port -dir O adc_clk]
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set adc_enable_a [create_bd_port -dir O adc_enable_a]
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set adc_valid_a [create_bd_port -dir O adc_valid_a]
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set adc_data_a [create_bd_port -dir O -from 31 -to 0 adc_data_a]
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set adc_enable_b [create_bd_port -dir O adc_enable_b]
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set adc_valid_b [create_bd_port -dir O adc_valid_b]
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set adc_data_b [create_bd_port -dir O -from 31 -to 0 adc_data_b]
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set dma_wr [create_bd_port -dir I dma_wr]
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set dma_sync [create_bd_port -dir I dma_sync]
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set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data]
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set tx_ref_clk_p [create_bd_port -dir I tx_ref_clk_p]
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set tx_ref_clk_n [create_bd_port -dir I tx_ref_clk_n]
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set tx_clk_p [create_bd_port -dir O tx_clk_p]
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set tx_clk_n [create_bd_port -dir O tx_clk_n]
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set tx_frame_p [create_bd_port -dir O tx_frame_p]
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set tx_frame_n [create_bd_port -dir O tx_frame_n]
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set tx_data_p [create_bd_port -dir O -from 15 -to 0 tx_data_p]
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set tx_data_n [create_bd_port -dir O -from 15 -to 0 tx_data_n]
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# dac peripherals
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set axi_ad9122_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core]
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set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
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set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9122_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
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set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9122_dma_interconnect
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# adc peripherals
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set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core]
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set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9250_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd
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set axi_ad9250_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma
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set axi_ad9250_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9250_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9250_dma_interconnect
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# dac/adc common gt/gpio
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set axi_daq1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq1_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {2}] [get_bd_cells axi_daq1_gt]
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set axi_daq1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq1_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq1_gt_interconnect
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# additions to default configuration
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set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {40}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property LEFT 39 [get_bd_ports GPIO_I]
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set_property LEFT 39 [get_bd_ports GPIO_O]
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set_property LEFT 39 [get_bd_ports GPIO_T]
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# connections (spi)
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set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat]
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set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat
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connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O]
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connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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# connections (gt)
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connect_bd_net -net axi_daq1_gt_ref_clk_q [get_bd_pins axi_daq1_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_daq1_gt_rx_data_p [get_bd_pins axi_daq1_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_daq1_gt_rx_data_n [get_bd_pins axi_daq1_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_daq1_gt_rx_sync [get_bd_pins axi_daq1_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_daq1_gt_rx_ext_sysref [get_bd_pins axi_daq1_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
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# connections (adc)
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk_g]
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk]
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_ad9250_core/rx_clk]
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_ad9250_jesd/rx_core_clk]
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connect_bd_net -net axi_daq1_gt_rx_rst [get_bd_pins axi_daq1_gt/rx_rst] [get_bd_pins axi_ad9250_jesd/rx_reset]
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connect_bd_net -net axi_daq1_gt_rx_sysref [get_bd_pins axi_daq1_gt/rx_sysref] [get_bd_pins axi_ad9250_jesd/rx_sysref]
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connect_bd_net -net axi_daq1_gt_rx_gt_charisk [get_bd_pins axi_daq1_gt/rx_gt_charisk] [get_bd_pins axi_ad9250_jesd/gt_rxcharisk_in]
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connect_bd_net -net axi_daq1_gt_rx_gt_disperr [get_bd_pins axi_daq1_gt/rx_gt_disperr] [get_bd_pins axi_ad9250_jesd/gt_rxdisperr_in]
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connect_bd_net -net axi_daq1_gt_rx_gt_notintable [get_bd_pins axi_daq1_gt/rx_gt_notintable] [get_bd_pins axi_ad9250_jesd/gt_rxnotintable_in]
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connect_bd_net -net axi_daq1_gt_rx_gt_data [get_bd_pins axi_daq1_gt/rx_gt_data] [get_bd_pins axi_ad9250_jesd/gt_rxdata_in]
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connect_bd_net -net axi_daq1_gt_rx_rst_done [get_bd_pins axi_daq1_gt/rx_rst_done] [get_bd_pins axi_ad9250_jesd/rx_reset_done]
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connect_bd_net -net axi_daq1_gt_rx_ip_comma_align [get_bd_pins axi_daq1_gt/rx_ip_comma_align] [get_bd_pins axi_ad9250_jesd/rxencommaalign_out]
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connect_bd_net -net axi_daq1_gt_rx_ip_sync [get_bd_pins axi_daq1_gt/rx_ip_sync] [get_bd_pins axi_ad9250_jesd/rx_sync]
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connect_bd_net -net axi_daq1_gt_rx_ip_sof [get_bd_pins axi_daq1_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame]
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connect_bd_net -net axi_daq1_gt_rx_ip_data [get_bd_pins axi_daq1_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata]
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connect_bd_net -net axi_daq1_gt_rx_data [get_bd_pins axi_daq1_gt/rx_data] [get_bd_pins axi_ad9250_core/rx_data]
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connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk]
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connect_bd_net -net axi_ad9250_adc_enable_a [get_bd_pins axi_ad9250_core/adc_enable_a] [get_bd_ports adc_enable_a]
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connect_bd_net -net axi_ad9250_adc_valid_a [get_bd_pins axi_ad9250_core/adc_valid_a] [get_bd_ports adc_valid_a]
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connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/adc_data_a] [get_bd_ports adc_data_a]
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connect_bd_net -net axi_ad9250_adc_enable_b [get_bd_pins axi_ad9250_core/adc_enable_b] [get_bd_ports adc_enable_b]
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connect_bd_net -net axi_ad9250_adc_valid_b [get_bd_pins axi_ad9250_core/adc_valid_b] [get_bd_ports adc_valid_b]
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connect_bd_net -net axi_ad9250_adc_data_b [get_bd_pins axi_ad9250_core/adc_data_b] [get_bd_ports adc_data_b]
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connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports dma_wr]
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connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports dma_sync]
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connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports dma_data]
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connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2]
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# connections (dac)
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connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_pins axi_ad9122_core/dac_clk_in_p] [get_bd_ports tx_ref_clk_p]
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connect_bd_net -net axi_ad9122_dac_clk_in_n [get_bd_pins axi_ad9122_core/dac_clk_in_n] [get_bd_ports tx_ref_clk_n]
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connect_bd_net -net axi_ad9122_dac_clk_out_p [get_bd_pins axi_ad9122_core/dac_clk_out_p] [get_bd_ports tx_clk_p]
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connect_bd_net -net axi_ad9122_dac_clk_out_n [get_bd_pins axi_ad9122_core/dac_clk_out_n] [get_bd_ports tx_clk_n]
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connect_bd_net -net axi_ad9122_dac_frame_out_p [get_bd_pins axi_ad9122_core/dac_frame_out_p] [get_bd_ports tx_frame_p]
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connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_pins axi_ad9122_core/dac_frame_out_n] [get_bd_ports tx_frame_n]
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connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_pins axi_ad9122_core/dac_data_out_p] [get_bd_ports tx_data_p]
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connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_pins axi_ad9122_core/dac_data_out_n] [get_bd_ports tx_data_n]
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connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_pins axi_ad9122_core/dac_div_clk] [get_bd_pins axi_ad9122_dma/fifo_rd_clk]
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connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122_core/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en]
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connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122_core/dac_ddata] [get_bd_pins axi_ad9122_dma/fifo_rd_dout]
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connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
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connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
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# interconnect (cpu)
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9122_core/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9250_dma/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9250_core/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9250_jesd/s_axi]
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_daq1_gt/s_axi]
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||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq1_gt/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122_core/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122_dma/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_core/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_jesd/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_dma/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq1_gt/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_core/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_core/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_jesd/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_dma/s_axi_aresetn]
|
||||||
|
|
||||||
|
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_daq1_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq1_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||||
|
connect_bd_intf_net -intf_net axi_daq1_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq1_gt/m_axi]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq1_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq1_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq1_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq1_gt/m_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq1_gt/drp_clk]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq1_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq1_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq1_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq1_gt/m_axi_aresetn]
|
||||||
|
|
||||||
|
# memory interconnects share the same clock (fclk2)
|
||||||
|
|
||||||
|
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
|
||||||
|
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
|
||||||
|
|
||||||
|
# interconnect (mem/dac)
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
|
||||||
|
connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||||
|
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9250_dma/m_dest_axi]
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
|
||||||
|
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma/m_dest_axi_aclk]
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||||
|
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma/m_dest_axi_aresetn]
|
||||||
|
|
||||||
|
# ila
|
||||||
|
|
||||||
|
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
|
||||||
|
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon
|
||||||
|
set_property -dict [list CONFIG.C_PROBE0_WIDTH {170}] $ila_jesd_rx_mon
|
||||||
|
set_property -dict [list CONFIG.C_PROBE1_WIDTH {4}] $ila_jesd_rx_mon
|
||||||
|
|
||||||
|
connect_bd_net -net axi_daq1_gt_rx_mon_data [get_bd_pins axi_daq1_gt/rx_mon_data]
|
||||||
|
connect_bd_net -net axi_daq1_gt_rx_mon_trigger [get_bd_pins axi_daq1_gt/rx_mon_trigger]
|
||||||
|
connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||||
|
connect_bd_net -net axi_daq1_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||||
|
connect_bd_net -net axi_daq1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||||
|
|
||||||
|
# address mapping
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9122_core/s_axi/axi_lite] SEG_data_ad9122_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9122_dma
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9250_core/s_axi/axi_lite] SEG_data_ad9250_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9250_dma/s_axi/axi_lite] SEG_data_ad9250_dma
|
||||||
|
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9250_jesd/s_axi/Reg] SEG_data_ad9250_jesd
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_daq1_gt/s_axi/axi_lite] SEG_data_daq1_gt
|
||||||
|
|
||||||
|
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||||
|
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||||
|
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq1_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||||
|
|
@ -0,0 +1,111 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module daq1_spi (
|
||||||
|
|
||||||
|
spi_csn,
|
||||||
|
spi_clk,
|
||||||
|
spi_mosi,
|
||||||
|
spi_miso,
|
||||||
|
|
||||||
|
spi_sdio);
|
||||||
|
|
||||||
|
// 4 wire
|
||||||
|
|
||||||
|
input [ 2:0] spi_csn;
|
||||||
|
input spi_clk;
|
||||||
|
input spi_mosi;
|
||||||
|
output spi_miso;
|
||||||
|
|
||||||
|
// 3 wire
|
||||||
|
|
||||||
|
inout spi_sdio;
|
||||||
|
|
||||||
|
// internal registers
|
||||||
|
|
||||||
|
reg [ 5:0] spi_count = 'd0;
|
||||||
|
reg spi_rd_wr_n = 'd0;
|
||||||
|
reg spi_enable = 'd0;
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire spi_csn_s;
|
||||||
|
wire spi_enable_s;
|
||||||
|
|
||||||
|
// check on rising edge and change on falling edge
|
||||||
|
|
||||||
|
assign spi_csn_s = & spi_csn;
|
||||||
|
assign spi_enable_s = spi_enable & ~spi_csn_s;
|
||||||
|
|
||||||
|
always @(posedge spi_clk or posedge spi_csn_s) begin
|
||||||
|
if (spi_csn_s == 1'b1) begin
|
||||||
|
spi_count <= 6'd0;
|
||||||
|
spi_rd_wr_n <= 1'd0;
|
||||||
|
end else begin
|
||||||
|
spi_count <= spi_count + 1'b1;
|
||||||
|
if (spi_count == 6'd0) begin
|
||||||
|
spi_rd_wr_n <= spi_mosi;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(negedge spi_clk or posedge spi_csn_s) begin
|
||||||
|
if (spi_csn_s == 1'b1) begin
|
||||||
|
spi_enable <= 1'b0;
|
||||||
|
end else begin
|
||||||
|
if (((spi_count == 6'd16) && (spi_csn[2] == 1'b0)) ||
|
||||||
|
((spi_count == 6'd8) && (spi_csn[1] == 1'b0)) ||
|
||||||
|
((spi_count == 6'd16) && (spi_csn[0] == 1'b0))) begin
|
||||||
|
spi_enable <= spi_rd_wr_n;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// io butter
|
||||||
|
|
||||||
|
IOBUF i_iobuf_sdio (
|
||||||
|
.T (spi_enable_s),
|
||||||
|
.I (spi_mosi),
|
||||||
|
.O (spi_miso),
|
||||||
|
.IO (spi_sdio));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
|
||||||
|
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
|
||||||
|
source ../common/daq1_bd.tcl
|
||||||
|
|
||||||
|
|
@ -0,0 +1,81 @@
|
||||||
|
|
||||||
|
# daq1
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25} [get_ports tx_ref_clk_p] ; ## G06 FMC_HPC_LA00_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25} [get_ports tx_ref_clk_n] ; ## G07 FMC_HPC_LA00_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports tx_clk_p] ; ## D20 FMC_HPC_LA17_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports tx_clk_n] ; ## D21 FMC_HPC_LA17_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25} [get_ports tx_frame_p] ; ## C22 FMC_HPC_LA18_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS_25} [get_ports tx_frame_n] ; ## C23 FMC_HPC_LA18_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports tx_data_p[0]] ; ## H10 FMC_HPC_LA04_P
|
||||||
|
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports tx_data_n[0]] ; ## H11 FMC_HPC_LA04_N
|
||||||
|
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25} [get_ports tx_data_p[1]] ; ## D11 FMC_HPC_LA05_P
|
||||||
|
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25} [get_ports tx_data_n[1]] ; ## D12 FMC_HPC_LA05_N
|
||||||
|
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25} [get_ports tx_data_p[2]] ; ## C10 FMC_HPC_LA06_P
|
||||||
|
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25} [get_ports tx_data_n[2]] ; ## C11 FMC_HPC_LA06_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports tx_data_p[3]] ; ## H13 FMC_HPC_LA07_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports tx_data_n[3]] ; ## H14 FMC_HPC_LA07_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVDS_25} [get_ports tx_data_p[4]] ; ## G12 FMC_HPC_LA08_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS_25} [get_ports tx_data_n[4]] ; ## G13 FMC_HPC_LA08_N
|
||||||
|
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_data_p[5]] ; ## D14 FMC_HPC_LA09_P
|
||||||
|
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_data_n[5]] ; ## D15 FMC_HPC_LA09_N
|
||||||
|
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVDS_25} [get_ports tx_data_p[6]] ; ## C14 FMC_HPC_LA10_P
|
||||||
|
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25} [get_ports tx_data_n[6]] ; ## C15 FMC_HPC_LA10_N
|
||||||
|
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25} [get_ports tx_data_p[7]] ; ## H16 FMC_HPC_LA11_P
|
||||||
|
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25} [get_ports tx_data_n[7]] ; ## H17 FMC_HPC_LA11_N
|
||||||
|
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports tx_data_p[8]] ; ## G15 FMC_HPC_LA12_P
|
||||||
|
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports tx_data_n[8]] ; ## G16 FMC_HPC_LA12_N
|
||||||
|
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports tx_data_p[9]] ; ## D17 FMC_HPC_LA13_P
|
||||||
|
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports tx_data_n[9]] ; ## D18 FMC_HPC_LA13_N
|
||||||
|
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_p[10]] ; ## C18 FMC_HPC_LA14_P
|
||||||
|
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_n[10]] ; ## C19 FMC_HPC_LA14_N
|
||||||
|
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25} [get_ports tx_data_p[11]] ; ## H19 FMC_HPC_LA15_P
|
||||||
|
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25} [get_ports tx_data_n[11]] ; ## H20 FMC_HPC_LA15_N
|
||||||
|
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVDS_25} [get_ports tx_data_p[12]] ; ## G18 FMC_HPC_LA16_P
|
||||||
|
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25} [get_ports tx_data_n[12]] ; ## G19 FMC_HPC_LA16_N
|
||||||
|
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25} [get_ports tx_data_p[13]] ; ## H07 FMC_HPC_LA02_P
|
||||||
|
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25} [get_ports tx_data_n[13]] ; ## H08 FMC_HPC_LA02_N
|
||||||
|
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports tx_data_p[14]] ; ## D08 FMC_HPC_LA01_CC_P
|
||||||
|
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports tx_data_n[14]] ; ## D09 FMC_HPC_LA01_CC_N
|
||||||
|
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports tx_data_p[15]] ; ## G09 FMC_HPC_LA03_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports tx_data_n[15]] ; ## G10 FMC_HPC_LA03_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN AD10 } [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN AH10 } [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
|
||||||
|
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
|
||||||
|
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H22 FMC_HPC_LA19_P
|
||||||
|
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H23 FMC_HPC_LA19_N
|
||||||
|
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## H25 FMC_HPC_LA21_P
|
||||||
|
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## H26 FMC_HPC_LA21_N
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G28 FMC_HPC_LA25_N
|
||||||
|
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## G27 FMC_HPC_LA25_P
|
||||||
|
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## H29 FMC_HPC_LA24_N
|
||||||
|
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D24 FMC_HPC_LA23_N
|
||||||
|
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D23 FMC_HPC_LA23_P
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports gpio_resetn] ; ## G25 FMC_HPC_LA22_N
|
||||||
|
set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_syncn] ; ## H32 FMC_HPC_LA28_N
|
||||||
|
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_pdn] ; ## H31 FMC_HPC_LA28_P
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[1]] ; ## D27 FMC_HPC_LA26_N
|
||||||
|
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[0]] ; ## D26 FMC_HPC_LA26_P
|
||||||
|
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports gpio_dac_irqn] ; ## G24 FMC_HPC_LA22_P
|
||||||
|
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_adc_fda] ; ## C26 FMC_HPC_LA27_P
|
||||||
|
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_adc_fdb] ; ## C27 FMC_HPC_LA27_N
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
|
||||||
|
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
|
||||||
|
create_clock -name tx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_ad9122_dac_div_clk]
|
||||||
|
create_clock -name rx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_daq1_gt_rx_clk]
|
||||||
|
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
|
||||||
|
|
||||||
|
set_clock_groups -asynchronous -group {tx_div_clk}
|
||||||
|
set_clock_groups -asynchronous -group {rx_div_clk}
|
||||||
|
set_clock_groups -asynchronous -group {fmc_dma_clk}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,17 @@
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
source ../../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||||
|
|
||||||
|
adi_project_create daq1_zc706
|
||||||
|
adi_project_files daq1_zc706 [list \
|
||||||
|
"../common/daq1_spi.v" \
|
||||||
|
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||||
|
"system_top.v" \
|
||||||
|
"system_constr.xdc"\
|
||||||
|
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||||
|
|
||||||
|
adi_project_run daq1_zc706
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,350 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
DDR_addr,
|
||||||
|
DDR_ba,
|
||||||
|
DDR_cas_n,
|
||||||
|
DDR_ck_n,
|
||||||
|
DDR_ck_p,
|
||||||
|
DDR_cke,
|
||||||
|
DDR_cs_n,
|
||||||
|
DDR_dm,
|
||||||
|
DDR_dq,
|
||||||
|
DDR_dqs_n,
|
||||||
|
DDR_dqs_p,
|
||||||
|
DDR_odt,
|
||||||
|
DDR_ras_n,
|
||||||
|
DDR_reset_n,
|
||||||
|
DDR_we_n,
|
||||||
|
|
||||||
|
FIXED_IO_ddr_vrn,
|
||||||
|
FIXED_IO_ddr_vrp,
|
||||||
|
FIXED_IO_mio,
|
||||||
|
FIXED_IO_ps_clk,
|
||||||
|
FIXED_IO_ps_porb,
|
||||||
|
FIXED_IO_ps_srstb,
|
||||||
|
|
||||||
|
gpio_bd,
|
||||||
|
|
||||||
|
hdmi_out_clk,
|
||||||
|
hdmi_vsync,
|
||||||
|
hdmi_hsync,
|
||||||
|
hdmi_data_e,
|
||||||
|
hdmi_data,
|
||||||
|
|
||||||
|
spdif,
|
||||||
|
|
||||||
|
iic_scl,
|
||||||
|
iic_sda,
|
||||||
|
|
||||||
|
rx_ref_clk_p,
|
||||||
|
rx_ref_clk_n,
|
||||||
|
rx_sysref_p,
|
||||||
|
rx_sysref_n,
|
||||||
|
rx_sync_p,
|
||||||
|
rx_sync_n,
|
||||||
|
rx_data_p,
|
||||||
|
rx_data_n,
|
||||||
|
|
||||||
|
tx_ref_clk_p,
|
||||||
|
tx_ref_clk_n,
|
||||||
|
tx_clk_p,
|
||||||
|
tx_clk_n,
|
||||||
|
tx_frame_p,
|
||||||
|
tx_frame_n,
|
||||||
|
tx_data_p,
|
||||||
|
tx_data_n,
|
||||||
|
|
||||||
|
gpio_adc_fdb,
|
||||||
|
gpio_adc_fda,
|
||||||
|
gpio_dac_irqn,
|
||||||
|
gpio_clkd_status,
|
||||||
|
|
||||||
|
gpio_clkd_pdn,
|
||||||
|
gpio_clkd_syncn,
|
||||||
|
gpio_resetn,
|
||||||
|
|
||||||
|
spi_csn_clk,
|
||||||
|
spi_csn_dac,
|
||||||
|
spi_csn_adc,
|
||||||
|
spi_clk,
|
||||||
|
spi_sdio);
|
||||||
|
|
||||||
|
inout [14:0] DDR_addr;
|
||||||
|
inout [ 2:0] DDR_ba;
|
||||||
|
inout DDR_cas_n;
|
||||||
|
inout DDR_ck_n;
|
||||||
|
inout DDR_ck_p;
|
||||||
|
inout DDR_cke;
|
||||||
|
inout DDR_cs_n;
|
||||||
|
inout [ 3:0] DDR_dm;
|
||||||
|
inout [31:0] DDR_dq;
|
||||||
|
inout [ 3:0] DDR_dqs_n;
|
||||||
|
inout [ 3:0] DDR_dqs_p;
|
||||||
|
inout DDR_odt;
|
||||||
|
inout DDR_ras_n;
|
||||||
|
inout DDR_reset_n;
|
||||||
|
inout DDR_we_n;
|
||||||
|
|
||||||
|
inout FIXED_IO_ddr_vrn;
|
||||||
|
inout FIXED_IO_ddr_vrp;
|
||||||
|
inout [53:0] FIXED_IO_mio;
|
||||||
|
inout FIXED_IO_ps_clk;
|
||||||
|
inout FIXED_IO_ps_porb;
|
||||||
|
inout FIXED_IO_ps_srstb;
|
||||||
|
|
||||||
|
inout [14:0] gpio_bd;
|
||||||
|
|
||||||
|
output hdmi_out_clk;
|
||||||
|
output hdmi_vsync;
|
||||||
|
output hdmi_hsync;
|
||||||
|
output hdmi_data_e;
|
||||||
|
output [23:0] hdmi_data;
|
||||||
|
|
||||||
|
output spdif;
|
||||||
|
|
||||||
|
inout iic_scl;
|
||||||
|
inout iic_sda;
|
||||||
|
|
||||||
|
input rx_ref_clk_p;
|
||||||
|
input rx_ref_clk_n;
|
||||||
|
input rx_sysref_p;
|
||||||
|
input rx_sysref_n;
|
||||||
|
output rx_sync_p;
|
||||||
|
output rx_sync_n;
|
||||||
|
input [ 1:0] rx_data_p;
|
||||||
|
input [ 1:0] rx_data_n;
|
||||||
|
|
||||||
|
input tx_ref_clk_p;
|
||||||
|
input tx_ref_clk_n;
|
||||||
|
output tx_clk_p;
|
||||||
|
output tx_clk_n;
|
||||||
|
output tx_frame_p;
|
||||||
|
output tx_frame_n;
|
||||||
|
output [15:0] tx_data_p;
|
||||||
|
output [15:0] tx_data_n;
|
||||||
|
|
||||||
|
inout gpio_adc_fdb;
|
||||||
|
inout gpio_adc_fda;
|
||||||
|
inout gpio_dac_irqn;
|
||||||
|
inout [ 1:0] gpio_clkd_status;
|
||||||
|
|
||||||
|
inout gpio_clkd_pdn;
|
||||||
|
inout gpio_clkd_syncn;
|
||||||
|
inout gpio_resetn;
|
||||||
|
|
||||||
|
output spi_csn_clk;
|
||||||
|
output spi_csn_dac;
|
||||||
|
output spi_csn_adc;
|
||||||
|
output spi_clk;
|
||||||
|
inout spi_sdio;
|
||||||
|
|
||||||
|
// internal registers
|
||||||
|
reg dma_wr = 'd0;
|
||||||
|
reg [63:0] dma_data = 'd0;
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire [39:0] gpio_i;
|
||||||
|
wire [39:0] gpio_o;
|
||||||
|
wire [39:0] gpio_t;
|
||||||
|
|
||||||
|
wire rx_ref_clk;
|
||||||
|
wire rx_sysref;
|
||||||
|
wire rx_sync;
|
||||||
|
wire [ 2:0] spi_csn;
|
||||||
|
|
||||||
|
wire adc_clk;
|
||||||
|
wire adc_enable_a;
|
||||||
|
wire [31:0] adc_data_a;
|
||||||
|
wire adc_enable_b;
|
||||||
|
wire [31:0] adc_data_b;
|
||||||
|
|
||||||
|
// pack & unpack data
|
||||||
|
|
||||||
|
always @(posedge adc_clk) begin
|
||||||
|
case ({adc_enable_b, adc_enable_a})
|
||||||
|
2'b11: begin
|
||||||
|
dma_wr <= 1'b1;
|
||||||
|
dma_data[63:48] <= adc_data_b[31:16];
|
||||||
|
dma_data[47:32] <= adc_data_a[31:16];
|
||||||
|
dma_data[31:16] <= adc_data_b[15: 0];
|
||||||
|
dma_data[15: 0] <= adc_data_a[15: 0];
|
||||||
|
end
|
||||||
|
2'b10: begin
|
||||||
|
dma_wr <= ~dma_wr;
|
||||||
|
dma_data[63:48] <= adc_data_b[31:16];
|
||||||
|
dma_data[47:32] <= adc_data_b[15: 0];
|
||||||
|
dma_data[31:16] <= dma_data[63:48];
|
||||||
|
dma_data[15: 0] <= dma_data[47:32];
|
||||||
|
end
|
||||||
|
2'b01: begin
|
||||||
|
dma_wr <= ~dma_wr;
|
||||||
|
dma_data[63:48] <= adc_data_a[31:16];
|
||||||
|
dma_data[47:32] <= adc_data_a[15: 0];
|
||||||
|
dma_data[31:16] <= dma_data[63:48];
|
||||||
|
dma_data[15: 0] <= dma_data[47:32];
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
dma_wr <= 1'b0;
|
||||||
|
dma_data[63:48] <= 16'd0;
|
||||||
|
dma_data[47:32] <= 16'd0;
|
||||||
|
dma_data[31:16] <= 16'd0;
|
||||||
|
dma_data[15: 0] <= 16'd0;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
assign spi_csn_adc = spi_csn[2];
|
||||||
|
assign spi_csn_dac = spi_csn[1];
|
||||||
|
assign spi_csn_clk = spi_csn[0];
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (rx_ref_clk_p),
|
||||||
|
.IB (rx_ref_clk_n),
|
||||||
|
.O (rx_ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_rx_sysref (
|
||||||
|
.I (rx_sysref_p),
|
||||||
|
.IB (rx_sysref_n),
|
||||||
|
.O (rx_sysref));
|
||||||
|
|
||||||
|
OBUFDS i_obufds_rx_sync (
|
||||||
|
.I (rx_sync),
|
||||||
|
.O (rx_sync_p),
|
||||||
|
.OB (rx_sync_n));
|
||||||
|
|
||||||
|
daq1_spi i_spi (
|
||||||
|
.spi_csn (spi_csn),
|
||||||
|
.spi_clk (spi_clk),
|
||||||
|
.spi_mosi (spi_mosi),
|
||||||
|
.spi_miso (spi_miso),
|
||||||
|
.spi_sdio (spi_sdio));
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(23)) i_iobuf (
|
||||||
|
.dt({gpio_t[39:32], gpio_t[14:0]}),
|
||||||
|
.di({gpio_o[39:32], gpio_o[14:0]}),
|
||||||
|
.do({gpio_i[39:32], gpio_i[14:0]}),
|
||||||
|
.dio({gpio_adc_fdb, // 39
|
||||||
|
gpio_adc_fda, // 38
|
||||||
|
gpio_dac_irqn, // 37
|
||||||
|
gpio_clkd_status, // 36:35
|
||||||
|
gpio_clkd_pdn, // 34
|
||||||
|
gpio_clkd_syncn, // 33
|
||||||
|
gpio_resetn, // 32
|
||||||
|
gpio_bd})); // 14:0
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.DDR_addr (DDR_addr),
|
||||||
|
.DDR_ba (DDR_ba),
|
||||||
|
.DDR_cas_n (DDR_cas_n),
|
||||||
|
.DDR_ck_n (DDR_ck_n),
|
||||||
|
.DDR_ck_p (DDR_ck_p),
|
||||||
|
.DDR_cke (DDR_cke),
|
||||||
|
.DDR_cs_n (DDR_cs_n),
|
||||||
|
.DDR_dm (DDR_dm),
|
||||||
|
.DDR_dq (DDR_dq),
|
||||||
|
.DDR_dqs_n (DDR_dqs_n),
|
||||||
|
.DDR_dqs_p (DDR_dqs_p),
|
||||||
|
.DDR_odt (DDR_odt),
|
||||||
|
.DDR_ras_n (DDR_ras_n),
|
||||||
|
.DDR_reset_n (DDR_reset_n),
|
||||||
|
.DDR_we_n (DDR_we_n),
|
||||||
|
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
|
||||||
|
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
|
||||||
|
.FIXED_IO_mio (FIXED_IO_mio),
|
||||||
|
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
|
||||||
|
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
|
||||||
|
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
|
||||||
|
.GPIO_I (gpio_i),
|
||||||
|
.GPIO_O (gpio_o),
|
||||||
|
.GPIO_T (gpio_t),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.rx_data_n (rx_data_n),
|
||||||
|
.rx_data_p (rx_data_p),
|
||||||
|
.rx_ref_clk (rx_ref_clk),
|
||||||
|
.rx_sync (rx_sync),
|
||||||
|
.rx_sysref (rx_sysref),
|
||||||
|
.adc_clk (adc_clk),
|
||||||
|
.adc_data_a (adc_data_a),
|
||||||
|
.adc_data_b (adc_data_b),
|
||||||
|
.adc_enable_a (adc_enable_a),
|
||||||
|
.adc_enable_b (adc_enable_b),
|
||||||
|
.adc_valid_a (),
|
||||||
|
.adc_valid_b (),
|
||||||
|
.dma_data (dma_data),
|
||||||
|
.dma_sync (1'b1),
|
||||||
|
.dma_wr (dma_wr),
|
||||||
|
.spdif (spdif),
|
||||||
|
.spi_clk_i (spi_clk),
|
||||||
|
.spi_clk_o (spi_clk),
|
||||||
|
.spi_csn_i (spi_csn),
|
||||||
|
.spi_csn_o (spi_csn),
|
||||||
|
.spi_sdi_i (spi_miso),
|
||||||
|
.spi_sdo_i (spi_mosi),
|
||||||
|
.spi_sdo_o (spi_mosi),
|
||||||
|
.tx_clk_n (tx_clk_n),
|
||||||
|
.tx_clk_p (tx_clk_p),
|
||||||
|
.tx_data_n (tx_data_n),
|
||||||
|
.tx_data_p (tx_data_p),
|
||||||
|
.tx_frame_n (tx_frame_n),
|
||||||
|
.tx_frame_p (tx_frame_p),
|
||||||
|
.tx_ref_clk_n (tx_ref_clk_n),
|
||||||
|
.tx_ref_clk_p (tx_ref_clk_p));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue