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avl_dacfifo: bundle AXIS signals into bus

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Laszlo Nagy 2019-05-16 08:08:01 +01:00 committed by Laszlo Nagy
parent dd952ddad1
commit eedb2ce0f4
1 changed files with 8 additions and 4 deletions
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12
library/altera/avl_dacfifo/avl_dacfifo_hw.tcl
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@ -32,11 +32,15 @@ ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000
ad_alt_intf clock dma_clk input 1 clk ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf reset dma_rst input 1 if_dma_clk ad_alt_intf reset dma_rst input 1 if_dma_clk
ad_alt_intf signal dma_valid input 1 valid
ad_alt_intf signal dma_data input DMA_DATA_WIDTH data
ad_alt_intf signal dma_ready output 1 ready
ad_alt_intf signal dma_xfer_req input 1 xfer_req ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_alt_intf signal dma_xfer_last input 1 last
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock if_dma_clk
set_interface_property s_axis associatedReset if_dma_rst
add_interface_port s_axis dma_valid tvalid Input 1
add_interface_port s_axis dma_xfer_last tlast Input 1
add_interface_port s_axis dma_ready tready Output 1
add_interface_port s_axis dma_data tdata Input DMA_DATA_WIDTH
ad_alt_intf clock dac_clk input 1 clk ad_alt_intf clock dac_clk input 1 clk
ad_alt_intf reset dac_rst input 1 if_dac_clk ad_alt_intf reset dac_rst input 1 if_dac_clk