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library/axi_tdd: Add generic TDD engine 

Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
main
Ionut Podgoreanu 2022-04-07 08:50:43 +01:00 committed by podgori
parent 7faefab1be
commit ef278e1c88
13 changed files with 1764 additions and 369 deletions
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20
library/axi_tdd/Makefile
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@ -6,17 +6,21 @@
LIBRARY_NAME := axi_tdd
GENERIC_DEPS += ../common/ad_addsub.v
GENERIC_DEPS += ../common/ad_tdd_control.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_tdd_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_tdd.v
GENERIC_DEPS += ../util_cdc/sync_bits.v
GENERIC_DEPS += ../util_cdc/sync_data.v
GENERIC_DEPS += ../util_cdc/sync_event.v
GENERIC_DEPS += axi_tdd.sv
GENERIC_DEPS += axi_tdd_channel.sv
GENERIC_DEPS += axi_tdd_counter.sv
GENERIC_DEPS += axi_tdd_pkg.sv
GENERIC_DEPS += axi_tdd_regmap.sv
GENERIC_DEPS += axi_tdd_sync_gen.sv
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_tdd_constr.ttcl
XILINX_DEPS += axi_tdd_ip.tcl
INTEL_DEPS += axi_tdd_constr.sdc
INTEL_DEPS += axi_tdd_hw.tcl
include ../scripts/library.mk

293
library/axi_tdd/axi_tdd.sv Normal file
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@ -0,0 +1,293 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_tdd #(
// Peripheral ID
parameter ID = 0,
// Number of active channels
parameter CHANNEL_COUNT = 8,
// Default polarity per channel
parameter DEFAULT_POLARITY = 8'h00,
// Timing register width, determines how long a single frame can be.
// T_max = (2^REGISTER_WIDTH) / f_clk
parameter REGISTER_WIDTH = 32,
// Burst count register width. Determines the maximum amount of repetitions
// of a frame.
parameter BURST_COUNT_WIDTH = 32,
// Synchronization / triggering options. These are not mutually exclusive, and
// both internal and external triggering can be available and selected at
// runtime.
parameter SYNC_INTERNAL = 1,
parameter SYNC_EXTERNAL = 0,
// Whether to insert a CDC stage with false path constraint for the external
// synchronization input.
parameter SYNC_EXTERNAL_CDC = 0,
parameter SYNC_COUNT_WIDTH = 64
) (
input logic clk,
input logic resetn,
// Sync signal
input logic sync_in,
output logic sync_out,
// Output channels
output logic [CHANNEL_COUNT-1:0] tdd_channel,
// AXI BUS
input logic s_axi_aresetn,
input logic s_axi_aclk,
input logic s_axi_awvalid,
input logic [ 9:0] s_axi_awaddr,
input logic [ 2:0] s_axi_awprot,
output logic s_axi_awready,
input logic s_axi_wvalid,
input logic [31:0] s_axi_wdata,
input logic [ 3:0] s_axi_wstrb,
output logic s_axi_wready,
output logic s_axi_bvalid,
output logic [ 1:0] s_axi_bresp,
input logic s_axi_bready,
input logic s_axi_arvalid,
input logic [ 9:0] s_axi_araddr,
input logic [ 2:0] s_axi_arprot,
output logic s_axi_arready,
output logic s_axi_rvalid,
output logic [ 1:0] s_axi_rresp,
output logic [31:0] s_axi_rdata,
input logic s_axi_rready
);
// Package import
import axi_tdd_pkg::*;
// Internal up bus, translated by up_axi
logic up_rstn;
logic up_clk;
logic up_wreq;
logic [ 7:0] up_waddr;
logic [31:0] up_wdata;
logic up_wack;
logic up_rreq;
logic [ 7:0] up_raddr;
logic [31:0] up_rdata;
logic up_rack;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// Control signals
logic tdd_enable;
logic tdd_sync_rst;
logic tdd_sync_int;
logic tdd_sync_ext;
logic tdd_sync_soft;
// Config wires
logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count;
logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay;
logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length;
// Synchronization config
logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period;
// Channel config
logic [CHANNEL_COUNT-1:0] tdd_channel_en;
logic [CHANNEL_COUNT-1:0] asy_tdd_channel_pol;
logic [REGISTER_WIDTH-1:0] asy_tdd_channel_on [0:CHANNEL_COUNT-1];
logic [REGISTER_WIDTH-1:0] asy_tdd_channel_off [0:CHANNEL_COUNT-1];
// Current counter value
logic [REGISTER_WIDTH-1:0] tdd_counter;
// Current FSM state
state_t tdd_cstate;
// Asserted to indicate the end of a tdd frame. This allows the channels to
// reset outputs which are still open due to a potential misconfiguration.
logic tdd_endof_frame;
axi_tdd_regmap #(
.ID (ID),
.CHANNEL_COUNT (CHANNEL_COUNT),
.DEFAULT_POLARITY (DEFAULT_POLARITY),
.REGISTER_WIDTH (REGISTER_WIDTH),
.BURST_COUNT_WIDTH (BURST_COUNT_WIDTH),
.SYNC_INTERNAL (SYNC_INTERNAL),
.SYNC_EXTERNAL (SYNC_EXTERNAL),
.SYNC_EXTERNAL_CDC (SYNC_EXTERNAL_CDC),
.SYNC_COUNT_WIDTH (SYNC_COUNT_WIDTH)
) i_regmap (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack),
.tdd_clk (clk),
.tdd_resetn (resetn),
.tdd_cstate (tdd_cstate),
.tdd_enable (tdd_enable),
.tdd_channel_en (tdd_channel_en),
.asy_tdd_channel_pol (asy_tdd_channel_pol),
.asy_tdd_burst_count (asy_tdd_burst_count),
.asy_tdd_startup_delay (asy_tdd_startup_delay),
.asy_tdd_frame_length (asy_tdd_frame_length),
.asy_tdd_channel_on (asy_tdd_channel_on),
.asy_tdd_channel_off (asy_tdd_channel_off),
.asy_tdd_sync_period (asy_tdd_sync_period),
.tdd_sync_rst (tdd_sync_rst),
.tdd_sync_int (tdd_sync_int),
.tdd_sync_ext (tdd_sync_ext),
.tdd_sync_soft (tdd_sync_soft));
axi_tdd_counter #(
.REGISTER_WIDTH (REGISTER_WIDTH),
.BURST_COUNT_WIDTH (BURST_COUNT_WIDTH)
) i_counter (
.clk (clk),
.resetn (resetn),
.tdd_enable (tdd_enable),
.tdd_sync_rst (tdd_sync_rst),
.tdd_sync (sync_out),
.asy_tdd_burst_count (asy_tdd_burst_count),
.asy_tdd_startup_delay (asy_tdd_startup_delay),
.asy_tdd_frame_length (asy_tdd_frame_length),
.tdd_counter (tdd_counter),
.tdd_cstate (tdd_cstate),
.tdd_endof_frame (tdd_endof_frame));
axi_tdd_sync_gen #(
.SYNC_INTERNAL (SYNC_INTERNAL),
.SYNC_EXTERNAL (SYNC_EXTERNAL),
.SYNC_EXTERNAL_CDC (SYNC_EXTERNAL_CDC),
.SYNC_COUNT_WIDTH (SYNC_COUNT_WIDTH)
) i_sync_gen (
.clk (clk),
.resetn (resetn),
.sync_in (sync_in),
.sync_out (sync_out),
.tdd_enable (tdd_enable),
.tdd_sync_int (tdd_sync_int),
.tdd_sync_ext (tdd_sync_ext),
.tdd_sync_soft (tdd_sync_soft),
.asy_tdd_sync_period (asy_tdd_sync_period));
genvar i;
generate
for (i = 0; i < CHANNEL_COUNT; i=i+1) begin
axi_tdd_channel #(
.DEFAULT_POLARITY (DEFAULT_POLARITY[i]),
.REGISTER_WIDTH (REGISTER_WIDTH)
) i_channel (
.clk (clk),
.resetn (resetn),
.tdd_counter (tdd_counter),
.tdd_cstate (tdd_cstate),
.tdd_enable (tdd_enable),
.tdd_endof_frame (tdd_endof_frame),
.ch_en (tdd_channel_en[i]),
.asy_ch_pol (asy_tdd_channel_pol[i]),
.asy_t_high (asy_tdd_channel_on[i]),
.asy_t_low (asy_tdd_channel_off[i]),
.out (tdd_channel[i]));
end
endgenerate
up_axi #(
.AXI_ADDRESS_WIDTH(10)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
endmodule

329
library/axi_tdd/axi_tdd.v
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@ -1,329 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_tdd #(
// Boolean. Whether a false path constraint should be introduced for the tdd_sync
// trigger input. This allows asynchronous (or external) sources to be used.
// Note: This parameter isn't used inside of the core, but just for the
// configuration of the constraints file.
parameter ASYNC_TDD_SYNC = 1
) (
// clock
input clk,
input rst,
// control signals from the tdd control
output tdd_rx_vco_en,
output tdd_tx_vco_en,
output tdd_rx_rf_en,
output tdd_tx_rf_en,
// status signal
output tdd_enabled,
// sync signal
input tdd_sync,
output reg tdd_sync_cntr,
// tx/rx data flow control
output reg tdd_tx_valid,
output reg tdd_rx_valid,
// bus interface
input s_axi_aresetn,
input s_axi_aclk,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
// internal signals
wire up_rstn;
wire up_clk;
wire up_wreq;
wire [13:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_rreq;
wire [13:0] up_raddr;
wire [31:0] up_rdata;
wire up_rack;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
wire tdd_enable_s;
wire tdd_secondary_s;
wire [ 7:0] tdd_burst_count_s;
wire tdd_rx_only_s;
wire tdd_tx_only_s;
wire tdd_gated_rx_dmapath_s;
wire tdd_gated_tx_dmapath_s;
wire [23:0] tdd_counter_init_s;
wire [23:0] tdd_frame_length_s;
wire tdd_terminal_type_s;
wire tdd_sync_enable_s;
wire [23:0] tdd_vco_rx_on_1_s;
wire [23:0] tdd_vco_rx_off_1_s;
wire [23:0] tdd_vco_tx_on_1_s;
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_rx_dp_on_1_s;
wire [23:0] tdd_rx_dp_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_vco_rx_on_2_s;
wire [23:0] tdd_vco_rx_off_2_s;
wire [23:0] tdd_vco_tx_on_2_s;
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_rx_dp_on_2_s;
wire [23:0] tdd_rx_dp_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire [ 7:0] tdd_status;
wire [23:0] tdd_counter_status;
wire tdd_rx_dp_en_s;
wire tdd_tx_dp_en_s;
reg tdd_vco_overlap;
reg tdd_rf_overlap;
assign tdd_enabled = tdd_enable_s;
// syncronization control signal
always @(posedge clk) begin
if (tdd_enable_s == 1'b1) begin
tdd_sync_cntr <= ~tdd_terminal_type_s;
end else begin
tdd_sync_cntr <= 1'b0;
end
end
// tx/rx data flow control
always @(posedge clk) begin
if ((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_tx_valid <= tdd_tx_dp_en_s;
end else begin
tdd_tx_valid <= 1'b1;
end
end
always @(posedge clk) begin
if ((tdd_enable_s == 1) && (tdd_gated_rx_dmapath_s == 1)) begin
tdd_rx_valid <= tdd_rx_dp_en_s;
end else begin
tdd_rx_valid <= 1'b1;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_vco_overlap <= 1'b0;
tdd_rf_overlap <= 1'b0;
end else begin
tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
end
end
assign tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
// instantiations
up_tdd_cntrl #(
.BASE_ADDRESS('h0)
) i_up_tdd_cntrl(
.clk(clk),
.rst(rst),
.tdd_enable(tdd_enable_s),
.tdd_secondary(tdd_secondary_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_rx_only(tdd_rx_only_s),
.tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s),
.tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_terminal_type(tdd_terminal_type_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_status(tdd_status),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
ad_tdd_control #(
.TX_DATA_PATH_DELAY(0),
.CONTROL_PATH_DELAY(0)
) i_tdd_control (
.clk(clk),
.rst(rst),
.tdd_enable(tdd_enable_s),
.tdd_secondary(tdd_secondary_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_rx_only(tdd_rx_only_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_sync (tdd_sync),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_rx_dp_en(tdd_rx_dp_en_s),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en),
.tdd_tx_vco_en(tdd_tx_vco_en),
.tdd_rx_rf_en(tdd_rx_rf_en),
.tdd_tx_rf_en(tdd_tx_rf_en),
.tdd_counter_status(tdd_counter_status));
up_axi #(
.AXI_ADDRESS_WIDTH(16)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
endmodule

168
library/axi_tdd/axi_tdd_channel.sv Normal file
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@ -0,0 +1,168 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_tdd_channel #(
parameter DEFAULT_POLARITY = 0,
parameter REGISTER_WIDTH = 32
) (
input logic clk,
input logic resetn,
input logic [REGISTER_WIDTH-1:0] tdd_counter,
input axi_tdd_pkg::state_t tdd_cstate,
input logic tdd_enable,
input logic tdd_endof_frame,
input logic ch_en,
input logic asy_ch_pol,
input logic [REGISTER_WIDTH-1:0] asy_t_high,
input logic [REGISTER_WIDTH-1:0] asy_t_low,
output logic out
);
// package import
import axi_tdd_pkg::*;
// internal registers
logic ch_pol;
logic [REGISTER_WIDTH-1:0] t_high;
logic [REGISTER_WIDTH-1:0] t_low;
logic tdd_ch_en;
logic tdd_ch_set;
logic tdd_ch_rst;
// initial values
initial begin
tdd_ch_en = 1'b0;
tdd_ch_set = 1'b0;
tdd_ch_rst = 1'b0;
out = 1'b0;
end
// Connect the enable signal to the enable flop lines
(* direct_enable = "yes" *) logic enable;
assign enable = tdd_enable;
// Save the async register values only when the module is enabled
always @(posedge clk) begin
if (resetn == 1'b0) begin
ch_pol <= DEFAULT_POLARITY;
end else begin
if (enable) begin
ch_pol <= asy_ch_pol;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
t_high <= '0;
end else begin
if (enable) begin
t_high <= asy_t_high;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
t_low <= '0;
end else begin
if (enable) begin
t_low <= asy_t_low;
end
end
end
// TDD channel control signals
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_ch_en <= 1'b0;
end else begin
if (tdd_cstate == IDLE) begin
tdd_ch_en <= 1'b0;
end else begin
if ((tdd_cstate == ARMED) || (tdd_endof_frame == 1'b1)) begin
tdd_ch_en <= ch_en;
end
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_ch_set <= 1'b0;
end else begin
if ((tdd_cstate == RUNNING) && (tdd_counter == t_high)) begin
tdd_ch_set <= 1'b1;
end else begin
tdd_ch_set <= 1'b0;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_ch_rst <= 1'b0;
end else begin
if (((tdd_cstate == RUNNING) && (tdd_counter == t_low)) || (tdd_endof_frame == 1'b1)) begin
tdd_ch_rst <= 1'b1;
end else begin
tdd_ch_rst <= 1'b0;
end
end
end
// TDD channel output
always @(posedge clk) begin
if (resetn == 1'b0) begin
out <= DEFAULT_POLARITY;
end else begin
if ((tdd_ch_en == 1'b0) || (tdd_ch_rst == 1'b1)) begin
out <= ch_pol;
end else begin
if (tdd_ch_set == 1'b1) begin
out <= ~ch_pol;
end else begin
out <= out;
end
end
end
end
endmodule

43
library/axi_tdd/axi_tdd_constr.sdc Normal file
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@ -0,0 +1,43 @@
set_false_path \
-from [get_registers {*|i_regmap|up_tdd_burst_count[*]}] \
-to [get_registers {*|i_counter|tdd_burst_count[*]}]
set_false_path \
-from [get_registers {*|i_regmap|up_tdd_startup_delay[*]}] \
-to [get_registers {*|i_counter|tdd_startup_delay[*]}]
set_false_path \
-from [get_registers {*|i_regmap|up_tdd_frame_length[*]}] \
-to [get_registers {*|i_counter|tdd_frame_length[*]}]
set_false_path \
-to [get_registers {*|i_sync_gen|tdd_sync_m1}]
set_false_path \
-from [get_registers {*|i_regmap|up_tdd_sync_period_low[*]}] \
-to [get_registers {*|i_sync_gen|tdd_sync_period[*]}]
set_false_path \
-from [get_registers {*|i_regmap|up_tdd_sync_period_high[*]}] \
-to [get_registers {*|i_sync_gen|tdd_sync_period[*]}]
set_false_path \
-from [get_registers {*|i_regmap|up_tdd_channel_pol[*]}] \
-to [get_registers {*|[*].i_channel|ch_pol}]
set_false_path \
-from [get_registers {*|i_regmap|*up_tdd_channel_on[*][*]}] \
-to [get_registers {*|[*].i_channel|t_high[*]}]
set_false_path \
-from [get_registers {*|i_regmap|*up_tdd_channel_off[*][*]}] \
-to [get_registers {*|[*].i_channel|t_low[*]}]
util_cdc_sync_bits_constr {*|axi_tdd_regmap:i_regmap|sync_bits:i_tdd_control_sync}
util_cdc_sync_bits_constr {*|axi_tdd_regmap:i_regmap|sync_bits:i_tdd_ch_en_sync}
util_cdc_sync_data_constr {*|axi_tdd_regmap:i_regmap|sync_data:i_tdd_cstate_sync}
util_cdc_sync_event_constr {*|axi_tdd_regmap:i_regmap|sync_event:i_tdd_soft_sync}

100
library/axi_tdd/axi_tdd_constr.ttcl
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@ -3,14 +3,100 @@
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set async_tdd_sync [getBooleanValue "ASYNC_TDD_SYNC"] :>
<: set tdd_sync_int [get_property MODELPARAM_VALUE.SYNC_INTERNAL] :>
<: set tdd_sync_ext [get_property MODELPARAM_VALUE.SYNC_EXTERNAL] :>
<: set tdd_sync_cdc [get_property MODELPARAM_VALUE.SYNC_EXTERNAL_CDC] :>
<: set tdd_sync_width [get_property MODELPARAM_VALUE.SYNC_COUNT_WIDTH] :>
## For RX in case of BRAMs
<: if { $async_tdd_sync == 1 } { :>
# TDD sync false paths
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *tdd_sync_d && IS_SEQUENTIAL}]
set_false_path -quiet -to [get_cells -quiet -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -hier {*cdc_sync_stage1_reg*}] \
[get_cells -hier {*cdc_sync_stage2_reg*}]
<: if { $tdd_sync_cdc == 1 } { :>
set_property ASYNC_REG TRUE \
[get_cells -hier {*tdd_sync_m1_reg*}] \
[get_cells -hier {*tdd_sync_m2_reg*}] \
[get_cells -hier {*tdd_sync_m3_reg*}]
set_false_path -to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_m1_reg}]
<: } :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_burst_count_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_burst_count_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_startup_delay_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_startup_delay_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_frame_length_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_frame_length_reg[*]}]
<: if { $tdd_sync_width > 0 } { :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_period_low_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_period_reg[*]}]
<: } :>
<: if { $tdd_sync_width > 32 } { :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_period_high_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_period_reg[*]}]
<: } :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_channel_pol_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_channel/ch_pol_reg}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*up_tdd_channel_on_reg[*][*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_channel/t_high_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*up_tdd_channel_off_reg[*][*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_channel/t_low_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_enable_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[0]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_rst_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[1]}]
<: if { $tdd_sync_int == 1 } { :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_int_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[2]}]
<: } :>
<: if { $tdd_sync_ext == 1 } { :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_ext_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[3]}]
<: } :>
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_channel_en_reg[*]}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_ch_en_sync/cdc_sync_stage1_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/out_data_reg*}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/in_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/i_sync_out/cdc_sync_stage1_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/out_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/i_sync_in/cdc_sync_stage1_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/in_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/i_sync_out/cdc_sync_stage1_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/out_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/i_sync_in/cdc_sync_stage1_reg[*]}]

243
library/axi_tdd/axi_tdd_counter.sv Normal file
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@ -0,0 +1,243 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_tdd_counter #(
parameter REGISTER_WIDTH = 32,
parameter BURST_COUNT_WIDTH = 32
) (
input logic clk,
input logic resetn,
input logic tdd_enable,
input logic tdd_sync_rst,
input logic tdd_sync,
input logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count,
input logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay,
input logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length,
output logic [REGISTER_WIDTH-1:0] tdd_counter,
output axi_tdd_pkg::state_t tdd_cstate,
output logic tdd_endof_frame
);
// package import
import axi_tdd_pkg::*;
// internal registers/wires
logic [BURST_COUNT_WIDTH-1:0] tdd_burst_count;
logic [REGISTER_WIDTH-1:0] tdd_startup_delay;
logic [REGISTER_WIDTH-1:0] tdd_frame_length;
logic [BURST_COUNT_WIDTH-1:0] tdd_burst_counter;
logic tdd_delay_done;
logic tdd_delay_skip;
logic tdd_endof_burst;
logic tdd_last_burst;
state_t tdd_cstate_ns;
// initial values
initial begin
tdd_burst_counter = '0;
tdd_counter = '0;
tdd_cstate = IDLE;
tdd_cstate_ns = IDLE;
tdd_delay_done = 1'b0;
tdd_delay_skip = 1'b0;
tdd_endof_frame = 1'b0;
tdd_last_burst = 1'b0;
end
// Connect the enable signal to the enable flop lines
(* direct_enable = "yes" *) logic enable;
assign enable = tdd_enable;
// Save the async register values only when the module is enabled
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_burst_count <= '0;
end else begin
if (enable) begin
tdd_burst_count <= asy_tdd_burst_count;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_startup_delay <= '0;
end else begin
if (enable) begin
tdd_startup_delay <= asy_tdd_startup_delay;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_frame_length <= '0;
end else begin
if (enable) begin
tdd_frame_length <= asy_tdd_frame_length;
end
end
end
// TDD counter FSM
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_cstate <= IDLE;
end else begin
tdd_cstate <= tdd_cstate_ns;
end
end
always @* begin
tdd_cstate_ns = tdd_cstate;
case (tdd_cstate)
IDLE : begin
if (tdd_enable == 1'b1) begin
tdd_cstate_ns = ARMED;
end
end
ARMED : begin
if (tdd_enable == 1'b0) begin
tdd_cstate_ns = IDLE;
end else if (tdd_sync == 1'b1) begin
tdd_cstate_ns = (tdd_delay_skip == 1'b1) ? RUNNING : WAITING;
end
end
WAITING : begin
if (tdd_delay_done == 1'b1) begin
tdd_cstate_ns = RUNNING;
end
end
RUNNING : begin
if (tdd_endof_frame == 1'b1) begin
tdd_cstate_ns = (tdd_endof_burst == 1'b1) ? (tdd_enable ? ARMED : IDLE) :
(((tdd_burst_counter == 0) && !tdd_enable) ? IDLE : RUNNING);
end
end
endcase
end
// TDD control signals
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_delay_done <= 1'b0;
end else begin
if (tdd_counter == (tdd_startup_delay - 1'b1)) begin
tdd_delay_done <= 1'b1;
end else begin
tdd_delay_done <= 1'b0;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_delay_skip <= 1'b0;
end else begin
if (tdd_startup_delay == 0) begin
tdd_delay_skip <= 1'b1;
end else begin
tdd_delay_skip <= 1'b0;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_endof_frame <= 1'b0;
end else begin
if (tdd_counter == (tdd_frame_length - 1'b1)) begin
tdd_endof_frame <= 1'b1;
end else begin
tdd_endof_frame <= 1'b0;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_last_burst <= 1'b0;
end else begin
tdd_last_burst <= (tdd_burst_counter == 1) ? 1'b1 : 1'b0;
end
end
assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_endof_frame == 1'b1)) ? 1'b1 : 1'b0;
// TDD free running counter
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_counter <= '0;
end else begin
if ((tdd_sync && tdd_sync_rst) == 1'b1) begin
tdd_counter <= '0;
end else begin
if (tdd_cstate == WAITING) begin
tdd_counter <= (tdd_delay_done == 1'b1) ? '0 : tdd_counter + 1'b1;
end else begin
if (tdd_cstate == RUNNING) begin
tdd_counter <= (tdd_endof_frame == 1'b1) ? '0 : tdd_counter + 1'b1;
end else begin
tdd_counter <= '0;
end
end
end
end
end
// TDD burst counter
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_burst_counter <= '0;
end else begin
if (tdd_cstate == ARMED) begin
tdd_burst_counter <= tdd_burst_count;
end else begin
if ((tdd_cstate == RUNNING) && (tdd_burst_counter != 0) && (tdd_endof_frame == 1'b1)) begin
tdd_burst_counter <= tdd_burst_counter - 1'b1;
end
end
end
end
endmodule

95
library/axi_tdd/axi_tdd_hw.tcl Normal file
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@ -0,0 +1,95 @@
package require qsys 14.0
source ../../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_tdd
set_module_property DESCRIPTION "AXI TDD Interface"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_tdd
ad_ip_files axi_tdd [list\
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/util_cdc/sync_bits.v \
$ad_hdl_dir/library/util_cdc/sync_data.v \
$ad_hdl_dir/library/util_cdc/sync_event.v \
axi_tdd_pkg.sv \
axi_tdd_channel.sv \
axi_tdd_counter.sv \
axi_tdd_regmap.sv \
axi_tdd_sync_gen.sv \
axi_tdd.sv \
axi_tdd_constr.sdc]
# parameters
set group "General Configuration"
add_parameter ID INTEGER 0
set_parameter_property ID DISPLAY_NAME "Core ID"
set_parameter_property ID HDL_PARAMETER true
set_parameter_property ID GROUP $group
add_parameter CHANNEL_COUNT INTEGER 8
set_parameter_property CHANNEL_COUNT DISPLAY_NAME "Number of TDD Channels"
set_parameter_property CHANNEL_COUNT HDL_PARAMETER true
set_parameter_property CHANNEL_COUNT ALLOWED_RANGES {1:32}
set_parameter_property CHANNEL_COUNT GROUP $group
add_parameter DEFAULT_POLARITY INTEGER 0
set_parameter_property DEFAULT_POLARITY DISPLAY_NAME "Default Channel output Polarity"
set_parameter_property DEFAULT_POLARITY HDL_PARAMETER true
set_parameter_property DEFAULT_POLARITY GROUP $group
add_parameter REGISTER_WIDTH INTEGER 32
set_parameter_property REGISTER_WIDTH DISPLAY_NAME "TDD Register Width"
set_parameter_property REGISTER_WIDTH HDL_PARAMETER true
set_parameter_property REGISTER_WIDTH ALLOWED_RANGES {8:32}
set_parameter_property REGISTER_WIDTH GROUP $group
add_parameter BURST_COUNT_WIDTH INTEGER 32
set_parameter_property BURST_COUNT_WIDTH DISPLAY_NAME "TDD Burst Counter Width"
set_parameter_property BURST_COUNT_WIDTH HDL_PARAMETER true
set_parameter_property BURST_COUNT_WIDTH ALLOWED_RANGES {8:32}
set_parameter_property BURST_COUNT_WIDTH GROUP $group
add_parameter SYNC_INTERNAL INTEGER 1
set_parameter_property SYNC_INTERNAL DISPLAY_NAME "Sync Internal enable"
set_parameter_property SYNC_INTERNAL HDL_PARAMETER true
set_parameter_property SYNC_INTERNAL ALLOWED_RANGES {0:1}
set_parameter_property SYNC_INTERNAL GROUP $group
add_parameter SYNC_EXTERNAL INTEGER 0
set_parameter_property SYNC_EXTERNAL DISPLAY_NAME "Sync External enable"
set_parameter_property SYNC_EXTERNAL HDL_PARAMETER true
set_parameter_property SYNC_EXTERNAL ALLOWED_RANGES {0:1}
set_parameter_property SYNC_EXTERNAL GROUP $group
add_parameter SYNC_EXTERNAL_CDC INTEGER 0
set_parameter_property SYNC_EXTERNAL_CDC DISPLAY_NAME "Sync External CDC enable"
set_parameter_property SYNC_EXTERNAL_CDC HDL_PARAMETER true
set_parameter_property SYNC_EXTERNAL_CDC ALLOWED_RANGES {0:1}
set_parameter_property SYNC_EXTERNAL_CDC GROUP $group
add_parameter SYNC_COUNT_WIDTH INTEGER 64
set_parameter_property SYNC_COUNT_WIDTH DISPLAY_NAME "TDD Sync Counter Width"
set_parameter_property SYNC_COUNT_WIDTH HDL_PARAMETER true
set_parameter_property SYNC_COUNT_WIDTH ALLOWED_RANGES {0:64}
set_parameter_property SYNC_COUNT_WIDTH GROUP $group
# interfaces
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
add_interface tdd_clock clock end
add_interface_port tdd_clock clk clk Input 1
add_interface tdd_reset reset end
set_interface_property tdd_reset associatedClock tdd_clock
add_interface_port tdd_reset resetn reset_n Input 1
ad_interface signal sync_in input 1
ad_interface signal sync_out output 1
ad_interface signal tdd_channel output 32

81
library/axi_tdd/axi_tdd_ip.tcl
View File

@ -5,15 +5,16 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_tdd
adi_ip_files axi_tdd [list \
"$ad_hdl_dir/library/common/ad_addsub.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"axi_tdd.v" ]
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
"$ad_hdl_dir/library/util_cdc/sync_data.v" \
"$ad_hdl_dir/library/util_cdc/sync_event.v" \
"axi_tdd_pkg.sv" \
"axi_tdd_channel.sv" \
"axi_tdd_counter.sv" \
"axi_tdd_regmap.sv" \
"axi_tdd_sync_gen.sv" \
"axi_tdd.sv" ]
adi_ip_properties axi_tdd
adi_ip_ttcl axi_tdd "axi_tdd_constr.ttcl"
@ -38,24 +39,54 @@ add_reset s_axi_aresetn ACTIVE_LOW
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]
set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
set cc [ipx::current_core]
## Remove the automatically generated GUI page
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
ipx::save_core [ipx::current_core]
## Create a new GUI page
ipgui::add_page -name {ADI AXI TDD Controller} -component [ipx::current_core] -display_name {ADI AXI TDD Controller}
set page0 [ipgui::get_pagespec -name "ADI AXI TDD Controller" -component $cc]
## General Configurations
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
-parent $page0 -display_name "General Configuration" ]
set param [ipgui::add_param -name {ASYNC_TDD_SYNC} -component $cc -parent $page0]
set_property -dict [list \
display_name {Insert false path for tdd_sync} \
widget {checkBox} \
] $param
"value_validation_type" "range_long" \
"value_validation_range_minimum" "1" \
"value_validation_range_maximum" "32" \
] \
[ipx::get_user_parameters CHANNEL_COUNT -of_objects [ipx::current_core]]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "8" \
"value_validation_range_maximum" "32" \
] \
[ipx::get_user_parameters REGISTER_WIDTH -of_objects [ipx::current_core]]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "8" \
"value_validation_range_maximum" "32" \
] \
[ipx::get_user_parameters BURST_COUNT_WIDTH -of_objects [ipx::current_core]]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "64" \
] \
[ipx::get_user_parameters SYNC_COUNT_WIDTH -of_objects [ipx::current_core]]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "1" \
] \
[ipx::get_user_parameters SYNC_INTERNAL -of_objects [ipx::current_core]]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "1" \
] \
[ipx::get_user_parameters SYNC_EXTERNAL -of_objects [ipx::current_core]]
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" "0" \
"value_validation_range_maximum" "1" \
] \
[ipx::get_user_parameters SYNC_EXTERNAL_CDC -of_objects [ipx::current_core]]
ipx::create_xgui_files [ipx::current_core]

103
library/axi_tdd/axi_tdd_pkg.sv Normal file
View File

@ -0,0 +1,103 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
package axi_tdd_pkg;
typedef enum logic [1:0] {
IDLE = 2'b00,
ARMED = 2'b01,
WAITING = 2'b10,
RUNNING = 2'b11} state_t;
localparam
PCORE_VERSION = 32'h00020061,
PCORE_MAGIC = 32'h5444444E; // "TDDN", big endian
// register address offset
localparam
ADDR_TDD_VERSION = 8'h00,
ADDR_TDD_ID = 8'h01,
ADDR_TDD_SCRATCH = 8'h02,
ADDR_TDD_IDENTIFICATION = 8'h03,
ADDR_TDD_INTERFACE = 8'h04,
ADDR_TDD_DEF_POLARITY = 8'h05,
ADDR_TDD_CONTROL = 8'h10,
ADDR_TDD_CH_ENABLE = 8'h11,
ADDR_TDD_CH_POLARITY = 8'h12,
ADDR_TDD_BURST_COUNT = 8'h13,
ADDR_TDD_STARTUP_DELAY = 8'h14,
ADDR_TDD_FRAME_LENGTH = 8'h15,
ADDR_TDD_SYNC_CNT_LOW = 8'h16,
ADDR_TDD_SYNC_CNT_HIGH = 8'h17,
ADDR_TDD_STATUS = 8'h18,
ADDR_TDD_CH_ON = 8'h20,
ADDR_TDD_CH_OFF = 8'h21;
// channel offset values
localparam
CH0 = 0,
CH1 = 1,
CH2 = 2,
CH3 = 3,
CH4 = 4,
CH5 = 5,
CH6 = 6,
CH7 = 7,
CH8 = 8,
CH9 = 9,
CH10 = 10,
CH11 = 11,
CH12 = 12,
CH13 = 13,
CH14 = 14,
CH15 = 15,
CH16 = 16,
CH17 = 17,
CH18 = 18,
CH19 = 19,
CH20 = 20,
CH21 = 21,
CH22 = 22,
CH23 = 23,
CH24 = 24,
CH25 = 25,
CH26 = 26,
CH27 = 27,
CH28 = 28,
CH29 = 29,
CH30 = 30,
CH31 = 31;
endpackage

445
library/axi_tdd/axi_tdd_regmap.sv Normal file
View File

@ -0,0 +1,445 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_tdd_regmap #(
parameter ID = 0,
parameter CHANNEL_COUNT = 8,
parameter DEFAULT_POLARITY = 8'h00,
parameter REGISTER_WIDTH = 32,
parameter BURST_COUNT_WIDTH = 32,
parameter SYNC_INTERNAL = 1,
parameter SYNC_EXTERNAL = 0,
parameter SYNC_EXTERNAL_CDC = 0,
parameter SYNC_COUNT_WIDTH = 64
) (
// tdd clock
input logic tdd_clk,
input logic tdd_resetn,
// tdd interface control
input axi_tdd_pkg::state_t tdd_cstate,
output logic tdd_enable,
output logic [CHANNEL_COUNT-1:0] tdd_channel_en,
output logic [CHANNEL_COUNT-1:0] asy_tdd_channel_pol,
output logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count,
output logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay,
output logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length,
output logic [REGISTER_WIDTH-1:0] asy_tdd_channel_on [0:CHANNEL_COUNT-1],
output logic [REGISTER_WIDTH-1:0] asy_tdd_channel_off [0:CHANNEL_COUNT-1],
output logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period,
output logic tdd_sync_rst,
output logic tdd_sync_int,
output logic tdd_sync_ext,
output logic tdd_sync_soft,
// bus interface
input logic up_rstn,
input logic up_clk,
input logic up_wreq,
input logic [ 7:0] up_waddr,
input logic [31:0] up_wdata,
output logic up_wack,
input logic up_rreq,
input logic [ 7:0] up_raddr,
output logic [31:0] up_rdata,
output logic up_rack
);
// package import
import axi_tdd_pkg::*;
// local params
localparam CHANNEL_COUNT_EXTRA = CHANNEL_COUNT - 1;
// internal registers
logic [31:0] up_scratch;
logic [ 1:0] up_tdd_cstate;
logic up_tdd_enable;
logic up_tdd_sync_rst;
logic up_tdd_sync_int;
logic up_tdd_sync_ext;
logic up_tdd_sync_soft;
logic [CHANNEL_COUNT-1:0] up_tdd_channel_en;
logic [CHANNEL_COUNT-1:0] up_tdd_channel_pol;
logic [BURST_COUNT_WIDTH-1:0] up_tdd_burst_count;
logic [REGISTER_WIDTH-1:0] up_tdd_startup_delay;
logic [REGISTER_WIDTH-1:0] up_tdd_frame_length;
logic [REGISTER_WIDTH-1:0] up_tdd_channel_on [0:CHANNEL_COUNT-1];
logic [REGISTER_WIDTH-1:0] up_tdd_channel_off [0:CHANNEL_COUNT-1];
//internal wires
logic [31:0] status_synth_params_s;
logic [31:0] status_def_polarity_s;
logic [31:0] up_tdd_channel_en_s;
logic [31:0] up_tdd_channel_pol_s;
logic [31:0] up_tdd_burst_count_s;
logic [31:0] up_tdd_startup_delay_s;
logic [31:0] up_tdd_frame_length_s;
logic [63:0] up_tdd_sync_period_s;
logic [31:0] up_tdd_channel_on_s [0:31];
logic [31:0] up_tdd_channel_off_s [0:31];
//initial values
initial begin
up_rdata = 32'b0;
up_wack = 1'b0;
up_rack = 1'b0;
up_scratch = 32'b0;
up_tdd_enable = 1'b0;
up_tdd_sync_rst = 1'b0;
up_tdd_sync_int = 1'b0;
up_tdd_sync_ext = 1'b0;
up_tdd_sync_soft = 1'b0;
up_tdd_channel_en = '0;
up_tdd_channel_pol = '0;
up_tdd_burst_count = '0;
up_tdd_startup_delay = '0;
up_tdd_frame_length = '0;
up_tdd_channel_on = '{default:0};
up_tdd_channel_off = '{default:0};
end
//read-only synthesis parameters
assign status_synth_params_s = {
/*31:24 */ 1'b0, 7'(SYNC_COUNT_WIDTH),
/*23:16 */ 2'b0, 6'(BURST_COUNT_WIDTH),
/*15: 8 */ 2'b0, 6'(REGISTER_WIDTH),
/* 7: 0 */ 1'(SYNC_EXTERNAL_CDC),
1'(SYNC_EXTERNAL),
1'(SYNC_INTERNAL),
5'(CHANNEL_COUNT_EXTRA)};
assign status_def_polarity_s = {{(32-CHANNEL_COUNT){1'b0}}, DEFAULT_POLARITY};
// processor write interface
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'b0;
up_scratch <= 32'b0;
up_tdd_enable <= 1'b0;
up_tdd_sync_rst <= 1'b0;
up_tdd_sync_int <= 1'b0;
up_tdd_sync_ext <= 1'b0;
up_tdd_sync_soft <= 1'b0;
up_tdd_channel_en <= '0;
up_tdd_channel_pol <= '0;
up_tdd_startup_delay <= '0;
up_tdd_frame_length <= '0;
up_tdd_burst_count <= '0;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SCRATCH)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CONTROL)) begin
up_tdd_sync_soft <= up_wdata[4];
up_tdd_sync_ext <= up_wdata[3] & SYNC_EXTERNAL;
up_tdd_sync_int <= up_wdata[2] & SYNC_INTERNAL;
up_tdd_sync_rst <= up_wdata[1];
up_tdd_enable <= up_wdata[0];
end else begin
up_tdd_sync_soft <= 1'b0;
up_tdd_sync_ext <= up_tdd_sync_ext;
up_tdd_sync_int <= up_tdd_sync_int;
up_tdd_sync_rst <= up_tdd_sync_rst;
up_tdd_enable <= up_tdd_enable;
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CH_ENABLE)) begin
up_tdd_channel_en <= up_wdata[CHANNEL_COUNT-1:0];
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CH_POLARITY) && !up_tdd_enable) begin
up_tdd_channel_pol <= up_wdata[CHANNEL_COUNT-1:0];
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_BURST_COUNT) && !up_tdd_enable) begin
up_tdd_burst_count <= up_wdata[BURST_COUNT_WIDTH-1:0];
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_STARTUP_DELAY) && !up_tdd_enable) begin
up_tdd_startup_delay <= up_wdata[REGISTER_WIDTH-1:0];
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_FRAME_LENGTH) && !up_tdd_enable) begin
up_tdd_frame_length <= up_wdata[REGISTER_WIDTH-1:0];
end
end
end
assign up_tdd_channel_en_s = {{(32-CHANNEL_COUNT){1'b0}}, up_tdd_channel_en};
assign up_tdd_channel_pol_s = {{(32-CHANNEL_COUNT){1'b0}}, up_tdd_channel_pol};
assign up_tdd_burst_count_s = {{(32-BURST_COUNT_WIDTH){1'b0}}, up_tdd_burst_count};
assign up_tdd_startup_delay_s = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_startup_delay};
assign up_tdd_frame_length_s = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_frame_length};
// internal sync counter generation (low and high)
generate
if (SYNC_COUNT_WIDTH>32) begin
logic [31:0] up_tdd_sync_period_low;
logic [(SYNC_COUNT_WIDTH-32-1):0] up_tdd_sync_period_high;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_tdd_sync_period_low <= 32'b0;
up_tdd_sync_period_high <= '0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_LOW) && !up_tdd_enable) begin
up_tdd_sync_period_low <= up_wdata[31:0];
end
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_HIGH) && !up_tdd_enable) begin
up_tdd_sync_period_high <= up_wdata[(SYNC_COUNT_WIDTH-32-1):0];
end
end
end
assign up_tdd_sync_period_s[31:0] = up_tdd_sync_period_low;
assign up_tdd_sync_period_s[63:32] = {{(64-SYNC_COUNT_WIDTH){1'b0}}, up_tdd_sync_period_high};
assign asy_tdd_sync_period = {up_tdd_sync_period_high, up_tdd_sync_period_low}; //skipping CDC
end else begin
if (SYNC_COUNT_WIDTH>0) begin
logic [SYNC_COUNT_WIDTH-1:0] up_tdd_sync_period_low;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_tdd_sync_period_low <= '0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_LOW) && !up_tdd_enable) begin
up_tdd_sync_period_low <= up_wdata[(SYNC_COUNT_WIDTH-1):0];
end
end
end
assign up_tdd_sync_period_s[31:0] = {{(32-SYNC_COUNT_WIDTH){1'b0}}, up_tdd_sync_period_low};
assign up_tdd_sync_period_s[63:32] = 32'b0;
assign asy_tdd_sync_period = up_tdd_sync_period_low; //skipping CDC
end else begin
assign up_tdd_sync_period_s[31:0] = 32'b0;
assign up_tdd_sync_period_s[63:32] = 32'b0;
assign asy_tdd_sync_period = '0;
end
end
endgenerate
// channel register generation
genvar i;
generate
for (i=0; i<CHANNEL_COUNT; i=i+1) begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_tdd_channel_on[i] <= '0;
up_tdd_channel_off[i] <= '0;
end else begin
if ((up_wreq == 1'b1) && (up_waddr == (ADDR_TDD_CH_ON + i*2)) && !up_tdd_enable) begin
up_tdd_channel_on[i] <= up_wdata[REGISTER_WIDTH-1:0];
end
if ((up_wreq == 1'b1) && (up_waddr == (ADDR_TDD_CH_OFF + i*2)) && !up_tdd_enable) begin
up_tdd_channel_off[i] <= up_wdata[REGISTER_WIDTH-1:0];
end
end
end
assign up_tdd_channel_on_s[i] = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_channel_on[i]};
assign up_tdd_channel_off_s[i] = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_channel_off[i]};
end
if (CHANNEL_COUNT<32) begin
assign up_tdd_channel_on_s[CHANNEL_COUNT:31] = '{default:0};
assign up_tdd_channel_off_s[CHANNEL_COUNT:31] = '{default:0};
end
endgenerate
// processor read interface
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 32'b0;
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr)
ADDR_TDD_VERSION : up_rdata <= PCORE_VERSION;
ADDR_TDD_ID : up_rdata <= ID[31:0];
ADDR_TDD_SCRATCH : up_rdata <= up_scratch;
ADDR_TDD_IDENTIFICATION : up_rdata <= PCORE_MAGIC;
ADDR_TDD_INTERFACE : up_rdata <= status_synth_params_s;
ADDR_TDD_DEF_POLARITY : up_rdata <= status_def_polarity_s;
ADDR_TDD_CONTROL : up_rdata <= {27'b0, up_tdd_sync_soft,
up_tdd_sync_ext,
up_tdd_sync_int,
up_tdd_sync_rst,
up_tdd_enable};
ADDR_TDD_CH_ENABLE : up_rdata <= up_tdd_channel_en_s;
ADDR_TDD_CH_POLARITY : up_rdata <= up_tdd_channel_pol_s;
ADDR_TDD_BURST_COUNT : up_rdata <= up_tdd_burst_count_s;
ADDR_TDD_STARTUP_DELAY : up_rdata <= up_tdd_startup_delay_s;
ADDR_TDD_FRAME_LENGTH : up_rdata <= up_tdd_frame_length_s;
ADDR_TDD_SYNC_CNT_LOW : up_rdata <= up_tdd_sync_period_s[31:0];
ADDR_TDD_SYNC_CNT_HIGH : up_rdata <= up_tdd_sync_period_s[63:32];
ADDR_TDD_STATUS : up_rdata <= {30'b0, up_tdd_cstate};
ADDR_TDD_CH_ON + 2*CH0 : up_rdata <= up_tdd_channel_on_s[CH0];
ADDR_TDD_CH_OFF + 2*CH0 : up_rdata <= up_tdd_channel_off_s[CH0];
ADDR_TDD_CH_ON + 2*CH1 : up_rdata <= up_tdd_channel_on_s[CH1];
ADDR_TDD_CH_OFF + 2*CH1 : up_rdata <= up_tdd_channel_off_s[CH1];
ADDR_TDD_CH_ON + 2*CH2 : up_rdata <= up_tdd_channel_on_s[CH2];
ADDR_TDD_CH_OFF + 2*CH2 : up_rdata <= up_tdd_channel_off_s[CH2];
ADDR_TDD_CH_ON + 2*CH3 : up_rdata <= up_tdd_channel_on_s[CH3];
ADDR_TDD_CH_OFF + 2*CH3 : up_rdata <= up_tdd_channel_off_s[CH3];
ADDR_TDD_CH_ON + 2*CH4 : up_rdata <= up_tdd_channel_on_s[CH4];
ADDR_TDD_CH_OFF + 2*CH4 : up_rdata <= up_tdd_channel_off_s[CH4];
ADDR_TDD_CH_ON + 2*CH5 : up_rdata <= up_tdd_channel_on_s[CH5];
ADDR_TDD_CH_OFF + 2*CH5 : up_rdata <= up_tdd_channel_off_s[CH5];
ADDR_TDD_CH_ON + 2*CH6 : up_rdata <= up_tdd_channel_on_s[CH6];
ADDR_TDD_CH_OFF + 2*CH6 : up_rdata <= up_tdd_channel_off_s[CH6];
ADDR_TDD_CH_ON + 2*CH7 : up_rdata <= up_tdd_channel_on_s[CH7];
ADDR_TDD_CH_OFF + 2*CH7 : up_rdata <= up_tdd_channel_off_s[CH7];
ADDR_TDD_CH_ON + 2*CH8 : up_rdata <= up_tdd_channel_on_s[CH8];
ADDR_TDD_CH_OFF + 2*CH8 : up_rdata <= up_tdd_channel_off_s[CH8];
ADDR_TDD_CH_ON + 2*CH9 : up_rdata <= up_tdd_channel_on_s[CH9];
ADDR_TDD_CH_OFF + 2*CH9 : up_rdata <= up_tdd_channel_off_s[CH9];
ADDR_TDD_CH_ON + 2*CH10 : up_rdata <= up_tdd_channel_on_s[CH10];
ADDR_TDD_CH_OFF + 2*CH10 : up_rdata <= up_tdd_channel_off_s[CH10];
ADDR_TDD_CH_ON + 2*CH11 : up_rdata <= up_tdd_channel_on_s[CH11];
ADDR_TDD_CH_OFF + 2*CH11 : up_rdata <= up_tdd_channel_off_s[CH11];
ADDR_TDD_CH_ON + 2*CH12 : up_rdata <= up_tdd_channel_on_s[CH12];
ADDR_TDD_CH_OFF + 2*CH12 : up_rdata <= up_tdd_channel_off_s[CH12];
ADDR_TDD_CH_ON + 2*CH13 : up_rdata <= up_tdd_channel_on_s[CH13];
ADDR_TDD_CH_OFF + 2*CH13 : up_rdata <= up_tdd_channel_off_s[CH13];
ADDR_TDD_CH_ON + 2*CH14 : up_rdata <= up_tdd_channel_on_s[CH14];
ADDR_TDD_CH_OFF + 2*CH14 : up_rdata <= up_tdd_channel_off_s[CH14];
ADDR_TDD_CH_ON + 2*CH15 : up_rdata <= up_tdd_channel_on_s[CH15];
ADDR_TDD_CH_OFF + 2*CH15 : up_rdata <= up_tdd_channel_off_s[CH15];
ADDR_TDD_CH_ON + 2*CH16 : up_rdata <= up_tdd_channel_on_s[CH16];
ADDR_TDD_CH_OFF + 2*CH16 : up_rdata <= up_tdd_channel_off_s[CH16];
ADDR_TDD_CH_ON + 2*CH17 : up_rdata <= up_tdd_channel_on_s[CH17];
ADDR_TDD_CH_OFF + 2*CH17 : up_rdata <= up_tdd_channel_off_s[CH17];
ADDR_TDD_CH_ON + 2*CH18 : up_rdata <= up_tdd_channel_on_s[CH18];
ADDR_TDD_CH_OFF + 2*CH18 : up_rdata <= up_tdd_channel_off_s[CH18];
ADDR_TDD_CH_ON + 2*CH19 : up_rdata <= up_tdd_channel_on_s[CH19];
ADDR_TDD_CH_OFF + 2*CH19 : up_rdata <= up_tdd_channel_off_s[CH19];
ADDR_TDD_CH_ON + 2*CH20 : up_rdata <= up_tdd_channel_on_s[CH20];
ADDR_TDD_CH_OFF + 2*CH20 : up_rdata <= up_tdd_channel_off_s[CH20];
ADDR_TDD_CH_ON + 2*CH21 : up_rdata <= up_tdd_channel_on_s[CH21];
ADDR_TDD_CH_OFF + 2*CH21 : up_rdata <= up_tdd_channel_off_s[CH21];
ADDR_TDD_CH_ON + 2*CH22 : up_rdata <= up_tdd_channel_on_s[CH22];
ADDR_TDD_CH_OFF + 2*CH22 : up_rdata <= up_tdd_channel_off_s[CH22];
ADDR_TDD_CH_ON + 2*CH23 : up_rdata <= up_tdd_channel_on_s[CH23];
ADDR_TDD_CH_OFF + 2*CH23 : up_rdata <= up_tdd_channel_off_s[CH23];
ADDR_TDD_CH_ON + 2*CH24 : up_rdata <= up_tdd_channel_on_s[CH24];
ADDR_TDD_CH_OFF + 2*CH24 : up_rdata <= up_tdd_channel_off_s[CH24];
ADDR_TDD_CH_ON + 2*CH25 : up_rdata <= up_tdd_channel_on_s[CH25];
ADDR_TDD_CH_OFF + 2*CH25 : up_rdata <= up_tdd_channel_off_s[CH25];
ADDR_TDD_CH_ON + 2*CH26 : up_rdata <= up_tdd_channel_on_s[CH26];
ADDR_TDD_CH_OFF + 2*CH26 : up_rdata <= up_tdd_channel_off_s[CH26];
ADDR_TDD_CH_ON + 2*CH27 : up_rdata <= up_tdd_channel_on_s[CH27];
ADDR_TDD_CH_OFF + 2*CH27 : up_rdata <= up_tdd_channel_off_s[CH27];
ADDR_TDD_CH_ON + 2*CH28 : up_rdata <= up_tdd_channel_on_s[CH28];
ADDR_TDD_CH_OFF + 2*CH28 : up_rdata <= up_tdd_channel_off_s[CH28];
ADDR_TDD_CH_ON + 2*CH29 : up_rdata <= up_tdd_channel_on_s[CH29];
ADDR_TDD_CH_OFF + 2*CH29 : up_rdata <= up_tdd_channel_off_s[CH29];
ADDR_TDD_CH_ON + 2*CH30 : up_rdata <= up_tdd_channel_on_s[CH30];
ADDR_TDD_CH_OFF + 2*CH30 : up_rdata <= up_tdd_channel_off_s[CH30];
ADDR_TDD_CH_ON + 2*CH31 : up_rdata <= up_tdd_channel_on_s[CH31];
ADDR_TDD_CH_OFF + 2*CH31 : up_rdata <= up_tdd_channel_off_s[CH31];
default: up_rdata <= 32'b0;
endcase
end else begin
up_rdata <= 32'b0;
end
end
end
// control signals CDC
sync_bits #(
.NUM_OF_BITS (4),
.ASYNC_CLK (1)
) i_tdd_control_sync (
.in_bits ({up_tdd_sync_ext,
up_tdd_sync_int,
up_tdd_sync_rst,
up_tdd_enable}),
.out_resetn (tdd_resetn),
.out_clk (tdd_clk),
.out_bits ({tdd_sync_ext,
tdd_sync_int,
tdd_sync_rst,
tdd_enable}));
sync_event #(
.NUM_OF_EVENTS (1),
.ASYNC_CLK (1)
) i_tdd_soft_sync (
.in_clk (up_clk),
.in_event (up_tdd_sync_soft),
.out_clk (tdd_clk),
.out_event (tdd_sync_soft));
sync_bits #(
.NUM_OF_BITS (CHANNEL_COUNT),
.ASYNC_CLK (1)
) i_tdd_ch_en_sync (
.in_bits (up_tdd_channel_en),
.out_resetn (tdd_resetn),
.out_clk (tdd_clk),
.out_bits (tdd_channel_en));
sync_data #(
.NUM_OF_BITS (2),
.ASYNC_CLK (1)
) i_tdd_cstate_sync (
.in_clk (tdd_clk),
.in_data (tdd_cstate),
.out_clk (up_clk),
.out_data (up_tdd_cstate));
// skipping CDC for the rest of the registers since the register writes are gated with module enable
// furthermore, updating the async domain registers is also conditioned by the synchronized module enable
assign asy_tdd_burst_count = up_tdd_burst_count;
assign asy_tdd_startup_delay = up_tdd_startup_delay;
assign asy_tdd_frame_length = up_tdd_frame_length;
assign asy_tdd_channel_pol = up_tdd_channel_pol;
assign asy_tdd_channel_on = up_tdd_channel_on;
assign asy_tdd_channel_off = up_tdd_channel_off;
endmodule

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library/axi_tdd/axi_tdd_sync_gen.sv Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_tdd_sync_gen #(
parameter SYNC_INTERNAL = 1,
parameter SYNC_EXTERNAL = 0,
parameter SYNC_EXTERNAL_CDC = 0,
parameter SYNC_COUNT_WIDTH = 64
) (
input logic clk,
input logic resetn,
input logic sync_in,
output logic sync_out,
input logic tdd_enable,
input logic tdd_sync_ext,
input logic tdd_sync_int,
input logic tdd_sync_soft,
input logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period
);
// internal signals
logic [1:0] sync_source;
// Connect the enable signal to the enable flop lines
(* direct_enable = "yes" *) logic enable;
assign enable = tdd_enable;
// first sync source (external)
generate
if (SYNC_EXTERNAL == 1) begin
if (SYNC_EXTERNAL_CDC == 1) begin
logic tdd_sync_m1 = 1'b0;
logic tdd_sync_m2 = 1'b0;
logic tdd_sync_m3 = 1'b0;
// synchronization of sync_in
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_sync_m1 <= 1'b0;
tdd_sync_m2 <= 1'b0;
tdd_sync_m3 <= 1'b0;
end else begin
tdd_sync_m1 <= sync_in;
tdd_sync_m2 <= tdd_sync_m1;
tdd_sync_m3 <= tdd_sync_m2;
end
end
assign sync_source[0] = ~tdd_sync_m3 & tdd_sync_m2;
end else begin
assign sync_source[0] = sync_in;
end
end else begin
assign sync_source[0] = 1'b0;
end
endgenerate
// second sync source (internal)
generate
if (SYNC_INTERNAL == 1) begin
logic tdd_sync_trigger = 1'b0;
logic [SYNC_COUNT_WIDTH-1:0] tdd_sync_counter = '0;
logic [SYNC_COUNT_WIDTH-1:0] tdd_sync_period = '0;
// Save the async register values only when the module is enabled
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_sync_period <= '0;
end else begin
if (enable) begin
tdd_sync_period <= asy_tdd_sync_period;
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_sync_trigger <= 1'b0;
end else begin
if (tdd_sync_counter == (tdd_sync_period - 1'b1)) begin
tdd_sync_trigger <= 1'b1;
end else begin
tdd_sync_trigger <= 1'b0;
end
end
end
// sync counter
always @(posedge clk) begin
if (resetn == 1'b0) begin
tdd_sync_counter <= '0;
end else begin
if (tdd_enable) begin
tdd_sync_counter <= (tdd_sync_trigger == 1'b1) ? '0 : tdd_sync_counter + 1'b1;
end else begin
tdd_sync_counter <= '0;
end
end
end
assign sync_source[1] = tdd_sync_trigger;
end else begin
assign sync_source[1] = 1'b0;
end
endgenerate
// creating the output sync signal
assign sync_out = (tdd_sync_ext & sync_source[0]) | (tdd_sync_int & sync_source[1]) | tdd_sync_soft;
endmodule

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library/axi_tdd/scripts/axi_tdd.tcl Normal file
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proc ad_tdd_gen_create {ip_name
num_of_channels
{default_polarity 0}
{reg_counter_width 32}
{burst_counter_width 32}
{sync_counter_width 64}
{sync_internal 1}
{sync_external 0}
{sync_external_cdc 0}} {
create_bd_cell -type hier $ip_name
# Control interface
create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
# Device interface
create_bd_pin -dir I -type clk "${ip_name}/clk"
create_bd_pin -dir I -type rst "${ip_name}/resetn"
create_bd_pin -dir I "${ip_name}/sync_in"
create_bd_pin -dir O "${ip_name}/sync_out"
for {set i 0} {$i < $num_of_channels} {incr i} {
create_bd_pin -dir O "${ip_name}/tdd_channel_${i}"
}
# Generic TDD core
ad_ip_instance axi_tdd "${ip_name}/tdd_core" [list \
CHANNEL_COUNT $num_of_channels \
DEFAULT_POLARITY $default_polarity \
REGISTER_WIDTH $reg_counter_width \
BURST_COUNT_WIDTH $burst_counter_width \
SYNC_COUNT_WIDTH $sync_counter_width \
SYNC_INTERNAL $sync_internal \
SYNC_EXTERNAL $sync_external \
SYNC_EXTERNAL_CDC $sync_external_cdc
]
for {set i 0} {$i < $num_of_channels} {incr i} {
ad_ip_instance xlslice "${ip_name}/tdd_ch_slice_${i}" [list \
DIN_WIDTH $num_of_channels \
DIN_FROM $i \
DIN_TO $i \
]
}
# Create connections
ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tdd_core/s_axi_aclk"
ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tdd_core/s_axi_aresetn"
ad_connect "${ip_name}/s_axi" "${ip_name}/tdd_core/s_axi"
ad_connect ${ip_name}/tdd_core/clk ${ip_name}/clk
ad_connect ${ip_name}/tdd_core/resetn ${ip_name}/resetn
ad_connect ${ip_name}/tdd_core/sync_in ${ip_name}/sync_in
ad_connect ${ip_name}/tdd_core/sync_out ${ip_name}/sync_out
for {set i 0} {$i < $num_of_channels} {incr i} {
ad_connect ${ip_name}/tdd_core/tdd_channel ${ip_name}/tdd_ch_slice_$i/Din
ad_connect ${ip_name}/tdd_ch_slice_$i/Dout ${ip_name}/tdd_channel_$i
}
}