library/axi_ad9361: hw component updates
Rejeesh Kutty
parent
3b5e44e37d
commit
ef6c99ecab
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@ -73,13 +73,34 @@ set_parameter_property DEVICE_TYPE TYPE INTEGER
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set_parameter_property DEVICE_TYPE UNITS None
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set_parameter_property DEVICE_TYPE HDL_PARAMETER true
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add_parameter CMOS_OR_LVDS_N INTEGER 0
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set_parameter_property CMOS_OR_LVDS_N DEFAULT_VALUE 0
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set_parameter_property CMOS_OR_LVDS_N DISPLAY_NAME CMOS_OR_LVDS_N
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set_parameter_property CMOS_OR_LVDS_N TYPE INTEGER
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set_parameter_property CMOS_OR_LVDS_N UNITS None
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set_parameter_property CMOS_OR_LVDS_N HDL_PARAMETER true
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add_parameter DAC_DATAPATH_DISABLE INTEGER 0
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set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
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set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
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set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
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set_parameter_property DAC_DATAPATH_DISABLE UNITS None
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set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
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add_parameter ADC_DATAPATH_DISABLE INTEGER 0
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set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
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set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
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set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
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set_parameter_property ADC_DATAPATH_DISABLE UNITS None
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set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED false
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# axi4 slave
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# axi4 slave interface
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock s_axi_aclk clk Input 1
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@ -111,120 +132,134 @@ add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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# device interface
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# master-slave interface
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add_interface device_clock clock end
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add_interface_port device_clock clk clk Input 1
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ad_alt_intf signal dac_sync_in input 1
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ad_alt_intf signal dac_sync_out output 1
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ad_alt_intf signal tdd_sync input 1
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ad_alt_intf signal tdd_sync_cntr output 1
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add_interface device_if conduit end
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set_interface_property device_if associatedClock device_clock
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add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
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add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
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add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
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add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
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add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
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add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
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add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
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add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
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add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
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add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
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add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
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add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
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ad_alt_intf signal dac_sync_in input 1 sync
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ad_alt_intf signal dac_sync_out output 1 sync
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ad_alt_intf clock l_clk output 1
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ad_alt_intf reset rst output 1 if_l_clk
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ad_alt_intf clock delay_clk input 1
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ad_alt_intf clock l_clk output 1
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ad_alt_intf clock clk input 1
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ad_alt_intf reset rst output 1 if_clk
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set_interface_property if_rst associatedResetSinks none
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add_interface fifo_ch_0_in conduit end
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add_interface_port fifo_ch_0_in adc_enable_i0 enable Output 1
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add_interface_port fifo_ch_0_in adc_valid_i0 valid Output 1
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add_interface_port fifo_ch_0_in adc_data_i0 data Output 16
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add_interface_port fifo_ch_0_in adc_enable_i0 enable Output 1
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add_interface_port fifo_ch_0_in adc_valid_i0 valid Output 1
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add_interface_port fifo_ch_0_in adc_data_i0 data Output 16
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add_interface fifo_ch_1_in conduit end
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add_interface_port fifo_ch_1_in adc_enable_q0 enable Output 1
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add_interface_port fifo_ch_1_in adc_valid_q0 valid Output 1
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add_interface_port fifo_ch_1_in adc_data_q0 data Output 16
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add_interface_port fifo_ch_1_in adc_enable_q0 enable Output 1
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add_interface_port fifo_ch_1_in adc_valid_q0 valid Output 1
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add_interface_port fifo_ch_1_in adc_data_q0 data Output 16
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add_interface fifo_ch_2_in conduit end
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add_interface_port fifo_ch_2_in adc_enable_i1 enable Output 1
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add_interface_port fifo_ch_2_in adc_valid_i1 valid Output 1
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add_interface_port fifo_ch_2_in adc_data_i1 data Output 16
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add_interface_port fifo_ch_2_in adc_enable_i1 enable Output 1
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add_interface_port fifo_ch_2_in adc_valid_i1 valid Output 1
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add_interface_port fifo_ch_2_in adc_data_i1 data Output 16
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add_interface fifo_ch_3_in conduit end
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add_interface_port fifo_ch_3_in adc_enable_q1 enable Output 1
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add_interface_port fifo_ch_3_in adc_valid_q1 valid Output 1
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add_interface_port fifo_ch_3_in adc_data_q1 data Output 16
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add_interface_port fifo_ch_3_in adc_enable_q1 enable Output 1
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add_interface_port fifo_ch_3_in adc_valid_q1 valid Output 1
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add_interface_port fifo_ch_3_in adc_data_q1 data Output 16
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ad_alt_intf signal adc_dovf input 1 ovf
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ad_alt_intf signal adc_dunf input 1 unf
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ad_alt_intf signal adc_dovf input 1 ovf
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ad_alt_intf signal adc_dunf input 1 unf
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ad_alt_intf signal adc_r1_mode output 1 r1_mode
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add_interface fifo_ch_0_out conduit end
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add_interface_port fifo_ch_0_out dac_enable_i0 enable Output 1
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add_interface_port fifo_ch_0_out dac_valid_i0 valid Output 1
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add_interface_port fifo_ch_0_out dac_data_i0 data Input 16
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add_interface_port fifo_ch_0_out dac_enable_i0 enable Output 1
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add_interface_port fifo_ch_0_out dac_valid_i0 valid Output 1
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add_interface_port fifo_ch_0_out dac_data_i0 data Input 16
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add_interface fifo_ch_1_out conduit end
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add_interface_port fifo_ch_1_out dac_enable_q0 enable Output 1
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add_interface_port fifo_ch_1_out dac_valid_q0 valid Output 1
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add_interface_port fifo_ch_1_out dac_data_q0 data Input 16
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add_interface_port fifo_ch_1_out dac_enable_q0 enable Output 1
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add_interface_port fifo_ch_1_out dac_valid_q0 valid Output 1
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add_interface_port fifo_ch_1_out dac_data_q0 data Input 16
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add_interface fifo_ch_2_out conduit end
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add_interface_port fifo_ch_2_out dac_enable_i1 enable Output 1
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add_interface_port fifo_ch_2_out dac_valid_i1 valid Output 1
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add_interface_port fifo_ch_2_out dac_data_i1 data Input 16
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add_interface_port fifo_ch_2_out dac_enable_i1 enable Output 1
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add_interface_port fifo_ch_2_out dac_valid_i1 valid Output 1
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add_interface_port fifo_ch_2_out dac_data_i1 data Input 16
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add_interface fifo_ch_3_out conduit end
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add_interface_port fifo_ch_3_out dac_enable_q1 enable Output 1
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add_interface_port fifo_ch_3_out dac_valid_q1 valid Output 1
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add_interface_port fifo_ch_3_out dac_data_q1 data Input 16
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add_interface_port fifo_ch_3_out dac_enable_q1 enable Output 1
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add_interface_port fifo_ch_3_out dac_valid_q1 valid Output 1
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add_interface_port fifo_ch_3_out dac_data_q1 data Input 16
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ad_alt_intf signal dac_dovf input 1 ovf
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ad_alt_intf signal dac_dunf input 1 unf
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ad_alt_intf signal dac_dovf input 1 ovf
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ad_alt_intf signal dac_dunf input 1 unf
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ad_alt_intf signal dac_r1_mode output 1 r1_mode
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add_interface delay_clock clock end
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add_interface_port delay_clock delay_clk clk Input 1
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ad_alt_intf signal up_enable input 1
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ad_alt_intf signal up_txnrx input 1
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ad_alt_intf signal up_dac_gpio_in input 32
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ad_alt_intf signal up_dac_gpio_out output 32
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ad_alt_intf signal up_adc_gpio_in input 32
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ad_alt_intf signal up_adc_gpio_out output 32
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add_hdl_instance alt_lvds_in altera_gpio
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set_instance_parameter_value alt_lvds_in {PIN_TYPE_GUI} {Input}
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set_instance_parameter_value alt_lvds_in {SIZE} {1}
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set_instance_parameter_value alt_lvds_in {gui_diff_buff} {1}
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set_instance_parameter_value alt_lvds_in {gui_pseudo_diff} {0}
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set_instance_parameter_value alt_lvds_in {gui_io_reg_mode} {DDIO}
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# sub-modules
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add_hdl_instance alt_lvds_out altera_gpio
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set_instance_parameter_value alt_lvds_out {PIN_TYPE_GUI} {Output}
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set_instance_parameter_value alt_lvds_out {SIZE} {1}
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set_instance_parameter_value alt_lvds_out {gui_diff_buff} {1}
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set_instance_parameter_value alt_lvds_out {gui_pseudo_diff} {0}
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set_instance_parameter_value alt_lvds_out {gui_io_reg_mode} {DDIO}
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add_hdl_instance alt_ddio_in altera_gpio
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set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
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set_instance_parameter_value alt_ddio_in {SIZE} {1}
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set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
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set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
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add_hdl_instance alt_cmos_in altera_gpio
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set_instance_parameter_value alt_cmos_in {PIN_TYPE_GUI} {Input}
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set_instance_parameter_value alt_cmos_in {SIZE} {1}
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set_instance_parameter_value alt_cmos_in {gui_diff_buff} {0}
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set_instance_parameter_value alt_cmos_in {gui_pseudo_diff} {0}
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set_instance_parameter_value alt_cmos_in {gui_io_reg_mode} {DDIO}
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add_hdl_instance alt_ddio_out altera_gpio
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set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
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set_instance_parameter_value alt_ddio_out {SIZE} {1}
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set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
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set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
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add_hdl_instance alt_cmos_out altera_gpio
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set_instance_parameter_value alt_cmos_out {PIN_TYPE_GUI} {Output}
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set_instance_parameter_value alt_cmos_out {SIZE} {1}
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set_instance_parameter_value alt_cmos_out {gui_diff_buff} {0}
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set_instance_parameter_value alt_cmos_out {gui_pseudo_diff} {0}
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set_instance_parameter_value alt_cmos_out {gui_io_reg_mode} {DDIO}
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# updates
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proc p_axi_ad9361 {} {
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set ALTERA_DEVICE_TYPE [get_parameter_value DEVICE_TYPE]
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set ALTERA_DEVICE_FAMILY [get_parameter_value DEVICE_FAMILY]
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set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
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set m_device_type [get_parameter_value DEVICE_TYPE]
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set m_device_family [get_parameter_value DEVICE_FAMILY]
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if {$ALTERA_DEVICE_TYPE == 1} {
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add_interface device_if conduit end
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set_interface_property device_if associatedClock none
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set_interface_property device_if associatedReset none
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if {$m_cmos_or_lvds_n == 1} {
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add_interface_port device_if rx_clk_in rx_clk_in_p Input 1
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add_interface_port device_if rx_frame_in rx_frame_in_p Input 1
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add_interface_port device_if rx_data_in rx_data_in_p Input 12
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add_interface_port device_if tx_clk_out tx_clk_out_p Output 1
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add_interface_port device_if tx_frame_out tx_frame_out_p Output 1
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add_interface_port device_if tx_data_out tx_data_out_p Output 12
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}
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if {$ALTERA_DEVICE_TYPE == 0} {
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if {$m_cmos_or_lvds_n == 0} {
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add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
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add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
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add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
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add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
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add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
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add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
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add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
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add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
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add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
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add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
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add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
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add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
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}
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add_interface_port device_if enable enable Output 1
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add_interface_port device_if txnrx txnrx Output 1
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if {$m_device_type == 1} {
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}
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if {$m_device_type == 0} {
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add_hdl_instance alt_clk altera_iopll
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set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {250.0}
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@ -234,7 +269,7 @@ proc p_axi_ad9361 {} {
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set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {250.0}
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set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
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set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {90.0}
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set_instance_parameter_value alt_clk {system_info_device_family} $ALTERA_DEVICE_FAMILY
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set_instance_parameter_value alt_clk {system_info_device_family} $m_device_family
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}
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}
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