zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

docs: Include sphinx documentation 

The parameters directive allows to almost automatically generate the
parameters table.
It allows to add rich descriptions to the parameters, such as references,
while checking if they exist in the *_hw.tcl file a obtaining the types
and default values.
However, it cannot obtain parameters generated from a foreach loop yet,
making it incompatible with the axi_dmac_hw.tcl file for example.
This commit also joins the other extensions into a single adi_links
extension.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
main
Jorge Marques 2023-08-16 09:57:14 -03:00 committed by Jorge Marques
parent 9f824554aa
commit ef9c98f9b9
46 changed files with 5266 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
docs/Containerfile Normal file
View File

@ -0,0 +1,36 @@
FROM registry.gitlab.com/islandoftex/images/texlive:TL2022-2022-12-25-full
SHELL ["/bin/bash", "-c"]
ENV HOME /root
ARG DEBIAN_FRONTEND=noninteractive
ENV TZ=Europe/Bucharest
ENV PROJ hdl-docs
RUN apt-get update
RUN apt-get -y --no-install-recommends install \
python3 python3-venv python3-pip
# To convert svg to pdf, used in sphinx->LaTeX->pdf pipeline
RUN apt-get -y --no-install-recommends install \
librsvg2-bin
RUN python3 -m venv /opt/venv
COPY requirements.txt .
RUN source /opt/venv/bin/activate ; \
pip3 install -U pip
RUN source /opt/venv/bin/activate ; \
pip3 install wheel vext vext.gi
RUN source /opt/venv/bin/activate ; \
pip3 install -r requirements.txt ; \
deactivate
RUN mkdir -p /usr/local/bin ; \
ln -s /opt/venv/bin/symbolator /usr/local/bin/symbolator

76
docs/Makefile Executable file
View File

@ -0,0 +1,76 @@
SHELL = /bin/bash
SPHINXOPTS ?=
SPHINXBUILD ?= sphinx-build
SOURCEDIR = .
BUILDDIR = _build
help:
@echo "For help about the container instance, do \`make container-help\`"
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
#------------------------------------------------------------------------------
# Container commands
#------------------------------------------------------------------------------
CONTAINER_IMG ?=hdl-docs
CONTAINER_ENGINE =podman
CONTAINER_REPO =${CONTAINER_IMG}
CONTAINER_IMAGE =${CONTAINER_IMG}_build
CONTAINER_VERSION ?=0.1
CONTAINER_SHELL ?=bash -l
CONTAINER_RUN_EXTRA ?=
CONTAINER_FORMAT =$(if $(filter podman,${CONTAINER_ENGINE}),--format docker,)
IF_CONTAINER_RUNS=$(shell ${CONTAINER_ENFINE} container inspect -f '{{.State.Running}}' ${CONTAINER_IMAGE} 2>/dev/null)
CONTAINER_RUN_PARAMS = -it --rm --name=${CONTAINER_IMG} \
--name=${CONTAINER_IMAGE} \
--workdir=/${CONTAINER_IMG} \
--mount type=bind,source=${CURDIR}/../,target=/${CONTAINER_IMG} \
${CONTAINER_RUN_EXTRA} \
${CONTAINER_REPO}/${CONTAINER_IMAGE}:${CONTAINER_VERSION}
container-login:
@if [ "${IF_CONTAINER_RUNS}" != "true" ]; then \
${CONTAINER_ENGINE} run ${CONTAINER_RUN_PARAMS} \
${CONTAINER_SHELL}; \
else \
${CONTAINER_ENGINE} exec -it ${CONTAINER_IMAGE} \
${CONTAINER_SHELL}; \
fi
container-build:
@printf "Building container image\n"
@${CONTAINER_ENGINE} build --no-cache=true ${CONTAINER_FORMAT} -t ${CONTAINER_REPO}/${CONTAINER_IMAGE}:${CONTAINER_VERSION} -f ./Containerfile .
container-html:
@${CONTAINER_ENGINE} run ${CONTAINER_RUN_PARAMS} ${CONTAINER_SHELL} -c \
"source /.venv/bin/activate ; cd docs ; make html"
container-pdf:
@${CONTAINER_ENGINE} run ${CONTAINER_RUN_PARAMS} ${CONTAINER_SHELL} -c \
"source /.venv/bin/activate ; cd docs ; make latexpdf"
container-clean:
@${CONTAINER_ENGINE} run ${CONTAINER_RUN_PARAMS} ${CONTAINER_SHELL} -c \
"source /.venv/bin/activate ; cd docs ; make clean"
.PHONY: container-build container-login container-html container-pdf container-clean
container-help:
@printf "The container commands allow to use a container to build the documentation.\n"
@printf "Both podman and docker are supported, change the CONTAINER_ENGINE variable to select which to use.\n\n"
@printf "Usage: make [options]\n"
@printf "\
Options:\n\
container-build Build the container image with dependencies (do once).\n\
container-login Access the container shell.\n\
container-html Build html documentation.\n\
container-latexpdf Build pdf documentation.\n\
\n"

6
docs/appendix/bibliography.rst Executable file
View File

@ -0,0 +1,6 @@
Bibliography
======================================================
.. bibliography::
:all:

97
docs/appendix/glossary.rst Normal file
View File

@ -0,0 +1,97 @@
Glossary
======================================================
.. glossary::
SVG
Scalable Vector Graphics
reST
reStructuredText Primer
HDL
hardware description language
S
Start
PS
Processing System
Sr
Repeated Start
P
Stop
ACK
Acknowledge
IBI
In-band Interrupt
DAA
Dynamic Address Assignment
ADC
analog-digital converter
SoC
system-on-a-chip
SAR
succesive-approximation-register
IP
intellectual-property
PMOD
peripheral module interface
SOM
system on module
SDR
standard data rate
DDR
double data rate
HDR
high data rate
ID
identification
PID
Provisioned ID
MIPI
Manufacturer ID
MDB
Mandatory data byte
I/O
input/output
PUR
Pull-Up Resistor
CCC
Common Command Codes
T-bit
Transaction bit
SCL
Serial Clock
SDA
Serial Data
SPI
Serial Peripheral Interface
GPIO
General Purpose Input/Output

13
docs/appendix/references.bib Executable file
View File

@ -0,0 +1,13 @@
@misc{adi:hdl,
organization = {Analog Devices Inc},
title = {HDL Reference Designs},
howpublished = {\url{https://github.com/analogdevicesinc/hdl}},
year = {2023}
}
@misc{adi:i2c-quick-guide,
organization = {Analog Devices Inc},
title = {I²C Quick Guide},
howpublished = {\url{https://www.analog.com/media/en/technical-documentation/product-selector-card/i2Cb.pdf}},
year = {2017},
month = {April}
}

56
docs/conf.py Executable file
View File

@ -0,0 +1,56 @@
# Configuration file for the Sphinx documentation builder.
#
# https://www.sphinx-doc.org/en/master/usage/configuration.html
# -- Project information -----------------------------------------------------
project = 'HDL, Analog Devices'
copyright = '2023, Analog Devices Inc'
author = 'Analog Devices Inc'
release = 'v0.1'
# -- General configuration ---------------------------------------------------
import os, sys
sys.path.append(os.path.abspath("./extensions"))
extensions = [
"sphinx.ext.todo",
"sphinx.ext.viewcode",
"sphinxcontrib.bibtex",
"sphinxcontrib.mermaid",
"sphinxcontrib.wavedrom",
"symbolator_sphinx",
"adi_links",
"adi_hdl_parser"
]
templates_path = ['sources/template']
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
# -- Custom extensions configuration -------------------------------------------
# -- todo configuration -------------------------------------------------------
todo_include_todos = True
todo_emit_warnings = True
# -- Symbolator configuration -------------------------------------------------
symbolator_cmd = '~/.local/bin/symbolator' # Update with your installed location
symbolator_cmd_args = ['-t', '--scale=0.75']
# -- BibTeX configuration -----------------------------------------------------
bibtex_bibfiles = ['appendix/references.bib']
# -- Options for HTML output --------------------------------------------------
html_theme = 'furo'
html_static_path = ['sources']
source_suffix = '.rst'
html_css_files = ["custom.css"]
html_favicon = "sources/icon.svg"

316
docs/contributing/guidelines.rst Normal file
View File

@ -0,0 +1,316 @@
Guidelines
================================================================================
A brief set-of-rules for the documentation.
.. note::
The old wiki uses `dokuwiki <https://www.dokuwiki.org/dokuwiki>`_. When
importing text from there, consider the automated options that are provided
in this page to convert it to :term:`reST`.
Templates
--------------------------------------------------------------------------------
Templates are available:
* :git-hdl:`docs/library/template_ip` (:ref:`rendered <template_ip>`).
* :git-hdl:`docs/library/template_framework` (:ref:`rendered <template_framework>`).
Remove the ``:orphan:`` in the first line, it is to hide the templates from the
`TOC tree <https://www.sphinx-doc.org/en/master/usage/restructuredtext/directives.html#directive-toctree>`_.
Indentation
--------------------------------------------------------------------------------
Directives are indented with 3 space, which is Sphinx's default.
At code directives, the code keeps its original indentation (e.g. 2 spaces for
verilog code), but is offset by 3 spaces at the beginning of every line, to
instruct Sphinx the beginning and end of the code directive.
References
--------------------------------------------------------------------------------
References have the format ``library/project context``, e.g.
:code:`:ref:\`spi_engine execution\`` renders as :ref:`spi_engine execution`.
Notice how neither *library* nor *project* are present in the label, since there is no
naming collision between libraries or projects (no project will ever be named
*axi_dmac*).
Also, for project, libraries and :term:`IP`\s, the names should be exactly the
name of its folders, e.g. ``axi_pwm_gen`` and not ``axi-pwm-gen`` or ``AXI_PWM_GEN``,
this helps avoid broken references.
For resources without a particular source code file/folder, prefer hyphen ``-``
separation, for example, ``spi_engine control-interface`` instead of
``spi_engine control_interface``.
Text width
--------------------------------------------------------------------------------
Each line must be less than 80 columns wide.
You can use the :code:`fold` command to break the lines of the imported text
while respecting word-breaks:
.. code:: bash
cat imported.txt | fold -sw 80 > imported.rst
Or use the pandoc command provided in the next topic, since it will also fold
at column 80.
Tables
--------------------------------------------------------------------------------
Prefer
`list-tables <https://docutils.sourceforge.io/docs/ref/rst/directives.html#list-table>`_
and imported
`csv-tables <https://docutils.sourceforge.io/docs/ref/rst/directives.html#csv-table-1>`_
(using the file option), because they are faster to create, easier to maintain
and the 80 column-width rule can be respected with list-tables.
Converting dokuwiki tables to list-table would be very time consuming, however
there is a pandoc `list-table filter <https://github.com/jgm/pandoc/issues/4564>`_,
see :ref:`installing_pandoc` for install instructions.
You can use the following command:
.. code:: bash
pandoc <input.txt> -f dokuwiki -t rst --columns=80 -s -o <output.rst> --list-tables
The :code:`list-tables` parameter requires *pandoc-types* >= 1.23, if it is not
an option, you shall remove it and export in the *grid* table format.
Now you only have to adjust the widths and give the final touches, like using
the correct directives and roles.
Code
--------------------------------------------------------------------------------
Prefer
`code-blocks <https://www.sphinx-doc.org/en/master/usage/restructuredtext/directives.html#directive-code-block>`_
to
`code <https://docutils.sourceforge.io/docs/ref/rst/directives.html#code>`_
directives, because code-blocks have more options, such as showing line numbers
and emphasizing lines.
For example,
.. code:: rst
.. code-block:: python
:linenos:
:emphasize-lines: 2
def hello_world():
string = "Hello world"
print(string)
renders as
.. code-block:: python
:linenos:
:emphasize-lines: 2
def hello_world():
string = "Hello world"
print(string)
Images
--------------------------------------------------------------------------------
Prefer the :term:`SVG` format for images, and save it as *Optimized SVG* in
`inkscape <https://inkscape.org/>`_ to use less space.
Vivado block-diagrams
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vivado block-diadrams can be exported as PDF and then converted to SVG with
inkscape. See :ref:`spi_engine tutorial` for a "final result" example.
Vivado waveform data
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
There is no way to export Vivado waveform data as vectors.
Therefore, the recommended method is to take a PNG screenshot and use
`GIMP <gimp.org>`_ to export as **8bpc RGB** with all metadata options
disabled.
.. note::
Always use the *Export As..* ``Ctrl+Shift+E`` option.
To reduce even further the size, you can use *Color > Dither..* to reduce the
number of colors in the png.
Saving as greyscale also reduces the PNG size, but might reduce readability and
it is not recommended.
Third-party directives and roles
--------------------------------------------------------------------------------
Third-party tools are used to expand Sphinx functionality, for example, to
generate component diagrams.
.. tip::
Check :git-hdl:`docs/Containterfile` for a recipe to install these
tools, either in the host or in a container.
Symbolator directive
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`Symbolator <https://kevinpt.github.io/symbolator/>`_ is a tool to generate
component diagrams.
Custom directives and roles
--------------------------------------------------------------------------------
To expand Sphinx functionality beyond existing tools, custom directives and roles
have been written, which are located in the *docs/extensions* folder.
Extensions are straight forward to create, if some functionality is missing,
consider requesting or creating one.
Git role
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The Git role allows to create links to the Git repository with a shorter syntax.
The role syntax is :code:`:git-<repo>:\`<branch>:<path>\``, for example,
:code:`:git-hdl:\`master:contributing/guidelines.rst\``
is rendered as :git-hdl:`master:contributing/guidelines.rst`.
You can leave the branch blank to autofill the link with the current branch.
You can also do :code:`:git-<repo>:\`/\`` for a link to the root of the
repository with pretty naming, for example, :code:`:git-hdl:\`/\`` is rendered
as :git-hdl:`/`.
Part role
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The part role creates links for a part to the Analog Devices website.
The role syntax is :code:`:part:\`<part_id>:<part_name>\``, for example,
:code:`:part:\`ad7175-2:AD7175-2\``.
Since links are case insensitive, you can also reduce it to
:code:`:part:\`AD7175-2\``, when *part_id* is the same as *part_name*.
It is rendered as :part:`AD7175-2`.
Datasheet role
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The datasheet role creates links for a datasheet in the Analog Devices website.
The role syntax is :code:`:datasheet:\`<part_id>:<anchor>\``, for example,
:code:`:datasheet:\`AD7984:[{"num"%3A51%2C"gen"%3A0}%2C{"name"%3A"XYZ"}%2C52%2C713%2C0]\``
is rendered as
:datasheet:`AD7984:[{"num"%3A51%2C"gen"%3A0}%2C{"name"%3A"XYZ"}%2C52%2C713%2C0]`.
The anchor is optional and is a link to a section of the PDF, and can be obtained
by just copying the link in the table of contents.
.. caution::
Since not all PDF readers support anchors, always provide the page and/or
figure number!
Dokuwiki role
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The dokuwiki role creates links to the Analog Devices wiki website.
The role syntax is :code:`:dokuwiki:\`<name>:<path>\``, for example,
:code:`:dokuwiki:\`pulsar-adc-pmods:resources/eval/user-guides/circuits-from-the-lab/pulsar-adc-pmods\``
gets rendered as
:dokuwiki:`pulsar-adc-pmods:resources/eval/user-guides/circuits-from-the-lab/pulsar-adc-pmods`.
EngineerZone role
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The ez role creates links to the Analog Devices EngineerZone support website.
The role syntax is :code:`:ez:\`<community>\``, for example, :code:`:ez:\`fpga\``
gets rendered as :ez:`fpga`.
Xilinx role
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The xilinx role creates links to the Xilinx website.
The role syntax is :code:`:xilinx:\`<name>:<path>\``, for example,
:code:`:xilinx:\`Zynq-7000 SoC Overview:support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf\``
gets rendered
:xilinx:`Zynq-7000 SoC Overview:support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf`.
The name parameter is optional, if absent, the file name will be used as the name.
HDL parameters directive
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The HDL parameters directive parses the *\*_hw.tcl* library files to generate a
table with the IP parameters.
.. attention::
This directive does not support parameters generated in a foreach loop yet
(e.g. :git-hdl:`library/axi_dmac/axi_dmac_hw.tcl#L90`).
Manually create the parameters table in these cases.
The directive syntax is:
.. code:: rst
.. hdl-parameters::
:path: <ip_path>
* - <parameter>
- <description>
For example:
.. code:: rst
.. hdl-parameters::
:path: library/spi_engine/spi_engine_interconnect
* - DATA_WIDTH
- Data width of the parallel SDI/SDO data interfaces.
* - NUM_OF_SDI
- Number of SDI lines on the physical SPI interface.
renders as:
.. hdl-parameters::
:path: library/spi_engine/spi_engine_interconnect
* - DATA_WIDTH
- Data width of the parallel SDI/SDO data interfaces.
* - NUM_OF_SDI
- Number of SDI lines on the physical SPI interface.
Notice how the *Type* and *Default* values are obtained from the *\*_hw.tcl*.
Parameters not listed in the directive are also added to the table, but
will have an empty description, unless a comment follows the ``ad_ip_parameter``
method in the source file.
If you are felling adventurous, the ``:path:`` option is optional, and the
extension will guess the path to the library.
.. _installing_pandoc:
Installing pandoc
--------------------------------------------------------------------------------
The recommended way to import dokuwiki to reST is to use
`pandoc <https://pandoc.org>`_.
To ensure a up-to date version, considering installing from source:
.. code::
curl --proto '=https' --tlsv1.2 -sSf https://get-ghcup.haskell.org | sh
cabal v2-update
cabal v2-install pandoc-cli
If custom pandoc haskell filters are needed, also install as a library:
.. code::
cabal v2-install --lib pandoc-types --package-env .
The tested *pandoc* version is 3.1.5, with *pandoc-types* version 2.13.

162
docs/extensions/adi_hdl_parser.py Normal file
View File

@ -0,0 +1,162 @@
from docutils import nodes
from docutils.statemachine import ViewList
from docutils.parsers.rst import Directive, directives
from sphinx.util.nodes import nested_parse_with_titles
from sphinx.util import logging
import os.path
logger = logging.getLogger(__name__)
class node_parameters(nodes.Structural, nodes.Element):
pass
class directive_parameters(Directive):
required_arguments = 0
optional_arguments = 0
final_argument_whitespace = True
option_spec = {'path': directives.unchanged}
has_content = True
add_index = True
current_doc = ''
def warning(self, msg):
logger.warning(msg + f" Current file: {self.current_doc}")
def table_parameters(self, path, content):
description = {}
tag = ''
for line in content:
if line.startswith('* -'):
tag = line[line.find('* -')+3:].split()[0]
description[tag] = []
else:
description[tag].append(line)
for tag in description:
description[tag] = ' '.join(description[tag]).strip().replace('- ', '', 1)
table = nodes.table()
parameters = {}
full_path = path+'/'+path[path.rfind('/')+1:]+'_hw.tcl'
if not os.path.isfile('../'+full_path):
self.warning(f"{full_path} does not exist!")
return table
with open('../'+full_path, 'r') as file:
for line in file:
line = line.strip()
if line.startswith('ad_ip_parameter'):
line_ = line.split(' ', 4)
if len(line_) == 4:
line_.append('')
_, name, type_, default, comment = line_
comment = comment.replace('#','',1).strip()
if comment != '' and comment[-1] != '.':
comment += '.'
parameters[name] = {'type':type_, 'default':default, 'comment':comment}
for tag in description:
if tag not in parameters:
self.warning(f"{tag} does not exist in {full_path}!")
elif parameters[tag]['comment'] != '':
description[tag] = ' '.join([parameters[tag]['comment'], description[tag]])
tgroup = nodes.tgroup(cols=4)
for _ in range(4):
colspec = nodes.colspec(colwidth=1)
tgroup.append(colspec)
table += tgroup
thead = nodes.thead()
tgroup += thead
row = nodes.row()
for header_name in ["Name", "Description", "Type", "Default Value"]:
entry = nodes.entry()
entry += nodes.paragraph(text=header_name)
row += entry
thead.append(row)
rows = []
for key in parameters:
row = nodes.row()
entry = nodes.entry()
entry += nodes.literal(text="{:s}".format(key))
row += entry
entry = nodes.entry()
if key in description:
rst = ViewList()
rst.append(description[key], "virtual_"+path, 0)
node = nodes.section()
node.document = self.state.document
nested_parse_with_titles(self.state, rst, node)
entry += node
else:
entry += ''
row += entry
for tag in ['type', 'default']:
entry = nodes.entry()
entry += nodes.paragraph(text=parameters[key][tag].title())
row += entry
rows.append(row)
tbody = nodes.tbody()
tbody.extend(rows)
tgroup += tbody
return table
def guess_path(self):
path = self.current_doc
for key in ['library', 'projects']:
start_index = path.find(key)
if start_index != -1:
break
end_index = path.rfind('.')
return path[start_index:end_index]
def run(self):
env = self.state.document.settings.env
self.current_doc = env.doc2path(env.docname)
node = node_parameters()
if 'path' not in self.options:
path = self.guess_path()
if not os.path.isdir('../'+path):
self.warning(f"Guessed path {path}, but it does not exist, set the path option explicitely!")
return [ node ]
else:
path = self.options['path']
if not os.path.isdir('../'+path):
self.warning(f"Path {path} does not exist!")
return [ node ]
node_table = nodes.section(ids=["hdl-parameters"])
node_table += self.table_parameters(path, self.content)
node += node_table
return [ node ]
def visit_node_parameters(self, node):
pass
def depart_node_parameters(self, node):
pass
def setup(app):
app.add_directive('hdl-parameters', directive_parameters)
app.add_node(node_parameters,
html=(visit_node_parameters, depart_node_parameters),
latex=(visit_node_parameters, depart_node_parameters),
text=(visit_node_parameters, depart_node_parameters))
return {
'version': '0.1',
'parallel_read_safe': True,
'parallel_write_safe': True,
}

107
docs/extensions/adi_links.py Normal file
View File

@ -0,0 +1,107 @@
from docutils import nodes
import subprocess
# Default values
dft_url_datasheet = 'https://www.analog.com/media/en/technical-documentation/data-sheets/'
dft_url_dokuwiki = 'https://wiki.analog.com'
dft_url_ez = 'https://ez.analog.com'
dft_url_git = 'https://github.com/analogdevicesinc'
dft_url_part = 'https://www.analog.com/products'
dft_url_xilinx = 'https://www.xilinx.com'
def get_url_config(name, inliner):
app = inliner.document.settings.env.app
try:
if not eval("app.config.url_"+name):
raise AttributeError
except AttributeError as err:
raise ValueError(str(err))
return eval("app.config.url_"+name)
def datasheet():
def role(name, rawtext, text, lineno, inliner, options={}, content=[]):
if text.find(':') in [0, -1]:
url = get_url_config('datasheet', inliner) + '/' + part_id + '.pdf'
else:
anchor = text[text.find(':')+1:]
part_id = text[0:text.find(':')]
url = get_url_config('datasheet', inliner) + '/' + part_id + '.pdf#' + anchor
node = nodes.reference(rawtext, part_id + " datasheet", refuri=url, **options)
return [node], []
return role
def dokuwiki():
def role(name, rawtext, text, lineno, inliner, options={}, content=[]):
path = text[text.find(':')+1:]
name = path[path.rfind('/')+1:] if text.find(':') in [0, -1] else text[0:text.find(':')]
url = get_url_config('dokuwiki', inliner) + '/' + path
node = nodes.reference(rawtext, name, refuri=url, **options)
return [node], []
return role
def ez():
def role(name, rawtext, text, lineno, inliner, options={}, content=[]):
url = get_url_config('ez', inliner) + '/' + text
node = nodes.reference(rawtext, "EngineerZone", refuri=url, **options)
return [node], []
return role
def get_active_branch_name():
branch = subprocess.run(['git', 'branch', '--show-current'], capture_output=True)
return branch.stdout.decode('utf-8').replace('\n','')
def git(repo, alt_name):
def role(name, rawtext, text, lineno, inliner, options={}, content=[]):
url = get_url_config('git', inliner) + '/' + repo
if text == '/':
name = "ADI " + alt_name + " repository"
node = nodes.reference(rawtext, name, refuri=url, **options)
else:
branch = get_active_branch_name() if text.find(':') in [0, -1] else text[0:text.find(':')]
path = text[text.find(':')+1:]
url = url + '/blob/' + branch + '/' + path
node = nodes.reference(rawtext, path[path.rfind('/')+1:], refuri=url, **options)
return [node], []
return role
def part():
def role(name, rawtext, text, lineno, inliner, options={}, content=[]):
part_name = text[text.find(':')+1:]
part_id = part_name if text.find(':') in [0, -1] else text[0:text.find(':')]
url = get_url_config('part', inliner) + '/' + part_id + '.html'
node = nodes.reference(rawtext, part_name, refuri=url, **options)
return [node], []
return role
def xilinx():
def role(name, rawtext, text, lineno, inliner, options={}, content=[]):
name = text[text.rfind('/')+1:] if text.find(':') in [0, -1] else text[0:text.find(':')]
path = text[text.find(':')+1:]
url = get_url_config('xilinx', inliner) + '/' + path
node = nodes.reference(rawtext, name, refuri=url, **options)
return [node], []
return role
def setup(app):
app.add_role("datasheet", datasheet())
app.add_role("dokuwiki", dokuwiki())
app.add_role("ez", ez())
app.add_role("git-hdl", git('hdl', "HDL"))
app.add_role("git-testbenches", git('testbenches', "Testbenches"))
app.add_role("git-linux", git('linux', "Linux"))
app.add_role("part", part())
app.add_role("xilinx", xilinx())
app.add_config_value('url_datasheet', dft_url_datasheet, 'env')
app.add_config_value('url_dokuwiki', dft_url_dokuwiki, 'env')
app.add_config_value('url_ez', dft_url_ez, 'env')
app.add_config_value('url_git', dft_url_git, 'env')
app.add_config_value('url_part', dft_url_part, 'env')
app.add_config_value('url_xilinx', dft_url_xilinx, 'env')
return {
'version': '0.1',
'parallel_read_safe': True,
'parallel_write_safe': True,
}

40
docs/index.rst Executable file
View File

@ -0,0 +1,40 @@
:hide-toc:
HDL Reference Designs
===============================================================================
.. toctree::
:caption: Libraries
:hidden:
library/spi_engine/index
library/axi_dmac/index
.. toctree::
:caption: Contributing
:hidden:
contributing/guidelines
.. toctree::
:caption: Appendix
:hidden:
appendix/glossary
appendix/bibliography
.. attention::
Work-in-progress, not all content available at the
`wiki <https://wiki.analog.com/resources/fpga/docs/build>`_
have been imported yet.
.. image:: sources/HDL_logo.svg
:align: center
:scale: 100%
`Analog Devices Inc. <https://www.analog.com>`_
HDL libraries and projects for various reference design and prototyping systems.
This repository contains HDL code (Verilog or VHDL) and the required Tcl scripts
to create and build a specific FPGA example design using Xilinx and/or Intel tool
chain.

125
docs/library/axi_dmac/block_diagram.svg Normal file
View File

@ -0,0 +1,125 @@
<svg width="585" height="245" preserveAspectRatio="xMidYMid slice" version="1.1" viewBox="0 0 585 245" xmlns="http://www.w3.org/2000/svg">
<defs>
<marker id="h" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="i" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="j" overflow="visible" orient="auto">
<path transform="scale(-.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="s" overflow="visible" orient="auto">
<path transform="scale(-.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="k" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="l" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="m" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="n" overflow="visible" orient="auto">
<path transform="scale(-.2)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="a" overflow="visible" orient="auto">
<path transform="scale(-.2)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="b" overflow="visible" orient="auto">
<path transform="scale(.2)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="c" overflow="visible" orient="auto">
<path transform="scale(.2)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="p" overflow="visible" orient="auto">
<path transform="scale(.2)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="r" overflow="visible" orient="auto">
<path transform="scale(-.2)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="d" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="e" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="f" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="g" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="q" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<linearGradient id="o" x1="88.359" x2="117.89" y1="88.837" y2="88.837" gradientUnits="userSpaceOnUse">
<stop stop-color="#fce94f" offset="0"/>
<stop stop-color="#729fcf" offset="1"/>
</linearGradient>
</defs>
<g transform="matrix(4 0 0 4 -117.17 -304.15)">
<rect x="54.052" y="76.302" width="97.349" height="53.988" fill="#d3d7cf" fill-rule="evenodd" stroke="#000" stroke-width=".52917"/>
<rect x="120.14" y="118.32" width="28.324" height="8.6862" fill="#fcaf3e" fill-rule="evenodd" stroke="#000" stroke-width=".52917"/>
<g transform="translate(-.53474 -.4009)">
<rect x="88.624" y="82.623" width="28.999" height="12.428" fill="url(#o)" fill-rule="evenodd" stroke="#000" stroke-width=".52917"/>
<text x="103.00304" y="88.128853" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" text-anchor="middle" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="103.00304" y="88.128853" text-align="center">Store-and-forward</tspan><tspan x="103.00304" y="91.436142" text-align="center">Data Buffer</tspan></text>
</g>
<g font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px">
<text x="126.37469" y="123.3473" style="line-height:125%" xml:space="preserve"><tspan x="126.37469" y="123.3473" stroke-width=".26458px">Register Map</tspan></text>
<text x="119.46967" y="135.42929" style="line-height:125%" xml:space="preserve"><tspan x="119.46967" y="135.42929" stroke-width=".26458px">S_AXI</tspan></text>
<text x="129.22504" y="135.49905" style="line-height:125%" xml:space="preserve"><tspan x="129.22504" y="135.49905" stroke-width=".26458px">s_axi_aclk</tspan></text>
<text x="144.32582" y="135.49905" style="line-height:125%" xml:space="preserve"><tspan x="144.32582" y="135.49905" stroke-width=".26458px">irq</tspan></text>
</g>
<g transform="translate(-2.3947 -.19646)">
<rect x="92.956" y="118.52" width="22.985" height="8.6862" fill="#ad7fa8" fill-rule="evenodd" stroke="#000" stroke-width=".52917"/>
<text x="95.548859" y="123.54207" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="95.548859" y="123.54207" stroke-width=".26458px">Transfer queue</tspan></text>
</g>
<g transform="translate(-.00019488 -.8367)">
<rect x="59.148" y="80.92" width="18.041" height="16.704" fill="#fce94f" fill-rule="evenodd" stroke="#000" stroke-width=".52917"/>
<text x="68.105659" y="86.876122" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" text-anchor="middle" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="68.105659" y="86.876122" text-align="center">Source</tspan><tspan x="68.105659" y="90.183411" text-align="center">Data</tspan><tspan x="68.105659" y="93.4907" text-align="center">Interface</tspan></text>
</g>
<g transform="translate(68.822 -.8367)">
<rect x="59.148" y="80.92" width="18.041" height="16.704" fill="#729fcf" fill-rule="evenodd" stroke="#000" stroke-width=".52917"/>
<text x="68.105659" y="86.911003" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" text-anchor="middle" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="68.105659" y="86.911003" text-align="center">Destination</tspan><tspan x="68.105659" y="90.218292" text-align="center">Data</tspan><tspan x="68.105659" y="93.525581" text-align="center">Interface</tspan></text>
</g>
<g fill="none" stroke="#000">
<g stroke-width=".8">
<path d="m77.909 88.436h7.0159" marker-end="url(#q)"/>
<path d="m117.73 88.436h7.0159" marker-end="url(#g)"/>
<path d="m146.6 91.838h7.0159" marker-end="url(#f)"/>
<path d="m49.178 92.405h7.0159" marker-end="url(#e)"/>
</g>
<path d="m122.86 128.82v3.1851" marker-end="url(#p)" marker-start="url(#r)" stroke-width=".79375"/>
<g stroke-width=".79375">
<path d="m135.05 132.81v-4.154" marker-end="url(#c)" stroke-linecap="square"/>
<path d="m145.92 128.22v4.2876" marker-end="url(#b)" stroke-linecap="square"/>
<path d="m115.81 122.66h3.0711" marker-start="url(#a)"/>
</g>
</g>
<text x="156.62027" y="89.125519" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="156.62027" y="89.125519">AXI-MM /</tspan><tspan x="156.62027" y="92.432816">AXI-Streaming /</tspan><tspan x="156.62027" y="95.74012">FIFO</tspan></text>
<text x="29.533192" y="89.692482" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="29.533192" y="89.692482">AXI-MM /</tspan><tspan x="29.533192" y="92.999779">AXI-Streaming /</tspan><tspan x="29.533192" y="96.307083">FIFO</tspan></text>
<rect x="89.669" y="99.087" width="24.856" height="13.497" fill="#ad7fa8" fill-rule="evenodd" stroke="#000" stroke-linecap="square" stroke-width=".52917"/>
<path d="m102.51 114.56v3.0711" fill="none" marker-start="url(#n)" stroke="#000" stroke-width=".79375"/>
<g stroke-width=".26458px">
<text x="102.07667" y="105.10083" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" text-anchor="middle" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="102.07667" y="105.10083" text-align="center">Transfer</tspan><tspan x="102.07667" y="108.40813" text-align="center">management</tspan></text>
<path d="m123.27 117.71v-7.2403h-7.2761" fill="none" marker-end="url(#d)" stroke="#000"/>
<text x="116.81636" y="112.55849" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="116.81636" y="112.55849" font-size="1.7639px" stroke-width=".26458px">Control</tspan></text>
<path d="m115.18 108.44h10.307v8.6624" fill="none" marker-end="url(#m)" stroke="#000"/>
<text x="116.84208" y="107.68154" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="116.84208" y="107.68154" font-size="1.7639px" stroke-width=".26458px">Status</tspan></text>
<path d="m115.73 103.36h21.6v-5.2118" fill="none" marker-end="url(#k)" stroke="#000"/>
<path d="m88.565 103.36h-20.747v-5.2118" fill="none" marker-end="url(#l)" stroke="#000"/>
<text x="119.1261" y="105.23447" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="119.1261" y="105.23447" font-size="1.7639px" stroke-width=".26458px">Transfer request</tspan></text>
<text x="72.363274" y="105.23447" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="72.363274" y="105.23447" font-size="1.7639px" stroke-width=".26458px">Transfer request</tspan></text>
<path d="m87.931 101.49h-17.974v-3.8754" fill="none" marker-start="url(#s)" stroke="#000"/>
<text x="71.709557" y="100.62407" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="71.709557" y="100.62407" font-size="1.7639px" stroke-width=".26458px">Transfer response</tspan></text>
<path d="m116.48 101.49h17.974v-3.8754" fill="none" marker-start="url(#j)" stroke="#000"/>
<text x="118.47239" y="100.62407" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="118.47239" y="100.62407" font-size="1.7639px" stroke-width=".26458px">Transfer response</tspan></text>
</g>
<path d="m49.947 84.609h7.0159" fill="none" marker-end="url(#i)" stroke="#000" stroke-width=".52917"/>
<text x="41.117294" y="85.428101" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="41.117294" y="85.428101" stroke-width=".26458px">src_clk</tspan></text>
<path d="m155.32 84.042h-7.0159" fill="none" marker-end="url(#h)" stroke="#000" stroke-width=".52917"/>
<text x="155.82919" y="84.861137" fill="#000000" font-family="'Liberation Sans'" font-size="2.6458px" letter-spacing="0px" stroke-width=".26458px" word-spacing="0px" style="line-height:125%" xml:space="preserve"><tspan x="155.82919" y="84.861137" stroke-width=".26458px">dest_clk</tspan></text>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 12 KiB

742
docs/library/axi_dmac/index.rst Normal file
View File

@ -0,0 +1,742 @@
High-Speed DMA Controller
================================================================================
The AXI DMAC is a high-speed, high-throughput, general purpose DMA controller
intended to be used to transfer data between system memory and other peripherals
like high-speed converters.
Features
--------------------------------------------------------------------------------
- Supports multiple interface types
- AXI3/4 memory mapped
- AXI4 Streaming
- ADI FIFO interface
- Zero-latency transfer switch-over architecture
- Allows **continuous** high-speed streaming
- Cyclic transfers
- 2D transfers
Utilization
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Device Family
- LUTs
- FFs
* - Intel Arria 10
- TBD
- TBD
* - Xilinx Artix 7
- TBD
- TBD
* - Xilinx Kintex 7
- TBD
- TBD
* - Xilinx Virtex 7
- TBD
- TBD
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/axi_dmac/axi_dmac.v`
- Verilog source for the peripheral.
Block Diagram
--------------------------------------------------------------------------------
.. image:: block_diagram.svg
:alt: AXI DMAC block diagram
:align: center
Configuration Parameters
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
- Default
* - ``ID``
- Instance identification number.
- 0
* - ``DMA_DATA_WIDTH_SRC``
- Data path width of the source interface in bits.
- 64
* - ``DMA_DATA_WIDTH_DEST``
- Data path width of the destination interface in bits.
- 64
* - ``DMA_LENGTH_WIDTH``
- Width of transfer length control register in bits.
Limits length of the transfers to 2*\*\ ``DMA_LENGTH_WIDTH``.
- 24
* - ``DMA_2D_TRANSFER``
- Enable support for 2D transfers.
- 1
* - ``ASYNC_CLK_REQ_SRC``
- Whether the request and source clock domains are asynchronous.
- 1
* - ``ASYNC_CLK_SRC_DEST``
- Whether the source and destination clock domains are asynchronous.
- 1
* - ``ASYNC_CLK_DEST_REQ``
- Whether the destination and request clock domains are asynchronous.
- 1
* - ``AXI_SLICE_DEST``
- Whether to insert a extra register slice on the source data path.
- 0
* - ``AXI_SLICE_SRC``
- Whether to insert a extra register slice on the destination data path.
- 0
* - ``SYNC_TRANSFER_START``
- Enable the transfer start synchronization feature.
- 0
* - ``CYCLIC``
- Enable support for Cyclic transfers.
- 1
* - ``DMA_AXI_PROTOCOL_SRC``
- AXI protocol version of the source interface (0 = AXI4, 1 = AXI3).
- 0
* - ``DMA_AXI_PROTOCOL_DEST``
- AXI protocol version of the destionation interface (0 = AXI4, 1 = AXI3).
- 0
* - ``DMA_TYPE_SRC``
- Interface type for the source interface
(0 = AXI-MM, 1 = AXI-Streaming, 2 = ADI-FIFO).
- 2
* - ``DMA_TYPE_DEST``
- Interface type for the destination interface
(0 = AXI-MM, 1 = AXI-Streaming, 2 = ADI-FIFO).
- 0
* - ``DMA_AXI_ADDR_WIDTH``
- Maximum address width for AXI interfaces.
- 32
* - ``MAX_BYTES_PER_BURST``
- Maximum size of bursts in bytes. Must be power of 2 in a range of 2
beats to 4096 bytes
The size of the burst is limited by the largest burst that both source
and destination supports. This depends on the selected protocol.
For AXI3 the maximum beats per burst is 16, while for AXI4 is 256. For
non AXI interfaces the maximum beats per burst is in theory unlimited
but it is set to 1024 to provide a reasonable upper threshold.
This limitation is done internally in the core.
- 128
* - ``FIFO_SIZE``
- Size of the store-and-forward memory in bursts. Size of a burst is
defined by the ``MAX_BYTES_PER_BURST`` parameter. Must be power of 2 in
the range of 2 to 32.
- 4
* - ``DISABLE_DEBUG_REGISTERS``
- Disable debug registers.
- 0
* - ``ENABLE_DIAGNOSTICS_IF``
- Add insight into internal operation of the core, for debug purposes
only.
- 0
Interface
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Type
- Description
* - ``s_axi_aclk``
- Clock
- All ``s_axi`` signals and ``irq`` are synchronous to this clock.
* - ``s_axi_aresetn``
- Synchronous active low reset
- Resets the internal state of the peripheral.
* - ``s_axi``
- AXI4-Lite bus slave
- Memory mapped AXI-lite bus that provides access to modules register map.
* - ``irq``
- Level-High Interrupt
- Interrupt output of the module. Is asserted when at least one of the
modules interrupt is pending and enabled.
* - ``m_src_axi_aclk``
- Clock
- The ``m_src_axi`` interface is synchronous to this clock.
Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-MM (0).
* - ``m_src_axi_aresetn``
- Synchronous active low reset
- Reset for the ``m_src_axi`` interface.
Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-MM (0).
* - ``m_src_axi``
- AXI3/AXI4 bus master
-
* - ``m_dest_axi_aclk``
- Clock
- The ``m_src_axi`` interface is synchronous to this clock.
Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
* - ``m_dest_axi_aresetn``
- Synchronous active low reset
- Reset for the ``m_dest_axi`` interface.
Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-MM (0).
* - ``m_dest_axi``
- AXI3/AXI4 bus master
-
* - ``s_axis_aclk``
- Clock
- The ``s_axis`` interface is synchronous to this clock.
Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-Streaming
(1).
* - ``s_axis``
- AXI-streaming bus slave
-
Only present when ``DMA_TYPE_SRC`` parameter is set to AXI-Streaming
(1).
* - ``m_axis_aclk``
- Clock
- The ``m_axis`` interface is synchronous to this clock.
Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-Streaming
(1).
* - ``m_axis``
- AXI-streaming bus master
- Only present when ``DMA_TYPE_DEST`` parameter is set to AXI-Streaming
(1).
* - ``fifo_wr_clk``
- Clock
- The ``fifo_wr`` interface is synchronous to this clock.
Only present when ``DMA_TYPE_SRC`` parameter is set to FIFO (2).
* - ``fifo_wr``
- FIFO write interface
-
Only present when ``DMA_TYPE_SRC`` parameter is set to FIFO (2).
* - ``fifo_rd_clk``
- Clock
- The ``fifo_rd`` interface is synchronous to this clock.
Only present when ``DMA_TYPE_DEST`` parameter is set to FIFO (2).
* - ``fifo_rd``
- FIFO read interface
- Only present when ``DMA_TYPE_DEST`` parameter is set to FIFO (2).
* - ``dest_diag_level_bursts``
- Diagnostics interface
- Only present when ``ENABLE_DIAGNOSTICS_IF`` parameter is set.
Register Map
--------------------------------------------------------------------------------
.. csv-table::
:file: regmap.csv
:class: regmap
:header-rows: 2
.. list-table::
:widths: 10 20 70
:header-rows: 1
* - Access Type
- Name
- Description
* - RO
- Read-only
- Reads will return the current register value. Writes have no effect.
* - RW
- Read-write
- Reads will return the current register value. Writes will change the
current register value.
* - RW1C
- Write-1-to-clear
- Reads will return the current register value. Writing the register will
clear those bits of the register which were set to 1 in the value written.
Bits are set by hardware.
* - RW1S
- Write-1-to-set
- Reads will return the current register value. Writing the register will
set those bits of the register which were set to 1 in the value written.
Bits are cleared by hardware.
* - V
- Volatile
- The V suffix indicates that the register is volatile and its content
might change without software interaction. The value of registers without
the volatile designation will not change without an explicit write done
by software.
Theory of Operation
--------------------------------------------------------------------------------
HDL Synthesis Settings
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Sizing of the internal store-and-forward data buffer
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
An internal buffer is used to store data from the source interface before it is
forwarded to the destination once that can accept it. The purpose of the buffer
is to even out the rate mismatches between the source and destination. e.g if
the destination is a FIFO interface with a fixed data rate and the source is a
MM interface, the intent is to keep the buffer as full as possible so in case of
the MM interface is not ready data can be still provided to the destination
without risking an underflow. Similarly in case the destination is a MM
interface and the source a FIFO interface with a fixed data rate, the intent is
to keep the buffer as empty as possible so in case the MM interface is not ready
data can be still accepted from the source without risking an overflow.
The size of the buffer in bytes is determined by the synthesis parameters of the
module and it is equal to ``FIFO_SIZE`` \* ``MAX_BYTES_PER_BURST``
The width of the buffer is sized to be the largest width from the source and
destination interfaces.
- BUFFER_WIDTH_IN_BYTES =
MAX(``DMA_DATA_WIDTH_SRC``,\ ``DMA_DATA_WIDTH_DEST``)/8
- BUFFER_DEPTH = ``FIFO_SIZE``\ \*\ ``MAX_BYTES_PER_BURST`` /
BUFFER_WIDTH_IN_BYTES
Interfaces and Signals
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Register Map Configuration Interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The register map configuration interface can be accessed through the AXI4-Lite
``S_AXI`` interface. The interface is synchronous to the ``s_axi_aclk``. The
``s_axi_aresetn`` signal is used to reset the peripheral and should be asserted
during system startup until the ``s_axi_aclk`` is active and stable.
De-assertion of the reset signal should by synchronous to ``s_axi_aclk``.
Data Interfaces
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
AXI-Streaming slave
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
The interface back-pressures through the ``s_axis_ready`` signal. If the core is
in the idle state the ``s_axis_ready`` signal will stay low until a descriptor
is submitted. The ``s_axis_ready`` will go low once the internal buffer of the
core is full. It will go high only after enough space is available to store at
least a burst (``MAX_BYTES_PER_BURST`` bytes); Once the current transfer is
finished and a new descriptor was not submitted the ``s_axis_ready`` will go
low. The ``s_axis_ready`` will go low also when the TLAST is used that asserts
unexpectedly. Unexpectedly means that the transfer length defined by TLAST is
shorter than the transfer length programmed in the descriptor (``X_LENGTH``
register). If the next descriptor was already submitted the ``s_axis_ready``
will assert within few cycles, in other hand will stay low until a new
descriptor is submitted.
The ``xfer_req`` is asserted once a transfer is submitted to the descriptor
queue and stays high until all data from the current transfer is received/send
through the AXI Stream/FIFO interface. If during the current transfer another
descriptor is queued (submitted) it will stay high and so on.
Configuration Interface
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The peripheral features a register map configuration interface that can be
accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to
configure the peripherals operational parameters, query the current status of
the device and query the features supported by the device.
Peripheral Identification
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The peripheral contains multiple registers that allow the identification of the
peripheral as well as discovery of features that were configured at HDL
synthesis time. Apart from the ``SCRATCH`` register all registers in this
section are read only and writes to them will be ignored.
The ``VERSION`` (``0x000``) register contains the version of the peripheral. The
version determines the register map layout and general features supported by the
peripheral. The version number follows `semantic versioning <http://semver.org/>`_.
Increments in the major number indicate backwards incompatible changes, increments
in the minor number indicate backwards compatible changes, patch letter increments
indicate fixed incorrect behavior.
The ``PERIPHERAL_ID`` (``0x004``) register contains the value of the ``ID`` HDL
configuration parameter that was set during synthesis. Its primary function is
to allow to distinguish between multiple instances of the peripheral in the same
design.
The ``SCRATCH`` (``0x008``) register is a general purpose 32-bit register that
can be set to an arbitrary values. Reading the register will yield the value
previously written (The value will be cleared when the peripheral is reset).
It's content does not affect the operation of the peripheral. It can be used by
software to test whether the register map is accessible or store custom
peripheral associated data.
The ``IDENTIFICATION`` (``0x00c``) register contains the value of ``"DMAC"``.
This value is unique to this type of peripheral and can be used to ensure that
the peripheral exists at the expected location in the memory mapped IO register
space.
Interrupt Handling
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Interrupt processing is handled by three closely related registers. All three
registers follow the same layout, each bit in the register corresponds to one
particular interrupt.
When an interrupt event occurs it is recorded in the ``IRQ_SOURCE`` (``0x088``)
register. For a recorded interrupt event the corresponding bit is set to 1. If
an interrupt event occurs while the bit is already set to 1 it will stay set to
1.
The ``IRQ_MASK`` (``0x080``) register controls how recorded interrupt events
propagate. An interrupt is considered to be enabled if the corresponding bit in
the ``IRQ_MASK`` register is set to 0, it is considered to be disabled if the
bit is set to 1.
Disabling an interrupt will not prevent it from being recorded, but only its
propagation. This means if an interrupt event was previously recorded while the
interrupt was disabled and the interrupt is being enabled the interrupt event
will then propagate.
An interrupt event that has been recorded and is enabled propagates to the
``IRQ_PENDING`` (``0x084``) register. The corresponding bit for such an
interrupt will read as 1. Disabled or interrupts for which no events have been
recorded will read as 0. Also if at least one interrupt has been recorded and is
enabled the external ``irq`` signal will be asserted to signal the IRQ event to
the upstream IRQ controller.
A recorded interrupt event can be cleared (or acknowledged) by writing a 1 to
the corresponding bit to either the ``IRQ_SOURCE`` or ``IRQ_PENDING`` register.
It is possible to clear multiple interrupt events at the same time by setting
multiple bits in a single write operation.
For more details regarding interrupt operation see the :ref:`axi_dmac interrupts`.
Transfer Configuration
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The ``DEST_ADDRESS`` (``0x410``) register contains the destination address of
the transfer. The address must be aligned to the destination bus width.
Non-aligned addresses will be automatically aligned internally by setting the
LSBs to 0. This register is only valid if the DMA channel has been configured
for write to memory support.
The ``SRC_ADDRESS`` (``0x414``) register contains the source address of the
transfer. The address must be aligned to the source bus width. Non-aligned
addresses will be automatically aligned internally by setting the LSBs to 0.
This register is only valid if the DMA channel has been configured for write
from memory support.
The ``X_LENGTH`` (``0x418``) register contains the number of bytes to transfer
per row. The number of bytes is equal to the value of the register + 1 (E.g. a
value of 0x3ff means 0x400 bytes).
The ``Y_LENGTH`` (``0x41C``) register contains the number of rows to transfer.
The number of rows is equal to the value of the register + 1 (E.g. a value of
1079 means 1080 rows). This register is only valid if the DMA channel has been
configured with 2D transfer support. If 2D transfer support is disabled the
number of rows is always 1 per transfer.
The ``SRC_STRIDE`` (``0x424``) and ``DEST_STRIDE`` (``0x420``) registers contain
the number of bytes between the start of one row and the next row. Needs to be
aligned to the bus width. This field is only valid if the DMA channel has been
configured with 2D transfer support.
The total number of bytes transferred is equal to (``X_LENGTH`` + ``1``) \*
(``Y_LENGTH`` + ``1``).
The ``FLAGS`` (``0x40C``) register controls the behavior of the transfer.
- If the ``CYCLIC`` (``[0]``) bit is set the transfer will run in
:ref:`axi_dmac cyclic-transfers`.
- If the ``TLAST`` (``[1]``) bit is set the TLAST signal will be asserted
during the last beat of the AXI Stream transfer.
Transfer Submission
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Writing a 1 to the ``TRANSFER_SUBMIT`` (``0x408``) register queues a new
transfer. If the internal transfer queue is full the ``TRANSFER_SUBMIT`` bit
will stay asserted until room becomes available, the bit transitions back to 0
once the transfer has been queued. Writing a 0 to this register has no effect.
Writing a 1 to the register while it is already 1 will also have no effect. When
submitting a new transfer software should always check that the
``TRANSFER_SUBMIT`` [0] bit is 0 before setting it, otherwise the transfer will
not be queued.
If the DMA channel is disabled (``ENABLE`` control bit is set to 0) while a
queuing operation is in progress it will be aborted and the ``TRANSFER_SUBMIT``
bit will de-assert.
The ``TRANSFER_ID`` (``0x404``) register contains the ID of the next transfer.
The ID is generated by the DMA controller and can be used to check if a transfer
has been completed by checking the corresponding bit in the ``TRANSFER_DONE``
(``0x428``) register. The contents of this register is only valid if
``TRANSFER_SUBMIT`` is 0. Software should read this register before asserting
the ``TRANSFER_SUBMIT`` bit.
Transfer Status
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The ``TRANSFER_DONE`` (``0x428``) register indicates whether a submitted
transfer has been completed. Each bit in the register corresponds to transfer
ID. When a new transfer is submitted the corresponding bit in the register is
cleared, once the the transfer has been completed the corresponding bit will be
set.
The ``ACTIVE_TRANSFER_ID`` (``0x42C``) register holds the ID of the currently
active transfer. When no transfer is active the value of register will be equal
to the value of the ``TRANSFER_ID`` (``0x404``) register.
Transfer length reporting
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
When using MM or FIFO source interfaces the amount of data which the core will
transfer is defined by ``X_LENGTH`` and ``Y_LENGTH`` registers in the moment of
the transfer submission. Once the corresponding bit from the ``TRANSFER_DONE``
is set the programmed amount of data is transferred.
When using streaming interface (AXIS) as source, the length of transfers will be
defined by the assertion of ``TLAST`` signal which is unknown at the moment of
transfer submission. In this case ``X_LENGTH`` and ``Y_LENGTH`` specified during
the transfer submission will act as upper limits for the transfer. Transfers
where the TLAST occurs ahead of programmed length will be noted as partial
transfers. If ``PARTIAL_REPORTING_EN`` bit from the ``FLAGS`` register is set,
the length of partial transfers will be recorded and exposed through the
``PARTIAL_TRANSFER_LENGTH`` and ``PARTIAL_TRANSFER_ID`` registers. The
availability of information regarding partial transfers is done through the
``PARTIAL_TRANSFER_DONE`` field of ``TRANSFER_DONE`` register.
During operation the ``TRANSFER_PROGRESS`` register can be consulted to check
the progress of the current transfer. The register presents the number of bytes
the destination accepted during the in progress transfer. This register will be
cleared once the transfer completes. This register should be used for debugging
purposes only.
Transfer Tear-down
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Non-cyclic transfers stop once the programmed amount of data is transferred to
the destination. Cyclic transfers needs to be stopped with software intervention
by setting the ``ENABLE`` control bit to 0. In case if required, non cyclic
transfers can be interrupted in the same way. The transfer tear down is done
gracefully and is done at a burst resolution on MM interfaces and beat
resolution on non-MM interfaces. DMAC shuts down gracefully as fast as possible
while completing all in-progress MM transactions.
Source side: For MM interface once the ``ENABLE`` bit de-asserts the DMAC won't
issue new requests towards the source interface but will wait until all pending
requests are fulfilled by the source. For non-MM interfaces, once the ``ENABLE``
bit de-asserts the DMAC will stop to accept new data. This will lead to partial
bursts in the internal buffer but this data will be cleared/lost once the
destination side completes all pending bursts.
Destination side: For MM interface the DMAC will complete all pending requests
that have been started by issuing the address. For non-MM interfaces once the
``ENABLE`` bit de-asserts the DMAC will stop to drive new data. All the data
from the internal buffer will be cleared/lost. In case of AXIS the DMAC will
wait for data to be accepted if valid is high since it can't just de-assert
valid without breaking the interface semantics
.. _axi_dmac interrupts:
Interrupts
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The DMA controller supports interrupts to allow asynchronous notification of
certain events to the CPU. This can be used as an alternative to busy-polling
the status registers. Two types of interrupt events are implemented by the DMA
controller.
The ``TRANSFER_QUEUED`` interrupt is asserted when a transfer is moved from the
register map to the internal transfer queue. This is equivalent to the
``TRANSFER_SUBMIT`` register transitioning from 1 to 0. Software can use this
interrupt as an indication that the next transfer can be submitted.
Note that a transfer being queued does not mean that it has been started yet. If
other transfers are already queued those will be processed first.
The ``TRANSFER_COMPLETED`` interrupt is asserted when a previously submitted
transfer has been completed. To find out which transfer has been completed the
``TRANSFER_DONE`` register should be checked.
Note that depending on the transfer size and interrupt latency it is possible
for multiple transfers to complete before the interrupt handler runs. In that
case the interrupt handler will only run once. Software should always check all
submitted transfers for completion.
2D Transfers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If the ``DMA_2D_TRANSFER`` HDL synthesis configuration parameter is set the DMA
controller has support for 2D transfers.
A 2D transfer is composed of a number of rows with each row containing a certain
number of bytes. Between each row there might be a certain amount of padding
bytes that are skipped by the DMA.
For 2D transfers the ``X_LENGTH`` register configures the number of bytes per
row and the ``Y_LENGTH`` register configures the number of rows. The
``SRC_STRIDE`` and ``DEST_STRIDE`` registers configure the number of bytes in
between start of two rows.
E.g. the first row will start at the configured source or destination address,
the second row will start at the configured source or destination address plus
the stride and so on.
.. math::
ROW\_SRC\_ADDRESS = SRC\_ADDRESS + SRC\_STRIDE * N
.. math::
ROW\_DEST\_ADDRESS = DEST\_ADDRESS + DEST\_STRIDE * N
If support for 2D transfers is disabled only the X_LENGTH register is
considered and the number of rows per transfer is fixed to 1.
.. _axi_dmac cyclic-transfers:
Cyclic Transfers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If the ``CYCLIC`` HDL synthesis configuration parameter is set the DMA
controller has support for cyclic transfers.
A cyclic transfer once completed will restart automatically with the same
configuration. The behavior of cyclic transfer is equivalent to submitting the
same transfer over and over again, but generates less software management
overhead.
A transfer is cyclic if the ``CYCLIC`` (``[0]``) bit of the ``FLAGS``
(``0x40C``) is set to 1 during transfer submission.
For cyclic transfers no end-of-transfer interrupts will be generated. To stop a
cyclic transfer the DMA channel must be disabled.
Any additional transfers that are submitted after the submission of a cyclic
transfer (and before stopping the cyclic transfer) will never be executed.
Transfer Start Synchronization
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If the transfer start synchronization feature of the DMA controller is enabled
the start of a transfer is synchronized to a flag in the data stream. This is
primarily useful if the data stream does not have any back-pressure and one unit
of data spans multiple beats (e.g. packetized data). This ensures that the data
is properly aligned to the beginning of the memory buffer.
Data that is received before the synchronization flag is asserted will be
ignored by the DMA controller.
For the FIFO write interface the ``fifo_wr_sync`` signal is the synchronization
flag signal. For the AXI-Streaming interface the synchronization flag is carried
in ``s_axis_user[0]``. In both cases the synchronization flag is qualified by
the same control signal as the data.
Diagnostics interface
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
For debug purposes a diagnostics interface is added to the core.
The ``dest_diag_level_bursts`` signal adds insight into the fullness of the
internal memory buffer during operation. The information is exposed in number
of bursts where the size of a burst is defined by the ``MAX_BYTES_PER_BURST``
parameter. The value of ``dest_diag_level_bursts`` increments for each burst
accumulated in the DMACs internal buffer. It decrements once the burst leaves
the DMAC on its destination port. The signal is synchronous to the destination
clock domain (``m_dest_axi_aclk`` or ``m_axis_aclk`` depending on ``DMA_TYPE_DEST``).
Limitations
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
AXI 4kByte Address Boundary
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Software must program the ``SRC_ADDRESS`` and ``DEST_ADDRESS`` registers in such
way that AXI burst won't cross the 4kB address boundary. The following condition
must hold:
* ``MAX_BYTES_PER_BURST`` ≤ 4096;
* ``MAX_BYTES_PER_BURST`` is power of 2;
* ``​SRC/​DEST_ADDRESS`` ​mod ``​MAX_BYTES_PER_BURST`` ​== 0
* ``SRC/DEST_ADDRESS[11:0]`` + MIN(``X_LENGTH``\ +1,\ ``MAX_BYTES_PER_BURST``) ≤ 4096
Address Alignment
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Software must program the ``SRC_ADDRESS`` and ``DEST_ADDRESS``\ registers to be
multiple of the corresponding MM data bus. The following conditions must hold:
* ``SRC_ADDRESS`` MOD (``DMA_DATA_WIDTH_SRC``/8) == 0
* ``DEST_ADDRESS`` MOD (``DMA_DATA_WIDTH_DEST``/8) == 0
Transfer Length Alignment
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Software must program the ``X_LENGTH`` register to be multiple of the widest
data bus. The following condition must hold:
- (``X_LENGTH``\ +1) MOD MAX(``DMA_DATA_WIDTH_SRC``, ``DMA_DATA_WIDTH_DEST``)/8
== 0
This restriction can be relaxed for the memory mapped interfaces. This is done
by partially ignoring data of a beat from/to the MM interface:
- For write access the strobe bits are used to mask out bytes that do not
contain valid data.
- For read access a full beat is read but part of the data is discarded. This
works fine as long as the read access is side effect free. I.e. this method
should not be used to access data from memory mapped peripherals like a FIFO.
E.g. the length alignment requirement of a DMA configured for a 64-bit memory
mapped interface and a 16-bit streaming interface is only 2 bytes instead of 8
bytes.
Note that the address alignment requirement is not affected by this. The address
still needs to be aligned to the width of the MM interface that it belongs to.
Software Support
--------------------------------------------------------------------------------
Analog Devices recommends to use the provided software drivers.
- :dokuwiki:`Analog Device AXI-DMAC DMA Controller Linux Driver:
resources/tools-software/linux-drivers/axi-dmac`
Known Issues
--------------------------------------------------------------------------------
1. When max bytes per burst matches the data width of destination interface an
erroneous extra beat is inserted after every valid beat on the destination side.
Example configuration:
* axi mm -> axi stream
* max bytes per burst = 128
* destination width = 1024 bits
Workaround: increase the max bytes per burst to larger than 128
Technical Support
--------------------------------------------------------------------------------
Analog Devices will provide limited online support for anyone using the core
with Analog Devices components (ADC, DAC, Video, Audio, etc) via the :ez:`fpga`.
Glossary
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Term
- Description
* - beat
- Represents the amount of data that is transferred in one clock cycle.
* - burst
- Represents the amount of data that is transferred in a group of
consecutive beats.
* - partial transfer
- Represents a transfer which is shorter than the programmed length that
is based on the X_LENGTH and Y_LENGTH registers. This can occur on AXIS
source interfaces when TLAST asserts earlier than the programmed
length.

82
docs/library/axi_dmac/regmap.csv Normal file
View File

@ -0,0 +1,82 @@
Address ,,,,,,
DWORD ,BYTE ,Bits ,Name ,Type ,Default ,Description
0x000 ,0x0000 ,,VERSION ,,,Version of the peripheral. Follows semantic versioning. Current version 4.04.61.
,,[31:16] ,VERSION_MAJOR ,RO ,0x04 ,
,,[15:8] ,VERSION_MINOR ,RO ,0x03 ,
,,[7:0] ,VERSION_PATCH ,RO ,0x61 ,
0x001 ,0x0004 ,,PERIPHERAL_ID ,,,
,,[31:0] ,PERIPHERAL_ID ,RO ,ID ,Value of the ID configuration parameter.
0x002 ,0x0008 ,,SCRATCH ,,,
,,[31:0] ,SCRATCH ,RW ,0x00000000 ,Scratch register useful for debug.
0x003 ,0x000c ,,IDENTIFICATION ,,,
,,[31:0] ,IDENTIFICATION ,RO ,0x444D4143 ,"Peripheral identification ('D', 'M', 'A', 'C'). "
0x004 ,0x0010 ,,INTERFACE_DESCRIPTION ,,,
,,[3:0] ,BYTES_PER_BEAT_DEST_LOG2 ,R ,log2(DMA_DATA_WIDTH_DEST/8) ,Width of data bus on destination interface. Log2 of interface data widths in bytes.
,,[5:4] ,DMA_TYPE_DEST ,R ,DMA_TYPE_DEST ,"Value of DMA_TYPE_DEST parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO "
,,[11:8] ,BYTES_PER_BEAT_SRC_LOG2 ,R ,log2(DMA_DATA_WIDTH_SRC/8) ,Width of data bus on source interface. Log2 of interface data widths in bytes.
,,[13:12] ,DMA_TYPE_SRC ,R ,DMA_TYPE_SRC ,"Value of DMA_TYPE_SRC parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO "
,,[19:16] ,BYTES_PER_BURST_WIDTH ,R ,BYTES_PER_BURST_WIDTH ,Value of BYTES_PER_BURST_WIDTH interface parameter. Log2 of the real MAX_BYTES_PER_BURST. The starting address of the transfer must be aligned with MAX_BYTES_PER_BURST to avoid crossing the 4kB address boundary.
0x020 ,0x0080 ,,IRQ_MASK ,,,
,,[1] ,TRANSFER_COMPLETED ,RW ,0x1 ,Masks the TRANSFER_COMPLETED IRQ.
,,[0] ,TRANSFER_QUEUED ,RW ,0x1 ,Masks the TRANSFER_QUEUED IRQ.
0x021 ,0x0084 ,,IRQ_PENDING ,,,
,,[1] ,TRANSFER_COMPLETED ,RW1C ,0x0 ,This bit will be asserted if a transfer has been completed and the TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been transferred or an error occurred during the transfer.
,,[0] ,TRANSFER_QUEUED ,RW1C ,0x0 ,This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in the IRQ_MASK register.
0x022 ,0x0088 ,,IRQ_SOURCE ,,,
,,[1] ,TRANSFER_COMPLETED ,RO ,0x0 ,This bit will be asserted if a transfer has been completed. Either if all bytes have been transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit.
,,[0] ,TRANSFER_QUEUED ,RO ,0x0 ,This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit.
0x100 ,0x0400 ,,CONTROL ,,,
,,[1] ,PAUSE ,RW ,0x0 ,When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again.
,,[0] ,ENABLE ,RW ,0x0 ,When set to 1 the DMA channel is enabled.
0x101 ,0x0404 ,,TRANSFER_ID ,,,
,,[1:0] ,TRANSFER_ID ,RO ,0x00 ,This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0.
0x102 ,0x0408 ,,TRANSFER_SUBMIT ,,,
,,[0] ,TRANSFER_SUBMIT ,RW ,0x00 ,Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled. Writing a 0 to this register has no effect.
0x103 ,0x040c ,FLAGS ,,,,
,,[0] ,CYCLIC ,RW ,CYCLIC ,Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated.
,,[1] ,TLAST ,RW ,0x1 ,When setting this bit for a MM to AXIS transfer the TLAST signal will be asserted during the last beat of the transfer. For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored. After its occurrence all descriptors are ignored until this bit is set.
,,[2] ,PARTIAL_REPORTING_EN ,RW ,0x0 ,When setting this bit the length of partial transfers caused eventually by TLAST will be recorded.
0x104 ,0x0410 ,,DEST_ADDRESS ,,,
,,[31:0] ,DEST_ADDRESS ,RW ,0x00000000 ,This register contains the destination address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for write to memory support.
0x105 ,0x0414 ,,SRC_ADDRESS ,,,
,,[31:0] ,SRC_ADDRESS ,RW ,0x00000000 ,This register contains the source address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for read from memory support.
0x106 ,0x0418 ,,X_LENGTH ,,,
,,[23:0] ,X_LENGTH ,RW ,"{log2(max(
DMA_DATA_WIDTH_SRC,
DMA_DATA_WIDTH_DEST
)/8){1'b1}} ",Number of bytes to transfer - 1.
0x107 ,0x041c ,,Y_LENGTH ,,,
,,[23:0] ,Y_LENGTH ,RW ,0x000000 ,"Number of rows to transfer - 1. Note, this field is only valid if the DMA channel has been configured with 2D transfer support. "
0x108 ,0x0420 ,,DEST_STRIDE ,,,
,,[23:0] ,DEST_STRIDE ,RW ,0x000000 ,"The number of bytes between the start of one row and the next row for the destination address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer support and write to memory support. "
0x109 ,0x0424 ,,SRC_STRIDE ,,,
,,[23:0] ,SRC_STRIDE ,RW ,0x000000 ,"The number of bytes between the start of one row and the next row for the source address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer and read from memory support. "
0x10a ,0x0428 ,,TRANSFER_DONE ,,,If bit x is set in this register the transfer with ID x has been completed. The bit will automatically be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
,,[0] ,TRANSFER_0_DONE ,RO ,0x0 ,If this bit is set the transfer with ID 0 has been completed.
,,[1] ,TRANSFER_1_DONE ,RO ,0x0 ,If this bit is set the transfer with ID 1 has been completed.
,,[2] ,TRANSFER_2_DONE ,RO ,0x0 ,If this bit is set the transfer with ID 2 has been completed.
,,[3] ,TRANSFER_3_DONE ,RO ,0x0 ,If this bit is set the transfer with ID 3 has been completed.
,,[31] ,PARTIAL_TRANSFER_DONE ,RO ,0x0 ,If this bit is set at least one partial transfer was transferred. This field will reset when the ENABLE control bit is reset or when all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and PARTIAL_TRANSFER_ID registers.
0x10b ,0x042c ,,ACTIVE_TRANSFER_ID ,,,
,,[4:0] ,ACTIVE_TRANSFER_ID ,RO ,0x00 ,ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register.
0x10c ,0x0430 ,,STATUS ,,,
,,[31:0] ,RESERVED ,RO ,0x00 ,This register is reserved for future usage. Reading it will always return 0.
0x10d ,0x0434 ,,CURRENT_DEST_ADDRESS ,,,
,,[31:0] ,CURRENT_DEST_ADDRESS ,RO ,0x00 ,Address to which the next data sample is written to. This register is only valid if the DMA channel has been configured for write to memory support.
0x10e ,0x0438 ,,CURRENT_SRC_ADDRESS ,,,
,,[31:0] ,CURRENT_SRC_ADDRESS ,RO ,0x00 ,Address form which the next data sample is read. This register is only valid if the DMA channel has been configured for read from memory support.
0x112 ,0x0448 ,,TRANSFER_PROGRESS ,,,
,,[23:0] ,TRANSFER_PROGRESS ,RO ,0x000000 ,This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only.
0x113 ,0x044c ,,PARTIAL_TRANSFER_LENGTH ,,,
,,[31:0] ,PARTIAL_LENGTH ,RO ,0x000000 ,Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers.
0x114 ,0x0450 ,,PARTIAL_TRANSFER_ID ,,,Must be read after the PARTIAL_TRANSFER_LENGTH registers.
,,[1:0] ,PARTIAL_TRANSFER_ID ,RO ,0x0 ,ID of the transfer that was partial.
0x124 ,0x0490 ,,DEST_ADDRESS_HIGH ,,,
,,[31:0] ,DEST_ADDRESS_HIGH ,RW ,0x00000000 ,This register contains the HIGH segment of the destination address of the transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support.
0x125 ,0x0494 ,,SRC_ADDRESS_HIGH ,,,
,,[31:0] ,SRC_ADDRESS_HIGH ,RW ,0x00000000 ,This register contains the HIGH segment of the source address of the transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
0x126 ,0x0498 ,,CURRENT_DEST_ADDRESS_HIGH ,,,
,,[31:0] ,CURRENT_DEST_ADDRESS_HIGH ,RO ,0x00 ,HIGH segment of the address to which the next data sample is written to. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support.
0x127 ,0x049c ,,CURRENT_SRC_ADDRESS_HIGH ,,,
,,[31:0] ,CURRENT_SRC_ADDRESS_HIGH ,RO ,0x00 ,HIGH segment of the address from which the next data sample is read. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
,,,,,,Tue Mar 14 10:17:59 2023
1 Address
2 DWORD BYTE Bits Name Type Default Description
3 0x000 0x0000 VERSION Version of the peripheral. Follows semantic versioning. Current version 4.04.61.
4 [31:16] VERSION_MAJOR RO 0x04
5 [15:8] VERSION_MINOR RO 0x03
6 [7:0] VERSION_PATCH RO 0x61
7 0x001 0x0004 PERIPHERAL_ID
8 [31:0] PERIPHERAL_ID RO ID Value of the ID configuration parameter.
9 0x002 0x0008 SCRATCH
10 [31:0] SCRATCH RW 0x00000000 Scratch register useful for debug.
11 0x003 0x000c IDENTIFICATION
12 [31:0] IDENTIFICATION RO 0x444D4143 Peripheral identification ('D', 'M', 'A', 'C').
13 0x004 0x0010 INTERFACE_DESCRIPTION
14 [3:0] BYTES_PER_BEAT_DEST_LOG2 R log2(DMA_DATA_WIDTH_DEST/8) Width of data bus on destination interface. Log2 of interface data widths in bytes.
15 [5:4] DMA_TYPE_DEST R DMA_TYPE_DEST Value of DMA_TYPE_DEST parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO
16 [11:8] BYTES_PER_BEAT_SRC_LOG2 R log2(DMA_DATA_WIDTH_SRC/8) Width of data bus on source interface. Log2 of interface data widths in bytes.
17 [13:12] DMA_TYPE_SRC R DMA_TYPE_SRC Value of DMA_TYPE_SRC parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO
18 [19:16] BYTES_PER_BURST_WIDTH R BYTES_PER_BURST_WIDTH Value of BYTES_PER_BURST_WIDTH interface parameter. Log2 of the real MAX_BYTES_PER_BURST. The starting address of the transfer must be aligned with MAX_BYTES_PER_BURST to avoid crossing the 4kB address boundary.
19 0x020 0x0080 IRQ_MASK
20 [1] TRANSFER_COMPLETED RW 0x1 Masks the TRANSFER_COMPLETED IRQ.
21 [0] TRANSFER_QUEUED RW 0x1 Masks the TRANSFER_QUEUED IRQ.
22 0x021 0x0084 IRQ_PENDING
23 [1] TRANSFER_COMPLETED RW1C 0x0 This bit will be asserted if a transfer has been completed and the TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been transferred or an error occurred during the transfer.
24 [0] TRANSFER_QUEUED RW1C 0x0 This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in the IRQ_MASK register.
25 0x022 0x0088 IRQ_SOURCE
26 [1] TRANSFER_COMPLETED RO 0x0 This bit will be asserted if a transfer has been completed. Either if all bytes have been transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit.
27 [0] TRANSFER_QUEUED RO 0x0 This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit.
28 0x100 0x0400 CONTROL
29 [1] PAUSE RW 0x0 When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again.
30 [0] ENABLE RW 0x0 When set to 1 the DMA channel is enabled.
31 0x101 0x0404 TRANSFER_ID
32 [1:0] TRANSFER_ID RO 0x00 This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0.
33 0x102 0x0408 TRANSFER_SUBMIT
34 [0] TRANSFER_SUBMIT RW 0x00 Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled. Writing a 0 to this register has no effect.
35 0x103 0x040c FLAGS
36 [0] CYCLIC RW CYCLIC Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated.
37 [1] TLAST RW 0x1 When setting this bit for a MM to AXIS transfer the TLAST signal will be asserted during the last beat of the transfer. For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored. After its occurrence all descriptors are ignored until this bit is set.
38 [2] PARTIAL_REPORTING_EN RW 0x0 When setting this bit the length of partial transfers caused eventually by TLAST will be recorded.
39 0x104 0x0410 DEST_ADDRESS
40 [31:0] DEST_ADDRESS RW 0x00000000 This register contains the destination address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for write to memory support.
41 0x105 0x0414 SRC_ADDRESS
42 [31:0] SRC_ADDRESS RW 0x00000000 This register contains the source address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for read from memory support.
43 0x106 0x0418 X_LENGTH
44 [23:0] X_LENGTH RW {log2(max( DMA_DATA_WIDTH_SRC, DMA_DATA_WIDTH_DEST )/8){1'b1}} Number of bytes to transfer - 1.
45 0x107 0x041c Y_LENGTH
46 [23:0] Y_LENGTH RW 0x000000 Number of rows to transfer - 1. Note, this field is only valid if the DMA channel has been configured with 2D transfer support.
47 0x108 0x0420 DEST_STRIDE
48 [23:0] DEST_STRIDE RW 0x000000 The number of bytes between the start of one row and the next row for the destination address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer support and write to memory support.
49 0x109 0x0424 SRC_STRIDE
50 [23:0] SRC_STRIDE RW 0x000000 The number of bytes between the start of one row and the next row for the source address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer and read from memory support.
51 0x10a 0x0428 TRANSFER_DONE If bit x is set in this register the transfer with ID x has been completed. The bit will automatically be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
52 [0] TRANSFER_0_DONE RO 0x0 If this bit is set the transfer with ID 0 has been completed.
53 [1] TRANSFER_1_DONE RO 0x0 If this bit is set the transfer with ID 1 has been completed.
54 [2] TRANSFER_2_DONE RO 0x0 If this bit is set the transfer with ID 2 has been completed.
55 [3] TRANSFER_3_DONE RO 0x0 If this bit is set the transfer with ID 3 has been completed.
56 [31] PARTIAL_TRANSFER_DONE RO 0x0 If this bit is set at least one partial transfer was transferred. This field will reset when the ENABLE control bit is reset or when all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and PARTIAL_TRANSFER_ID registers.
57 0x10b 0x042c ACTIVE_TRANSFER_ID
58 [4:0] ACTIVE_TRANSFER_ID RO 0x00 ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register.
59 0x10c 0x0430 STATUS
60 [31:0] RESERVED RO 0x00 This register is reserved for future usage. Reading it will always return 0.
61 0x10d 0x0434 CURRENT_DEST_ADDRESS
62 [31:0] CURRENT_DEST_ADDRESS RO 0x00 Address to which the next data sample is written to. This register is only valid if the DMA channel has been configured for write to memory support.
63 0x10e 0x0438 CURRENT_SRC_ADDRESS
64 [31:0] CURRENT_SRC_ADDRESS RO 0x00 Address form which the next data sample is read. This register is only valid if the DMA channel has been configured for read from memory support.
65 0x112 0x0448 TRANSFER_PROGRESS
66 [23:0] TRANSFER_PROGRESS RO 0x000000 This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only.
67 0x113 0x044c PARTIAL_TRANSFER_LENGTH
68 [31:0] PARTIAL_LENGTH RO 0x000000 Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers.
69 0x114 0x0450 PARTIAL_TRANSFER_ID Must be read after the PARTIAL_TRANSFER_LENGTH registers.
70 [1:0] PARTIAL_TRANSFER_ID RO 0x0 ID of the transfer that was partial.
71 0x124 0x0490 DEST_ADDRESS_HIGH
72 [31:0] DEST_ADDRESS_HIGH RW 0x00000000 This register contains the HIGH segment of the destination address of the transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support.
73 0x125 0x0494 SRC_ADDRESS_HIGH
74 [31:0] SRC_ADDRESS_HIGH RW 0x00000000 This register contains the HIGH segment of the source address of the transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
75 0x126 0x0498 CURRENT_DEST_ADDRESS_HIGH
76 [31:0] CURRENT_DEST_ADDRESS_HIGH RO 0x00 HIGH segment of the address to which the next data sample is written to. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support.
77 0x127 0x049c CURRENT_SRC_ADDRESS_HIGH
78 [31:0] CURRENT_SRC_ADDRESS_HIGH RO 0x00 HIGH segment of the address from which the next data sample is read. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
79 Tue Mar 14 10:17:59 2023

53
docs/library/common/regmap_adc_channel.csv Normal file
View File

@ -0,0 +1,53 @@
Address ,,,,,,
DWORD ,BYTE ,Bits ,Name ,Type ,Default ,Description
0x0100 ,0x0400 ,,REG_CHAN_CNTRL ,,,ADC Interface Control & Status
,,[11] ,ADC_LB_OWR ,RW ,0x0 ,"If set, forces ADC_DATA_SEL to 1, enabling data loopback "
,,[10] ,ADC_PN_SEL_OWR ,RW ,0x0 ,"If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored "
,,[9] ,IQCOR_ENB ,RW ,0x0 ,"if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). "
,,[8] ,DCFILT_ENB ,RW ,0x0 ,"if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). "
,,[6] ,FORMAT_SIGNEXT ,RW ,0x0 ,"if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1). "
,,[5] ,FORMAT_TYPE ,RW ,0x0 ,Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
,,[4] ,FORMAT_ENABLE ,RW ,0x0 ,Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
,,[3] ,RESERVED ,RO ,0x0 ,Reserved for backward compatibility.
,,[2] ,RESERVED ,RO ,0x0 ,Reserved for backward compatibility.
,,[1] ,ADC_PN_TYPE_OWR ,RW ,0x0 ,"If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored "
,,[0] ,ENABLE ,RW ,0x0 ,"If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. "
0x0101 ,0x0404 ,,REG_CHAN_STATUS ,,,ADC Interface Control & Status
,,[12] ,CRC_ERR ,RW1C ,0x0 ,"CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards. "
,,[11:4] ,STATUS_HEADER ,RO ,0x00 ,The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
,,[2] ,PN_ERR ,RW1C ,0x0 ,"PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. "
,,[1] ,PN_OOS ,RW1C ,0x0 ,"PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. "
,,[0] ,OVER_RANGE ,RW1C ,0x0 ,"If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. "
0x0102 ,0x0408 ,,REG_CHAN_RAW_DATA ,,,ADC Raw Data Reading
,,[31:0] ,ADC_READ_DATA[31:0] ,RO ,0x0000 ,Raw data read from the ADC.
0x0104 ,0x0410 ,,REG_CHAN_CNTRL_1 ,,,ADC Interface Control & Status
,,[31:16] ,DCFILT_OFFSET[15:0] ,RW ,0x0000 ,DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
,,[15:0] ,DCFILT_COEFF[15:0] ,RW ,0x0000 ,"DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1). "
0x0105 ,0x0414 ,,REG_CHAN_CNTRL_2 ,,,ADC Interface Control & Status
,,[31:16] ,IQCOR_COEFF_1[15:0] ,RW ,0x0000 ,"IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). "
,,[15:0] ,IQCOR_COEFF_2[15:0] ,RW ,0x0000 ,"IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1). "
0x0106 ,0x0418 ,,REG_CHAN_CNTRL_3 ,,,ADC Interface Control & Status
,,[19:16] ,ADC_PN_SEL[3:0] ,RW ,0x0 ,"Selects the PN monitor sequence type (available only if ADC supports it).
- 0x0: pn9a (device specific, modified pn9)
- 0x1: pn23a (device specific, modified pn23)
- 0x4: pn7 (standard O.150)
- 0x5: pn15 (standard O.150)
- 0x6: pn23 (standard O.150)
- 0x7: pn31 (standard O.150)
- 0x9: pnX (device specific, e.g. ad9361)
- 0x0A: Nibble ramp (Device specific e.g. adrv9001)
- 0x0B: 16 bit ramp (Device specific e.g. adrv9001) "
,,[3:0] ,ADC_DATA_SEL[3:0] ,RW ,0x0 ,Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)
0x0108 ,0x0420 ,,REG_CHAN_USR_CNTRL_1 ,,,ADC Interface Control & Status
,,[25] ,USR_DATATYPE_BE ,RO ,0x0 ,"The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). "
,,[24] ,USR_DATATYPE_SIGNED ,RO ,0x0 ,"The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). "
,,[23:16] ,USR_DATATYPE_SHIFT[7:0] ,RO ,0x00 ,The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
,,[15:8] ,USR_DATATYPE_TOTAL_BITS[7:0] ,RO ,0x00 ,The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
,,[7:0] ,USR_DATATYPE_BITS[7:0] ,RO ,0x00 ,The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109 ,0x0424 ,,REG_CHAN_USR_CNTRL_2 ,,,ADC Interface Control & Status
,,[31:16] ,USR_DECIMATION_M[15:0] ,RW ,0x0000 ,This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
,,[15:0] ,USR_DECIMATION_N[15:0] ,RW ,0x0000 ,This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0110 ,0x0440 ,,REG_* ,,,"Channel 1, similar to register 0x100 to 0x10f. "
0x0120 ,0x0480 ,,REG_* ,,,"Channel 2, similar to register 0x100 to 0x10f. "
0x01F0 ,0x07c0 ,,REG_* ,,,"Channel 15, similar to register 0x100 to 0x10f. "
,,,,,,Tue Mar 14 10:17:59 2023
1 Address
2 DWORD BYTE Bits Name Type Default Description
3 0x0100 0x0400 REG_CHAN_CNTRL ADC Interface Control & Status
4 [11] ADC_LB_OWR RW 0x0 If set, forces ADC_DATA_SEL to 1, enabling data loopback
5 [10] ADC_PN_SEL_OWR RW 0x0 If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
6 [9] IQCOR_ENB RW 0x0 if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
7 [8] DCFILT_ENB RW 0x0 if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
8 [6] FORMAT_SIGNEXT RW 0x0 if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
9 [5] FORMAT_TYPE RW 0x0 Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
10 [4] FORMAT_ENABLE RW 0x0 Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
11 [3] RESERVED RO 0x0 Reserved for backward compatibility.
12 [2] RESERVED RO 0x0 Reserved for backward compatibility.
13 [1] ADC_PN_TYPE_OWR RW 0x0 If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
14 [0] ENABLE RW 0x0 If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.
15 0x0101 0x0404 REG_CHAN_STATUS ADC Interface Control & Status
16 [12] CRC_ERR RW1C 0x0 CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.
17 [11:4] STATUS_HEADER RO 0x00 The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
18 [2] PN_ERR RW1C 0x0 PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.
19 [1] PN_OOS RW1C 0x0 PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.
20 [0] OVER_RANGE RW1C 0x0 If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.
21 0x0102 0x0408 REG_CHAN_RAW_DATA ADC Raw Data Reading
22 [31:0] ADC_READ_DATA[31:0] RO 0x0000 Raw data read from the ADC.
23 0x0104 0x0410 REG_CHAN_CNTRL_1 ADC Interface Control & Status
24 [31:16] DCFILT_OFFSET[15:0] RW 0x0000 DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
25 [15:0] DCFILT_COEFF[15:0] RW 0x0000 DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
26 0x0105 0x0414 REG_CHAN_CNTRL_2 ADC Interface Control & Status
27 [31:16] IQCOR_COEFF_1[15:0] RW 0x0000 IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
28 [15:0] IQCOR_COEFF_2[15:0] RW 0x0000 IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
29 0x0106 0x0418 REG_CHAN_CNTRL_3 ADC Interface Control & Status
30 [19:16] ADC_PN_SEL[3:0] RW 0x0 Selects the PN monitor sequence type (available only if ADC supports it). - 0x0: pn9a (device specific, modified pn9) - 0x1: pn23a (device specific, modified pn23) - 0x4: pn7 (standard O.150) - 0x5: pn15 (standard O.150) - 0x6: pn23 (standard O.150) - 0x7: pn31 (standard O.150) - 0x9: pnX (device specific, e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
31 [3:0] ADC_DATA_SEL[3:0] RW 0x0 Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)
32 0x0108 0x0420 REG_CHAN_USR_CNTRL_1 ADC Interface Control & Status
33 [25] USR_DATATYPE_BE RO 0x0 The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
34 [24] USR_DATATYPE_SIGNED RO 0x0 The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
35 [23:16] USR_DATATYPE_SHIFT[7:0] RO 0x00 The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
36 [15:8] USR_DATATYPE_TOTAL_BITS[7:0] RO 0x00 The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
37 [7:0] USR_DATATYPE_BITS[7:0] RO 0x00 The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
38 0x0109 0x0424 REG_CHAN_USR_CNTRL_2 ADC Interface Control & Status
39 [31:16] USR_DECIMATION_M[15:0] RW 0x0000 This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
40 [15:0] USR_DECIMATION_N[15:0] RW 0x0000 This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
41 0x0110 0x0440 REG_* Channel 1, similar to register 0x100 to 0x10f.
42 0x0120 0x0480 REG_* Channel 2, similar to register 0x100 to 0x10f.
43 0x01F0 0x07c0 REG_* Channel 15, similar to register 0x100 to 0x10f.
44 Tue Mar 14 10:17:59 2023

78
docs/library/common/regmap_adc_common.csv Normal file
View File

@ -0,0 +1,78 @@
Address ,,,,,,
DWORD ,BYTE ,Bits ,Name ,Type ,Default ,Description
0x0010 ,0x0040 ,,REG_RSTN ,,,ADC Interface Control & Status
,,[2] ,CE_N ,RW ,0x0 ,"Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables "
,,[1] ,MMCM_RSTN ,RW ,0x0 ,"MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. "
,,[0] ,RSTN ,RW ,0x0 ,"Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. "
0x0011 ,0x0044 ,,REG_CNTRL ,,,ADC Interface Control & Status
,,[16] ,SDR_DDR_N ,RW ,0x0 ,"Interface type (1 represents SDR, 0 represents DDR) "
,,[15] ,SYMB_OP ,RW ,0x0 ,Select symbol data format mode (0x1)
,,[14] ,SYMB_8_16B ,RW ,0x0 ,"Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) "
,,[12:8] ,NUM_LANES[4:0] ,RW ,0x0 ,"Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported. "
,,[3] ,SYNC ,RW ,0x0 ,Initialize synchronization between multiple ADCs
,,[2] ,R1_MODE ,RW ,0x0 ,Select number of RF channels 1 (0x1) or 2 (0x0).
,,[1] ,DDR_EDGESEL ,RW ,0x0 ,Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
,,[0] ,PIN_MODE ,RW ,0x0 ,"Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge. "
0x0012 ,0x0048 ,,REG_CNTRL_2 ,,,ADC Interface Control & Status
,,[1] ,EXT_SYNC_ARM ,RW ,0x0 ,"Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. "
,,[2] ,EXT_SYNC_DISARM ,RW ,0x0 ,Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
,,[8] ,MANUAL_SYNC_REQUEST ,RW ,0x0 ,Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0013 ,0x004c ,,REG_CNTRL_3 ,,,ADC Interface Control & Status
,,[8] ,CRC_EN ,RW ,0x0 ,Setting this bit will enable the CRC generation.
,,[7:0] ,CUSTOM_CONTROL ,RW ,0x00 ,"Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode , bit 1 - enables alternate bit polarity decode). "
0x0015 ,0x0054 ,,REG_CLK_FREQ ,,,ADC Interface Control & Status
,,[31:0] ,CLK_FREQ[31:0] ,RO ,0x0000 ,Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016 ,0x0058 ,,REG_CLK_RATIO ,,,ADC Interface Control & Status
,,[31:0] ,CLK_RATIO[31:0] ,RO ,0x0000 ,Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017 ,0x005c ,,REG_STATUS ,,,ADC Interface Control & Status
,,[4] ,ADC_CTRL_STATUS ,RO ,0x0 ,"If set, indicates that the device'​s register data is available on the data bus. "
,,[3] ,PN_ERR ,RO ,0x0 ,"If set, indicates pn error in one or more channels. "
,,[2] ,PN_OOS ,RO ,0x0 ,"If set, indicates pn oos in one or more channels. "
,,[1] ,OVER_RANGE ,RO ,0x0 ,"If set, indicates over range in one or more channels. "
,,[0] ,STATUS ,RO ,0x0 ,"Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. "
0x0018 ,0x0060 ,,REG_DELAY_CNTRL ,,,ADC Interface Control & Status(Deprecated from version 9)
,,[17] ,DELAY_SEL ,RW ,0x0 ,"Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below. "
,,[16] ,DELAY_RWN ,RW ,0x0 ,"Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay. "
,,[15:8] ,DELAY_ADDRESS[7:0] ,RW ,0x00 ,"Delay address, the range depends on the interface pins, data pins are usually at the lower range. "
,,[4:0] ,DELAY_WDATA[4:0] ,RW ,0x0 ,"Delay write data, a value of 1 corresponds to (1/200)ns for most devices. "
0x0019 ,0x0064 ,,REG_DELAY_STATUS ,,,ADC Interface Control & Status(Deprecated from version 9)
,,[9] ,DELAY_LOCKED ,RO ,0x0 ,"Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements. "
,,[8] ,DELAY_STATUS ,RO ,0x0 ,"If set, indicates busy status (access pending). The read data may not be valid if this bit is set. "
,,[4:0] ,DELAY_RDATA[4:0] ,RO ,0x0 ,"Delay read data, current delay value in the elements "
0x001A ,0x0068 ,,REG_SYNC_STATUS ,,,ADC Synchronization Status register
,,[0] ,ADC_SYNC ,RO ,0x0 ,ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.
0x001C ,0x0070 ,,REG_DRP_CNTRL ,,,ADC Interface Control & Status
,,[28] ,DRP_RWN ,RW ,0x0 ,DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
,,[27:16] ,DRP_ADDRESS[11:0] ,RW ,0x00 ,"DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). "
,,[15:0] ,RESERVED[15:0] ,RO ,0x0000 ,Reserved for backward compatibility.
0x001D ,0x0074 ,,REG_DRP_STATUS ,,,ADC Interface Control & Status
,,[17] ,DRP_LOCKED ,RO ,0x0 ,If set indicates that the DRP has been locked.
,,[16] ,DRP_STATUS ,RO ,0x0 ,If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
,,[15:0] ,RESERVED[15:0] ,RO ,0x00 ,Reserved for backward compatibility.
0x001E ,0x0078 ,,REG_DRP_WDATA ,,,ADC DRP Write Data
,,[15:0] ,DRP_WDATA[15:0] ,RW ,0x00 ,DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F ,0x007c ,,REG_DRP_RDATA ,,,ADC DRP Read Data
,,[15:0] ,DRP_RDATA[15:0] ,RO ,0x00 ,DRP read data (does not include GTX lanes).
0x0020 ,0x0080 ,,REG_ADC_CONFIG_WR ,,,ADC Write Configuration ​Data
,,[31:0] ,ADC_CONFIG_WR[31:0] ,RW ,0x0000 ,Custom ​Write to the available registers.
0x0021 ,0x0084 ,,REG_ADC_CONFIG_RD ,,,ADC Read Configuration ​Data
,,[31:0] ,ADC_CONFIG_RD[31:0] ,RO ,0x0000 ,Custom read of the available registers.
0x0022 ,0x0088 ,,REG_UI_STATUS ,,,User Interface Status
,,[2] ,UI_OVF ,RW1C ,0x0 ,"User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. "
,,[1] ,UI_UNF ,RW1C ,0x0 ,"User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. "
,,[0] ,UI_RESERVED ,RW1C ,0x0 ,Reserved for backward compatibility.
0x0023 ,0x008c ,,REG_ADC_CONFIG_CTRL ,,,ADC RD/WR configuration
,,[31:0] ,ADC_CONFIG_CTRL[31:​0] ,RW ,0x0000 ,"Control RD/WR requests to the device'​s register map: bit 1 - RD ('b1) , WR ('b0), bit 0 - enable WR/RD operation. "
0x0028 ,0x00a0 ,,REG_USR_CNTRL_1 ,,,ADC Interface Control & Status
,,[7:0] ,USR_CHANMAX[7:0] ,RW ,0x00 ,This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0029 ,0x00a4 ,,REG_ADC_START_CODE ,,,ADC Synchronization start word
,,[31:0] ,ADC_START_CODE[31:0] ,RW ,0x00000000 ,This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
0x002E ,0x00b8 ,,REG_ADC_GPIO_IN ,,,ADC GPIO inputs
,,[31:0] ,ADC_GPIO_IN[31:0] ,RO ,0x00000000 ,This reads auxiliary GPI pins of the ADC core
0x002F ,0x00bc ,,REG_ADC_GPIO_OUT ,,,ADC GPIO outputs
,,[31:0] ,ADC_GPIO_OUT[31:0] ,RW ,0x00000000 ,This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
0x0030 ,0x00c0 ,,REG_PPS_COUNTER ,,,PPS Counter register
,,[31:0] ,PPS_COUNTER[31:0] ,RO ,0x00000000 ,Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
0x0031 ,0x00c4 ,,REG_PPS_STATUS ,,,PPS Status register
,,[0] ,PPS_STATUS ,RO ,0x0 ,If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
,,,,,,Tue Mar 14 10:17:59 2023
1 Address
2 DWORD BYTE Bits Name Type Default Description
3 0x0010 0x0040 REG_RSTN ADC Interface Control & Status
4 [2] CE_N RW 0x0 Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
5 [1] MMCM_RSTN RW 0x0 MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
6 [0] RSTN RW 0x0 Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
7 0x0011 0x0044 REG_CNTRL ADC Interface Control & Status
8 [16] SDR_DDR_N RW 0x0 Interface type (1 represents SDR, 0 represents DDR)
9 [15] SYMB_OP RW 0x0 Select symbol data format mode (0x1)
10 [14] SYMB_8_16B RW 0x0 Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
11 [12:8] NUM_LANES[4:0] RW 0x0 Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.
12 [3] SYNC RW 0x0 Initialize synchronization between multiple ADCs
13 [2] R1_MODE RW 0x0 Select number of RF channels 1 (0x1) or 2 (0x0).
14 [1] DDR_EDGESEL RW 0x0 Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
15 [0] PIN_MODE RW 0x0 Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.
16 0x0012 0x0048 REG_CNTRL_2 ADC Interface Control & Status
17 [1] EXT_SYNC_ARM RW 0x0 Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
18 [2] EXT_SYNC_DISARM RW 0x0 Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
19 [8] MANUAL_SYNC_REQUEST RW 0x0 Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
20 0x0013 0x004c REG_CNTRL_3 ADC Interface Control & Status
21 [8] CRC_EN RW 0x0 Setting this bit will enable the CRC generation.
22 [7:0] CUSTOM_CONTROL RW 0x00 Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode , bit 1 - enables alternate bit polarity decode).
23 0x0015 0x0054 REG_CLK_FREQ ADC Interface Control & Status
24 [31:0] CLK_FREQ[31:0] RO 0x0000 Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
25 0x0016 0x0058 REG_CLK_RATIO ADC Interface Control & Status
26 [31:0] CLK_RATIO[31:0] RO 0x0000 Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
27 0x0017 0x005c REG_STATUS ADC Interface Control & Status
28 [4] ADC_CTRL_STATUS RO 0x0 If set, indicates that the device'​s register data is available on the data bus.
29 [3] PN_ERR RO 0x0 If set, indicates pn error in one or more channels.
30 [2] PN_OOS RO 0x0 If set, indicates pn oos in one or more channels.
31 [1] OVER_RANGE RO 0x0 If set, indicates over range in one or more channels.
32 [0] STATUS RO 0x0 Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
33 0x0018 0x0060 REG_DELAY_CNTRL ADC Interface Control & Status(Deprecated from version 9)
34 [17] DELAY_SEL RW 0x0 Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.
35 [16] DELAY_RWN RW 0x0 Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.
36 [15:8] DELAY_ADDRESS[7:0] RW 0x00 Delay address, the range depends on the interface pins, data pins are usually at the lower range.
37 [4:0] DELAY_WDATA[4:0] RW 0x0 Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
38 0x0019 0x0064 REG_DELAY_STATUS ADC Interface Control & Status(Deprecated from version 9)
39 [9] DELAY_LOCKED RO 0x0 Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.
40 [8] DELAY_STATUS RO 0x0 If set, indicates busy status (access pending). The read data may not be valid if this bit is set.
41 [4:0] DELAY_RDATA[4:0] RO 0x0 Delay read data, current delay value in the elements
42 0x001A 0x0068 REG_SYNC_STATUS ADC Synchronization Status register
43 [0] ADC_SYNC RO 0x0 ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.
44 0x001C 0x0070 REG_DRP_CNTRL ADC Interface Control & Status
45 [28] DRP_RWN RW 0x0 DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
46 [27:16] DRP_ADDRESS[11:0] RW 0x00 DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
47 [15:0] RESERVED[15:0] RO 0x0000 Reserved for backward compatibility.
48 0x001D 0x0074 REG_DRP_STATUS ADC Interface Control & Status
49 [17] DRP_LOCKED RO 0x0 If set indicates that the DRP has been locked.
50 [16] DRP_STATUS RO 0x0 If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
51 [15:0] RESERVED[15:0] RO 0x00 Reserved for backward compatibility.
52 0x001E 0x0078 REG_DRP_WDATA ADC DRP Write Data
53 [15:0] DRP_WDATA[15:0] RW 0x00 DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
54 0x001F 0x007c REG_DRP_RDATA ADC DRP Read Data
55 [15:0] DRP_RDATA[15:0] RO 0x00 DRP read data (does not include GTX lanes).
56 0x0020 0x0080 REG_ADC_CONFIG_WR ADC Write Configuration ​Data
57 [31:0] ADC_CONFIG_WR[31:0] RW 0x0000 Custom ​Write to the available registers.
58 0x0021 0x0084 REG_ADC_CONFIG_RD ADC Read Configuration ​Data
59 [31:0] ADC_CONFIG_RD[31:0] RO 0x0000 Custom read of the available registers.
60 0x0022 0x0088 REG_UI_STATUS User Interface Status
61 [2] UI_OVF RW1C 0x0 User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
62 [1] UI_UNF RW1C 0x0 User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
63 [0] UI_RESERVED RW1C 0x0 Reserved for backward compatibility.
64 0x0023 0x008c REG_ADC_CONFIG_CTRL ADC RD/WR configuration
65 [31:0] ADC_CONFIG_CTRL[31:​0] RW 0x0000 Control RD/WR requests to the device'​s register map: bit 1 - RD ('b1) , WR ('b0), bit 0 - enable WR/RD operation.
66 0x0028 0x00a0 REG_USR_CNTRL_1 ADC Interface Control & Status
67 [7:0] USR_CHANMAX[7:0] RW 0x00 This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
68 0x0029 0x00a4 REG_ADC_START_CODE ADC Synchronization start word
69 [31:0] ADC_START_CODE[31:0] RW 0x00000000 This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
70 0x002E 0x00b8 REG_ADC_GPIO_IN ADC GPIO inputs
71 [31:0] ADC_GPIO_IN[31:0] RO 0x00000000 This reads auxiliary GPI pins of the ADC core
72 0x002F 0x00bc REG_ADC_GPIO_OUT ADC GPIO outputs
73 [31:0] ADC_GPIO_OUT[31:0] RW 0x00000000 This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
74 0x0030 0x00c0 REG_PPS_COUNTER PPS Counter register
75 [31:0] PPS_COUNTER[31:0] RO 0x00000000 Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
76 0x0031 0x00c4 REG_PPS_STATUS PPS Status register
77 [0] PPS_STATUS RO 0x0 If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
78 Tue Mar 14 10:17:59 2023

29
docs/library/common/regmap_base.csv Normal file
View File

@ -0,0 +1,29 @@
Address ,,,,,,
DWORD ,BYTE ,Bits ,Name ,Type ,Default ,Description
0x0000 ,0x0000 ,,REG_VERSION ,,,Version and Scratch Registers
,,[31:0] ,VERSION[31:0] ,RO ,0x00000000 ,Version number. Unique to all cores.
0x0001 ,0x0004 ,,REG_ID ,,,Version and Scratch Registers
,,[31:0] ,ID[31:0] ,RO ,0x00000000 ,Instance identifier number.
0x0002 ,0x0008 ,,REG_SCRATCH ,,,Version and Scratch Registers
,,[31:0] ,SCRATCH[31:0] ,RW ,0x00000000 ,Scratch register.
0x0003 ,0x000c ,,REG_CONFIG ,,,Version and Scratch Registers
,,[0] ,IQCORRECTION_DISABLE ,RO ,0x0 ,"If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) "
,,[1] ,DCFILTER_DISABLE ,RO ,0x0 ,"If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) "
,,[2] ,DATAFORMAT_DISABLE ,RO ,0x0 ,"If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) "
,,[3] ,USERPORTS_DISABLE ,RO ,0x0 ,"If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) "
,,[4] ,MODE_1R1T ,RO ,0x0 ,"If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet) "
,,[5] ,DELAY_CONTROL_DISABLE ,RO ,0x0 ,"If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) "
,,[6] ,DDS_DISABLE ,RO ,0x0 ,"If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) "
,,[7] ,CMOS_OR_LVDS_N ,RO ,0x0 ,CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
,,[8] ,PPS_RECEIVER_ENABLE ,RO ,0x0 ,"If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) "
,,[9] ,SCALECORRECTION_ONLY ,RO ,0x0 ,"If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) "
,,[12] ,EXT_SYNC ,RO ,0x0 ,If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
,,[13] ,RD_RAW_DATA ,RO ,0x0 ,"If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel. "
0x0004 ,0x0010 ,,REG_PPS_IRQ_MASK ,,,PPS Interrupt mask
,,[0] ,PPS_IRQ_MASK ,RW ,0x1 ,Mask bit for the 1PPS receiver interrupt
0x0007 ,0x001c ,,REG_FPGA_INFO ,,,FPGA device information Intel encoded values Xilinx encoded values
,,[31:24] ,FPGA_TECHNOLOGY ,RO ,0x0 ,Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
,,[23:16] ,FPGA_FAMILY ,RO ,0x0 ,"Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) "
,,[15:8] ,SPEED_GRADE ,RO ,0x0 ,Encoded value describing the FPGA's speed-grade
,,[7:0] ,DEV_PACKAGE ,RO ,0x0 ,Encoded value describing the device package. The package might affect high-speed interfaces
,,,,,,Tue Mar 14 10:17:59 2023
1 Address
2 DWORD BYTE Bits Name Type Default Description
3 0x0000 0x0000 REG_VERSION Version and Scratch Registers
4 [31:0] VERSION[31:0] RO 0x00000000 Version number. Unique to all cores.
5 0x0001 0x0004 REG_ID Version and Scratch Registers
6 [31:0] ID[31:0] RO 0x00000000 Instance identifier number.
7 0x0002 0x0008 REG_SCRATCH Version and Scratch Registers
8 [31:0] SCRATCH[31:0] RW 0x00000000 Scratch register.
9 0x0003 0x000c REG_CONFIG Version and Scratch Registers
10 [0] IQCORRECTION_DISABLE RO 0x0 If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
11 [1] DCFILTER_DISABLE RO 0x0 If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
12 [2] DATAFORMAT_DISABLE RO 0x0 If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
13 [3] USERPORTS_DISABLE RO 0x0 If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
14 [4] MODE_1R1T RO 0x0 If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
15 [5] DELAY_CONTROL_DISABLE RO 0x0 If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
16 [6] DDS_DISABLE RO 0x0 If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
17 [7] CMOS_OR_LVDS_N RO 0x0 CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
18 [8] PPS_RECEIVER_ENABLE RO 0x0 If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
19 [9] SCALECORRECTION_ONLY RO 0x0 If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
20 [12] EXT_SYNC RO 0x0 If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
21 [13] RD_RAW_DATA RO 0x0 If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.
22 0x0004 0x0010 REG_PPS_IRQ_MASK PPS Interrupt mask
23 [0] PPS_IRQ_MASK RW 0x1 Mask bit for the 1PPS receiver interrupt
24 0x0007 0x001c REG_FPGA_INFO FPGA device information Intel encoded values Xilinx encoded values
25 [31:24] FPGA_TECHNOLOGY RO 0x0 Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
26 [23:16] FPGA_FAMILY RO 0x0 Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
27 [15:8] SPEED_GRADE RO 0x0 Encoded value describing the FPGA's speed-grade
28 [7:0] DEV_PACKAGE RO 0x0 Encoded value describing the device package. The package might affect high-speed interfaces
29 Tue Mar 14 10:17:59 2023

236
docs/library/spi_engine/axi_spi_engine.rst Normal file
View File

@ -0,0 +1,236 @@
.. _spi_engine axi:
AXI SPI Engine Module
================================================================================
.. symbolator:: ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.v
:caption: axi_spi_engine
The AXI SPI Engine peripheral allows asynchronous interrupt-driven memory-mapped
access to a SPI Engine Control Interface.
This is typically used in combination with a software program to dynamically
generate SPI transactions.
The peripheral has also support for providing memory-mapped access to one or more
:ref:`spi_engine offload` cores and change its content dynamically at runtime.
Files
--------------------------------------------------------------------------------
.. list-table::
:widths: 25 75
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/axi_spi_engine/axi_spi_engine.v`
- Verilog source for the peripheral.
* - :git-hdl:`master:library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl`
- TCL script to generate the Vivado IP-integrator project for the peripheral.
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
:path: library/spi_engine/axi_spi_engine
* - ASYNC_SPI_CLK
- If set to 1 the ``s_axi_aclk`` and ``spi_clk`` clocks are assumed
to be asynchronous.
* - CMD_FIFO_ADDRESS_WIDTH
- Configures the size of the command FIFO.
* - SDO_FIFO_ADDRESS_WIDTH
- Configures the size of the serial-data out FIFO.
* - SDI_FIFO_ADDRESS_WIDTH
- Configures the size of the serial-data in FIFO.
* - NUM_OFFLOAD
- The number of offload control interfaces.
Signal and Interface Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 25 65
:header-rows: 1
* - Name
- Type
- Description
* - ``s_axi_aclk``
- Clock
- All ``s_axi`` signals and ``irq`` are synchronous to this clock.
* - ``s_axi_aresetn``
- Synchronous active-low reset
- Resets the internal state of the peripheral.
* - ``s_axi``
- AXI-Lite bus slave
- Memory-mapped AXI-lite bus that provides access to modules register map.
* - ``irq``
- Level-High Interrupt
- Interrupt output of the module. Is asserted when at least one of the
modules interrupt is pending and unmasked.
* - ``spi_clk``
- Clock
- All ``spi_engine_ctrl`` signals and ``spi_resetn`` are
synchronous to this clock.
* - ``spi_engine_ctrl``
- :ref:`spi_engine control-interface` slave
- SPI Engine Control stream that contains commands and data for the
execution module.
* - ``spi_resetn``
- Output
- This signal is asserted when the module is disabled through the ENABLE
register. Typically used as the reset for the SPI Engine modules
connected to these modules.
Register Map
--------------------------------------------------------------------------------
.. csv-table::
:file: regmap.csv
:class: regmap
:header-rows: 2
.. list-table::
:widths: 10 20 70
:header-rows: 1
* - Access Type
- Name
- Description
* - RO
- Read-only
- Reads will return the current register value. Writes have no effect.
* - RW
- Read-write
- Reads will return the current register value. Writes will change the
current register value.
* - WO
- Write-only
- Writes will change the current register value. Reads have no effect.
* - RW1C
- Write-1-to-clear
- Reads will return the current register value. Writing the register will
clear those bits of the register which were set to 1 in the value written.
Bits are set by hardware.
Theory of Operation
--------------------------------------------------------------------------------
Typically a software application running on a CPU will be able to execute much
faster than the SPI engine command will be processed.
In order to allow the software to execute other tasks while the SPI engine is
busy processing commands the AXI SPI Engine peripheral offers interrupt-driven
notification which can be used to notify the software when a SPI command has
been executed.
In order to reduce the necessary context switches the AXI SPI Engine peripheral
incorporates FIFOs to buffer the command as well as the data streams.
FIFOs
--------------------------------------------------------------------------------
The AXI SPI Engine peripheral has three FIFOs, one for each of the command, SDO
and SDI streams.
The size of the FIFOs can be configured by setting the CMD_FIFO_ADDRESS_WIDTH,
SDO_FIFO_ADDRESS_WIDTH and SDI_FIFO_ADDRESS_WIDTH parameters.
One end of the FIFOs are connected to a memory-mapped register and can be
accessed via the AXI-Lite interface.
The other end is directly connected to the matching stream of the
:ref:`spi_engine control-interface`.
Data can be inserted into the command FIFO by writing to the CMD_FIFO register
and new data can be inserted into the SDO_FIFO register.
If an application attempts to write to a FIFO while the FIFO is already full the
data is discarded and the state of the FIFO remains unmodified.
The number of empty entries in the command and SDO FIFO can be queried by
reading the CMD_FIFO_ROOM or SDO_FIFO_ROOM register.
Data can be removed from the SDI FIFO by reading from the SDI_FIFO register.
If an application attempts to read data while the FIFO is empty undefined data
is returned and the state of the FIFO remains unmodified.
It is possible to read the first entry in the SDI FIFO without removing it by
reading from the SDI_FIFO_PEEK register.
The number of valid entries in the SDI FIFO register can be queried by reading
the SDI_FIFO_LEVEL register.
If the peripheral is disabled by setting the ENABLE register to 0 any data
stored in the FIFOs is discarded and the state of the FIFO is reset.
Synchronization Events
--------------------------------------------------------------------------------
Synchronization events can be used to notify the software application about the
progress of the command stream.
An application can insert a SYNC instruction at any point in the command stream.
If the execution module reaches the SYNC instruction it will generate an event
on the SYNC stream.
When this event is received by the AXI SPI Engine peripheral it will update the
SYNC_ID register with the received event ID and will assert the SYNC_EVENT
interrupt.
Typically the SYNC instruction should be inserted after the last instruction in
a SPI transaction.
This will allow the application to be notified about the completion of the
transaction and allows it to do further processing based on the result of the
transaction.
It is recommended that synchronization IDs are generated in a monotonic
incrementing or decrementing manner.
This makes it possible to easily check if an event has completed by checking if
it is less or equal (incrementing IDs) or more or equal (decrementing IDs) to
the ID of the last completed event.
Interrupts
--------------------------------------------------------------------------------
The SPI Engine AXI peripheral has 4 internal interrupts. One for each of the
FIFOs which are asserted when the FIFO level falls bellow the almost empty level
(for the command or SDO FIFO) or rises above the almost full level (for the SDI
FIFO).
And one interrupt which is asserted when a new synchronization event arrives.
The peripheral has 1 external interrupt which is supposed to be connected to the
upstream interrupt controller.
The external interrupt is a logical OR-operation over the internal interrupts,
meaning if at least one of the internal interrupts is asserted the external
interrupt is asserted and only if all internal interrupts are de-asserted the
external interrupt is de-asserted. In addition, each interrupt has a mask bit
which can be used to stop the propagation of the internal interrupt to the
external interrupt. If an interrupt is masked it will count towards the external
interrupt state as if it were not asserted.
The mask bits can be modified by writing to the IRQ_MASK register.
The raw interrupt status can be read from the IRQ_SOURCE register and the
combined state of the IRQ_MASK and raw interrupt state can be read from the
IRQ_PENDING register.
.. code::
IRQ_PENDING = IRQ_SOURCE & IRQ_MASK;
IRQ = |IRQ_PENDING;
FIFO Threshold Interrupts
--------------------------------------------------------------------------------
The FIFO threshold interrupts can be used by software for flow control of the
command, SDI and SDO streams.
If an application wants to send more data than what fits into the FIFO can write
samples into the FIFO until it is full then suspend operation wait for the almost
empty interrupt and continue writing data to the FIFO.
Similarly, when the application wants to read more data than what fits into FIFO
it should listen for the almost full interrupt and read data from the FIFO when
it occurs.
The FIFO threshold interrupt is asserted when then FIFO level rises above the
watermark and is automatically de-asserted when the level drops below the
watermark.
SYNC_EVENT Interrupt
--------------------------------------------------------------------------------
The SYNC_EVENT interrupt is asserted when a new sync event is received from the
sync stream.
An application that generated a SYNC instruction on the command stream can use
this interrupt to be notified when the sync instruction has been completed.
To de-assert, the SYNC_EVENT interrupt the reception of the interrupt needs to
be acknowledged by the application by writing a 1 to the SYNC_EVENT bit in the
IRQ_PENDING register.

94
docs/library/spi_engine/control-interface.rst Normal file
View File

@ -0,0 +1,94 @@
.. _spi_engine control-interface:
SPI Engine Control Interface
================================================================================
The SPI Engine Control Interface is used to exchange data between different
cores within the SPI Engine framework. It is used to exchange the commands and
synchronization points as well as the SPI bus transmit and receive data.
The interface consists of four streams:
* The CMD stream which carries the SPI Engine commands. (Master to Slave)
* The SDO stream which carries the to be transmitted data for the SPI bus.
(Master to Slave)
* The SDI stream which carries the received data from the SPI bus. (Slave to
Master)
* The SYNC stream which carries the synchronization events. (Slave to Master)
Each of the streams has a valid, ready and data signal. They follow the
handshaking protocol as defined by the AXI standard. Meaning the master asserts
valid when the data on the data signal is valid and the slave asserts ready when
it is able to accept new data. If both valid and ready are asserted at the same
time the data has been transmitted from the master to the slave.
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml`
- Interface definition file
Signal Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 10 10 70
:header-rows: 1
* - Width
- Name
- Direction (Master)
- Description
* -
- ``cmd_ready``
- Input
- Ready signal of the CMD stream
* -
- ``cmd_valid``
- Output
- Valid signal of the CMD stream
* - [15:0]
- ``cmd_data``
- Output
- Data signal of the CMD stream
* -
- ``sdo_ready``
- Input
- Ready signal of the SDO stream
* -
- ``sdo_valid``
- Output
- Valid signal of the SDO stream
* - [DATA_WIDTH-1:0]
- ``sdo_data``
- Output
- Data signal of the SDO stream
* -
- ``sdi_ready``
- Output
- Ready signal of the SDI stream
* -
- ``sdi_valid``
- Input
- Valid signal of the SDI stream
* - [(NUM_OF_SDI*DATA_WIDTH-1):0]
- ``sdi_data``
- Input
- Data signal of the SDI stream
* -
- ``sync_ready``
- Output
- Ready signal of the SYNC stream
* -
- ``sync_valid``
- Input
- Valid signal of the SYNC stream
* - [7:0]
- ``sync_data``
- Input
- Data signal of the sync stream

96
docs/library/spi_engine/index.rst Normal file
View File

@ -0,0 +1,96 @@
.. _spi_engine:
SPI Engine
================================================================================
.. toctree::
:hidden:
Execution Module<spi_engine_execution>
AXI Module<axi_spi_engine>
Offload Module<spi_engine_offload>
Interconnect Module<spi_engine_interconnect>
Control Interface<control-interface>
Offload Control Interface<offload-control-interface>
SPI Bus Interface<spi-bus-interface>
Instruction Set Specification<instruction-format>
Tutorial - PulSAR ADC<tutorial>
SPI Engine is a highly flexible and powerful SPI controller framework.
It consist out of multiple sub-modules which communicate over well defined
interfaces.
This allows a high degree of flexibility and re-usability while at the same time
staying highly customizable and easily extensible.
The core component of the SPI Engine framework is a lean but powerful fully
programmable execution module, which implements the SPI bus control logic.
The SPI Engine execution module is controlled by a command stream which is
generated by a separate module. Different command stream master modules are
available and can be used depending on the system requirements.
For example a software controlled memory mapped command stream offers high
flexibility, while a offload core which executes a pre-programmed command stream
when triggered by an external event allows for very low latency response times.
By using a SPI Engine interconnect it is possible to connect multiple command
stream master modules to a SPI Engine execution module.
Sub-modules
--------------------------------------------------------------------------------
* :ref:`spi_engine execution`: Main module which processes a SPI engine command
stream and implements the SPI bus interface logic.
* :ref:`spi_engine axi`: Memory mapped software accessible interface to a
SPI Engine command stream and/or offload cores.
* :ref:`spi_engine offload`: Stores a SPI Engine command stream, execution is
triggered by an external event.
* :ref:`spi_engine interconnect`: Connects multiple SPI Engine command streams
to a SPI Engine execution module.
Interfaces
--------------------------------------------------------------------------------
* :ref:`spi_engine control-interface`: SPI Engine command stream.
* :ref:`spi_engine offload-control-interface`: Program the command stream stored
in a offload module.
* :ref:`spi_engine spi-bus-interface`: Low-level SPI bus interface.
Software
--------------------------------------------------------------------------------
* :dokuwiki:`Linux Driver:resources/tools-software/linux-drivers/spi/spi_engine`:
Linux driver for the SPI Engine framework.
* :ref:`spi_engine instruction-format`: Overview of the SPI Engine Instruction
format.
Related IP Cores
--------------------------------------------------------------------------------
This list contains cores that are not part of the core SPI engine framework but
make use of its interfaces and are intend to be used together with the SPI engine
framework.
* :dokuwiki:`util-sigma-delta-spi:resources/fpga/peripherals/util_sigma_delta_spi`:
Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family.
Examples
--------------------------------------------------------------------------------
* :dokuwiki:`CN0363:resources/eval/user-guides/eval-cn0363-pmdz`:
Colorimeter application using the :part:`AD7175-2` Sigma-Delta ADC.
* :dokuwiki:`resources/eval/user-guides/adaq7980-sdz`:
A 16-bit ADC subsystem with four common signal processing and conditioning blocks.
* :dokuwiki:`resources/tools-software/uc-drivers/ad5766`:
16-channel, 16-/12-bit, voltage output Digital-to-Analog Converters (DAC).
* :dokuwiki:`CN0363:resources/eval/user-guides/eval-cn0363-pmdz`:
The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC).
* :git-hdl:`master:projects/ad40xx_fmc`
Evaluation Board for the AD4000 Series 16-/18-/20-Bit Precision SAR ADCs.
* :dokuwiki:`AD469x:resources/eval/user-guides/ad469x`:
16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC.
* :dokuwiki:`AD4630-24 / AD4030-24 / AD4630-16:resources/eval/user-guides/ad463x/hdl`:
16/24-Bit, 2 MSPS Single or Dual Channel SAR ADC.
Additional Resources
--------------------------------------------------------------------------------
* :download:`Presentation: SPI Engine Design Philosophy <https://wiki.analog.com/_media/resources/fpga/peripherals/spi-engine3.pdf>`.
* :ref:`spi_engine tutorial`.

252
docs/library/spi_engine/instruction-format.rst Normal file
View File

@ -0,0 +1,252 @@
.. _spi_engine instruction-format:
SPI Engine Instruction Set Specification
================================================================================
The SPI Engine instruction set is a simple 16-bit instruction set of which
12-bit is currently allocated (bits 15,14,11,10 are always 0).
Instructions
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Transfer Instruction
--------------------------------------------------------------------------------
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 0 0 0 0 r w n n n n n n n n
== == == == == == = = = = = = = = = =
The transfer instructions perform a low-level SPI transfer. It will generate
SCLK transitions for the specified amount of cycles according to the SPI
configuration register. If the r bit is set the SDI pin will be sampled and
stored in the shift register at the end of each word the data is output on the
SDI_DATA stream. If the w bit is set the SDO pin will be updated with the data
received from the SDO_DATA stream. If the w bit is set the sdo_t signal will
also be set to 0 for the duration of the transfer. If the SDI_DATA stream is not
able to accept data or the SDO_DATA stream is not able to provide data the
execution is stalled at the end/start of the transfer until data is
accepted/becomes available.
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - r
- Read
- If set to 1 data will be read from the SDI pin during and the read words
will be available on the SDI_DATA interface.
* - w
- Write
- If set to 1 data will be taken from the SDO_DATA interface and output on
the SDO pin.
* - n
- Length
- n + 1 number of words that will be transferred.
Chip-select Instruction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 0 1 0 0 t t s s s s s s s s
== == == == == == = = = = = = = = = =
The chip-select instruction updates the value chip-select output signal of the
SPI Engine execution module.
Before and after the update is performed the execution module is paused for the
specified delay. The length of the delay depends on the module clock frequency,
the setting of the prescaler register and the t parameter of the instruction.
This delay is inserted before and after the update of the chip-select signal,
so the total execution time of the chip-select
instruction is twice the delay.
.. math::
delay = t * \frac{div + 1}{f_{clk}}
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - t
- Delay
- Delay before and after setting the new configuration.
* - s
- Chip-select
- The new chip-select configuration.
Configuration Write Instruction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 1 0 0 0 r r v v v v v v v v
== == == == == == = = = = = = = = = =
The configuration writes instruction updates a
:ref:`spi_engine configutarion-registers`
of the SPI Engine execution module with a new value.
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - r
- Register
- Configuration register address.
2'b00 = :ref:`spi_engine prescaler-configuration-register`
2'b01 = :ref:`spi_engine spi-configuration-register`
2'b10 = :ref:`spi_engine dynamic-transfer-length-register`.
* - v
- Value
- New value for the configuration register.
Synchronize Instruction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 1 1 0 0 0 0 n n n n n n n n
== == == == == == = = = = = = = = = =
The synchronize instruction generates a synchronization event on the SYNC output
stream. This can be used to monitor the progress of the command stream. The
synchronize instruction is also used by the :ref:`spi_engine interconnect`
module to identify the end of a transaction and re-start the arbitration process.
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - n
- id
- Value of the generated synchronization event.
Sleep Instruction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 1 1 0 0 0 1 t t t t t t t t
== == == == == == = = = = = = = = = =
The sleep instruction stops the execution of the command stream for the
specified amount of time. The time is based on the external clock frequency the
configuration value of the prescaler register and the time parameter of the
instruction.
.. math::
sleep\_time = \frac{(t + 1) * ((div + 1) * 2)}{f_{clk}}
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - t
- Time
- The amount of time to wait.
.. _spi_engine configutarion-registers:
Configuration Registers
--------------------------------------------------------------------------------
The SPI Engine execution module has a set of 8-bit configuration registers which
can be used to dynamically modify the behavior of the module at runtime.
.. _spi_engine spi-configuration-register:
SPI Configuration Register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The SPI configuration register configures various aspects of the low-level SPI
bus behavior.
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - [7:3]
- reserved
- Must always be 0.
* - [2]
- three_wire
- Configures the output of the three_wire pin.
* - [1]
- CPOL
- Configures the polarity of the SCLK signal. When 0, the idle state of
the SCLK signal is low. When 1, the idle state of the SCLK signal is
high.
* - [0]
- CPHA
- Configures the phase of the SCLK signal. When 0, data is updated on the
leading edge and sampled on the trailing edge. When 1, data is is
sampled on the leading edge and updated on the trailing edge.
.. _spi_engine prescaler-configuration-register:
Prescaler Configuration Register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The prescaler configuration register configures the divider that is applied to
the module clock when generating the SCLK signal and other internal control
signals used by the sleep and chip-select commands.
===== ==== =======================
Bits Name Description
===== ==== =======================
[7:0] div Prescaler clock divider
===== ==== =======================
The frequency of the SCLK signal is derived from the module clock frequency
using the following formula:
.. math::
f_{sclk} = \frac{f_{clk}}{((div + 1) * 2)}
If no prescaler block is present div is 0.
.. _spi_engine dynamic-transfer-length-register:
Dynamic Transfer Length Register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The dynamic transfer length register sets the length (in bits) of a transfer. By
default, the transfer length is equal to the DATA_WIDTH of the execution module.
If required the user can reduce this length by setting this register. A general
rule of thumb is to set the DATA_WIDTH parameter to the largest transfer length
supported by the target device.
===== ==== =======================
Bits Name Description
===== ==== =======================
[7:0] div Dynamic transfer length
===== ==== =======================

78
docs/library/spi_engine/offload-control-interface.rst Normal file
View File

@ -0,0 +1,78 @@
.. _spi_engine offload-control-interface:
SPI Engine Offload Control Interface
================================================================================
The SPI-Engine offload control interface is used to configure and control a
:ref:`spi_engine offload`.
It is used to activate/deactivate the core as well re-program the command and
SDO data RAM.
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml`
- Interface definition file
Signal Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 10 70
:header-rows: 1
* - Name
- Direction (Master)
- Description
* - ``cmd_wr_en``
- Output
- If asserted cmd_wr_data is written to the command memory.
* - ``cmd_wr_data``
- Output
- Data to write to the command memory.
* - ``sdo_wr_en``
- Output
- If asserted sdo_wr_data is written to the SDO data memory.
* - ``sdo_wr_data``
- Output
- Data to write to the SDO data memory.
* - ``mem_reset``
- Output
- Reset the contents of both the command and SDO data memory.
* - ``enable``
- Output
- If asserted the connected offload core will get enabled.
* - ``enabled``
- Input
- If asserted the connected offload core is enabled.
Theory of Operation
--------------------------------------------------------------------------------
The SPI-Engine offload core typically implements to RAMs, one for the command
stream and one for the SDO data stream. If the ``mem_reset`` signal is asserted
the content of both memories is cleared. Asserting ``cmd_wr_en`` will write the
value of ``cmd_wr_data`` to the command memory and increase the write address by
one. The next time ``cmd_wr_en`` is asserted the next entry in the memory will
be written and so on. If ``cmd_wr_en`` is asserted more times than the size of
the command memory (without a reset in between) undefined behavior will occur.
``sdo_wr_en`` and ``sdo_wr_data`` behave analogously for the SDO data memory.
If the ``enable`` signal the is asserted the SPI-Engine offload core will be
active, this means it will listen to external trigger events and execute the
stored SPI transfer when the external trigger is asserted. If ``enable`` is not
asserted the core will no longer listen to trigger events and will not start new
transfers. But it might still be busy executing a SPI transfer that was started
previously. The ``enabled`` signal is used to indicate this and it will stay
asserted even after ``enable`` as been deasserted until the currently active SPI
transfer has been completed.
If either ``enable`` or ``enabled`` is asserted ``cmd_wr_en``, ``sdo_wr_en``, or
``memt_reset`` must not be asserted, otherwise undefined behavior can occur. In
other words as long as the SPI-Engine offload core is active the content of both
the command and SDO data memory must remain stable and be consistent.

50
docs/library/spi_engine/regmap.csv Normal file
View File

@ -0,0 +1,50 @@
Address ,,,,,,
DWORD ,BYTE ,Bits ,Name ,Type ,Default ,Description
0x00 ,0x0000 ,,VERSION ,,,Version of the peripheral. Follows semantic versioning. Current version 1.00.71.
,,[31:16] ,VERSION_MAJOR ,RO ,0x01 ,
,,[15:8] ,VERSION_MINOR ,RO ,0x00 ,
,,[7:0] ,VERSION_PATCH ,RO ,0x71 ,
0x01 ,0x0004 ,,PERIPHERAL_ID ,,,
,,[31:0] ,PERIPHERAL_ID ,RO ,ID ,"Value of the ID configuration parameter. In case of multiple instances, each instance will have a unique ID. "
0x02 ,0x0008 ,,SCRATCH ,,,
,,[31:0] ,SCRATCH ,RW ,0x00000000 ,Scratch register useful for debug.
0x03 ,0x000c ,,DATA_WIDTH ,,,
,,[31:0] ,DATA_WIDTH ,RO ,0x00000008 ,Data width of the SDI/SDO parallel interface. It is equal with the maximum supported transfer length in bits.
0x10 ,0x0040 ,,ENABLE ,,,
,,[31:0] ,ENABLE ,RW ,0x00000001 ,"Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset. For proper operation, the bit needs to be set to 0. "
0x20 ,0x0080 ,,IRQ_MASK ,,,
,,[0] ,CMD_ALMOST_EMPTY ,RW ,0x00 ,If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
,,[1] ,SDO_ALMOST_EMPTY ,RW ,0x00 ,If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
,,[2] ,SDI_ALMOST_FULL ,RW ,0x00 ,If set to 0 the SDI_ALMOST_FULL interrupt is masked.
,,[3] ,SYNC_EVENT ,RW ,0x00 ,If set to 0 the SYNC_EVENT interrupt is masked.
0x21 ,0x0084 ,,IRQ_PENDING ,,,
,,[31:0] ,IRQ_PENDING ,RW1C ,0x00000000 ,Pending IRQs with mask.
0x22 ,0x0088 ,,IRQ_SOURCE ,,,
,,[31:0] ,IRQ_SOURCE ,RO ,0x00000000 ,Pending IRQs without mask.
0x30 ,0x00c0 ,,SYNC_ID ,,,
,,[31:0] ,SYNC_ID ,RO ,0x00000000 ,Last synchronization event ID received from the SPI engine control interface.
0x34 ,0x00d0 ,,CMD_FIFO_ROOM ,,,
,,[31:0] ,CMD_FIFO_ROOM ,RO ,0x???????? ,Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter.
0x35 ,0x00d4 ,,SDO_FIFO_ROOM ,,,
,,[31:0] ,SDO_FIFO_ROOM ,RO ,0x???????? ,Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter.
0x36 ,0x00d8 ,,SDI_FIFO_LEVEL ,,,
,,[31:0] ,SDI_FIFO_LEVEL ,RO ,0x00000000 ,Number of valid entries in the serial-data-in FIFO.
0x38 ,0x00e0 ,,CMD_FIFO ,,,
,,[31:0] ,CMD_FIFO ,WO ,0x????????? ,Command FIFO register. Writing to this register inserts an entry into the command FIFO. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x39 ,0x00e4 ,,SDO_FIFO ,,,
,,[31:0] ,SDO_FIFO ,WO ,0x????????? ,SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x3a ,0x00e8 ,,SDI_FIFO ,,,
,,[31:0] ,SDI_FIFO ,RO ,0x????????? ,SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
0x3c ,0x00f0 ,,SDI_FIFO_PEEK ,,,
,,[31:0] ,SDI_FIFO_PEEK ,RO ,0x????????? ,"SDI FIFO peek register. Reading from this register returns the first entry from the SDI FIFO, but without removing it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect. "
0x40 ,0x0100 ,,OFFLOAD0_EN ,,,
,,[31:0] ,OFFLOAD0_EN ,RW ,0x00000000 ,Set this bit to enable the offload module.
0x41 ,0x0104 ,,OFFLOAD0_STATUS ,,,
,,[31:0] ,OFFLOAD0_STATUS ,RO ,0x00000000 ,Offload status register.
0x42 ,0x0108 ,,OFFLOAD0_MEM_RESET ,,,
,,[31:0] ,OFFLOAD0_MEM_RESET ,WO ,0x00000000 ,Reset the memory of the offload module.
0x44 ,0x0110 ,,OFFLOAD0_CDM_FIFO ,,,
,,[31:0] ,OFFLOAD0_CDM_FIFO ,WO ,0x???????? ,Offload command FIFO register. Writing to this register inserts an entry into the command FIFO of the offload module. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x45 ,0x0114 ,,OFFLOAD0_SDO_FIFO ,,,
,,[31:0] ,OFFLOAD0_SDO_FIFO ,WO ,0x???????? ,Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
,,,,,,Wed Oct 12 14:15:25 2022
1 Address
2 DWORD BYTE Bits Name Type Default Description
3 0x00 0x0000 VERSION Version of the peripheral. Follows semantic versioning. Current version 1.00.71.
4 [31:16] VERSION_MAJOR RO 0x01
5 [15:8] VERSION_MINOR RO 0x00
6 [7:0] VERSION_PATCH RO 0x71
7 0x01 0x0004 PERIPHERAL_ID
8 [31:0] PERIPHERAL_ID RO ID Value of the ID configuration parameter. In case of multiple instances, each instance will have a unique ID.
9 0x02 0x0008 SCRATCH
10 [31:0] SCRATCH RW 0x00000000 Scratch register useful for debug.
11 0x03 0x000c DATA_WIDTH
12 [31:0] DATA_WIDTH RO 0x00000008 Data width of the SDI/SDO parallel interface. It is equal with the maximum supported transfer length in bits.
13 0x10 0x0040 ENABLE
14 [31:0] ENABLE RW 0x00000001 Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset. For proper operation, the bit needs to be set to 0.
15 0x20 0x0080 IRQ_MASK
16 [0] CMD_ALMOST_EMPTY RW 0x00 If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
17 [1] SDO_ALMOST_EMPTY RW 0x00 If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
18 [2] SDI_ALMOST_FULL RW 0x00 If set to 0 the SDI_ALMOST_FULL interrupt is masked.
19 [3] SYNC_EVENT RW 0x00 If set to 0 the SYNC_EVENT interrupt is masked.
20 0x21 0x0084 IRQ_PENDING
21 [31:0] IRQ_PENDING RW1C 0x00000000 Pending IRQs with mask.
22 0x22 0x0088 IRQ_SOURCE
23 [31:0] IRQ_SOURCE RO 0x00000000 Pending IRQs without mask.
24 0x30 0x00c0 SYNC_ID
25 [31:0] SYNC_ID RO 0x00000000 Last synchronization event ID received from the SPI engine control interface.
26 0x34 0x00d0 CMD_FIFO_ROOM
27 [31:0] CMD_FIFO_ROOM RO 0x???????? Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter.
28 0x35 0x00d4 SDO_FIFO_ROOM
29 [31:0] SDO_FIFO_ROOM RO 0x???????? Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter.
30 0x36 0x00d8 SDI_FIFO_LEVEL
31 [31:0] SDI_FIFO_LEVEL RO 0x00000000 Number of valid entries in the serial-data-in FIFO.
32 0x38 0x00e0 CMD_FIFO
33 [31:0] CMD_FIFO WO 0x????????? Command FIFO register. Writing to this register inserts an entry into the command FIFO. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
34 0x39 0x00e4 SDO_FIFO
35 [31:0] SDO_FIFO WO 0x????????? SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
36 0x3a 0x00e8 SDI_FIFO
37 [31:0] SDI_FIFO RO 0x????????? SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
38 0x3c 0x00f0 SDI_FIFO_PEEK
39 [31:0] SDI_FIFO_PEEK RO 0x????????? SDI FIFO peek register. Reading from this register returns the first entry from the SDI FIFO, but without removing it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
40 0x40 0x0100 OFFLOAD0_EN
41 [31:0] OFFLOAD0_EN RW 0x00000000 Set this bit to enable the offload module.
42 0x41 0x0104 OFFLOAD0_STATUS
43 [31:0] OFFLOAD0_STATUS RO 0x00000000 Offload status register.
44 0x42 0x0108 OFFLOAD0_MEM_RESET
45 [31:0] OFFLOAD0_MEM_RESET WO 0x00000000 Reset the memory of the offload module.
46 0x44 0x0110 OFFLOAD0_CDM_FIFO
47 [31:0] OFFLOAD0_CDM_FIFO WO 0x???????? Offload command FIFO register. Writing to this register inserts an entry into the command FIFO of the offload module. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
48 0x45 0x0114 OFFLOAD0_SDO_FIFO
49 [31:0] OFFLOAD0_SDO_FIFO WO 0x???????? Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
50 Wed Oct 12 14:15:25 2022

73
docs/library/spi_engine/spi-bus-interface.rst Normal file
View File

@ -0,0 +1,73 @@
.. _spi_engine spi-bus-interface:
SPI Bus Interface
================================================================================
The SPI bus interface carries logical low-level SPI bus signals.
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/interfaces/spi_master_rtl.xml`
- Interface definition file
Signal Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 15 65
:header-rows: 1
* - Name
- Direction (Master)
- Description
* - ``sclk``
- Output
- SPI Clock.
* - ``sdo``
- Output
- SPI SDO (MOSI) signal.
* - ``sdo_t``
- Output
- ``sdo`` tri-state enable. If 1 the MOSI signal should be tristated and
not be connected to ``sdo``
* - ``sdi``
- Input
- SPI SDI (MISO) signal. Execution module supports max 8 individual
``sdi`` lines.
* - ``cs``
- Output
- SPI chip-select signal.
* - ``three_wire``
- Output
- If set to 1 the bus should operate in three-wire mode. In three-wire
mode ``sdi`` is connected to MOSI instead of MISO.
IO configuration
--------------------------------------------------------------------------------
.. image:: spi_bus.svg
:width: 30%
:align: right
The SPI bus interface only carries a logical representation of the low-level SPI
bus signals. The top-level module in the FPGA design project is responsible for
translating the signal to physical SPI bus signals by instantiating and
connecting it to appropriate IO primitives.
The ``sclk`` and ``cs`` signals can typically be directly connected to a output
buffer. ``sdi`` should be connected to a mux, that depending on the setting of
the ``three_wire`` signal connects to a input buffer connected to the ``miso``
signal or to a input buffer connected to the ``mosi`` signal. The ``sdo`` signal
should be connected to a output tri-state buffer with the ``sdo_t`` signal
controlling the tri-state setting.
In some configurations three-wire support may not be required and ``sdi`` can
directly be connected to the input buffer for the ``miso`` signal. Similarly
when ``mosi`` tri-stating is not required the ``sdo`` signal can be directly
connected to the ``mosi`` signal leaving the ``sdo_t`` signal unconnected.

178
docs/library/spi_engine/spi_bus.svg Normal file
View File

@ -0,0 +1,178 @@
<svg width="164.71" height="116.24" version="1.1" viewBox="0 0 164.71 116.24" xmlns="http://www.w3.org/2000/svg">
<defs>
<marker id="TriangleOutM-0-6-3" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-86-2-7" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-8-3-9-3" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="DotM-7-9-6" overflow="visible" orient="auto">
<path transform="matrix(.4 0 0 .4 2.96 .4)" d="m-2.5-1c0 2.76-2.24 5-5 5s-5-2.24-5-5 2.24-5 5-5 5 2.24 5 5z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-8-0-1-4-1-1" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-9-8-8-7" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-9-9-31-0-9" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-8-0-4-0-6" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM-6-8-0-3-2-8-6" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width="1pt"/>
</marker>
</defs>
<g>
<g font-family="sans-serif">
<text x="-0.016578948" y="8.8173265" font-size="10.667px" style="line-height:1.25" xml:space="preserve"><tspan x="-0.016578948" y="8.8173265">Physical</tspan><tspan x="-0.016578948" y="22.150702">Bys</tspan></text>
<text x="113.34688" y="8.7684746" font-size="10.667px" style="line-height:1.25" xml:space="preserve"><tspan x="113.34688" y="8.7684746">FPGA</tspan><tspan x="113.34688" y="22.101851">Bus</tspan></text>
<g font-size="9.3333px">
<text x="40.463654" y="66.479492" style="line-height:1.25" xml:space="preserve"><tspan x="40.463654" y="66.479492" font-size="9.3333px" text-align="end" text-anchor="end">miso</tspan></text>
<text x="113.88789" y="38.479492" style="line-height:1.25" xml:space="preserve"><tspan x="113.88789" y="38.479492" font-size="9.3333px">sclk</tspan></text>
<text x="39.980583" y="38.479492" style="line-height:1.25" xml:space="preserve"><tspan x="39.980583" y="38.479492" font-size="9.3333px" text-align="end" text-anchor="end">sclk</tspan></text>
<text x="40.408966" y="46.547523" style="line-height:1.25" xml:space="preserve"><tspan x="40.408966" y="46.547523" font-size="9.3333px" text-align="end" text-anchor="end">cs</tspan></text>
<text x="40.828239" y="92.479492" style="line-height:1.25" xml:space="preserve"><tspan x="40.828239" y="92.479492" font-size="9.3333px" text-align="end" text-anchor="end">mosi</tspan></text>
<text x="113.87878" y="46.547523" style="line-height:1.25" xml:space="preserve"><tspan x="113.87878" y="46.547523" font-size="9.3333px">cs</tspan></text>
<text x="114.1431" y="56.444984" style="line-height:1.25" xml:space="preserve"><tspan x="114.1431" y="56.444984" font-size="9.3333px">three_wire</tspan></text>
<text x="113.88789" y="70.479492" style="line-height:1.25" xml:space="preserve"><tspan x="113.88789" y="70.479492" font-size="9.3333px">sdi</tspan></text>
<text x="113.88789" y="93.479492" style="line-height:1.25" xml:space="preserve"><tspan x="113.88789" y="93.479492" font-size="9.3333px">sdo</tspan></text>
<text x="113.88789" y="108.44498" style="line-height:1.25" xml:space="preserve"><tspan x="113.88789" y="108.44498" font-size="9.3333px">sdo_t</tspan></text>
</g>
</g>
<rect x="48" y="20" width="58" height="96" fill="none" stroke="#000" stroke-linecap="square"/>
<path d="m81 57 9 7v7l-9 7z" fill="none" stroke="#000" stroke-width="1px"/>
<path d="m73 81v17l-14-9z" fill="none" stroke="#000" stroke-width="1px"/>
</g>
<g display="none" fill="none" stroke="#000" stroke-width="1px">
<path d="m44 63h34" display="inline" marker-end="url(#TriangleOutM-6-8-3-9-3)"/>
<path d="m90 67h19" display="inline" marker-end="url(#TriangleOutM-6-8-0-4-0-6)"/>
<path d="m110 54h-24v4" display="inline" marker-end="url(#TriangleOutM-6-8-0-3-2-8-6)"/>
<path d="m53 89v-17h25" display="inline" marker-end="url(#TriangleOutM-6-8-0-1-4-1-1)" marker-start="url(#DotM-7-9-6)"/>
<path d="m110 35h-65" display="inline" marker-end="url(#TriangleOutM-0-6-3)"/>
<path d="m110 44h-65" display="inline" marker-end="url(#TriangleOutM-6-86-2-7)"/>
<path d="m59 89h-14" display="inline" marker-end="url(#TriangleOutM-6-9-8-8-7)"/>
<path d="m110 90h-34" display="inline" marker-end="url(#TriangleOutM-6-9-9-31-0-9)"/>
<path d="m110 106h-45v-11" display="inline" marker-end="url(#DotM-7-9-6)"/>
</g>
<g>
<g>
<path d="m80.308 63.5-3.46 2v-4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m111.31 67.5-3.46 2v-4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m86 60.808-2-3.46h4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt">
<path d="m80.308 72.5-3.46 2v-4z"/>
<path d="m53 87.54c1.104 0 2 0.896 2 2s-0.896 2-2 2-2-0.896-2-2 0.896-2 2-2z"/>
</g>
<g>
<path d="m42.692 35.5 3.46-2v4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m42.692 44.5 3.46-2v4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m42.692 89.5 3.46-2v4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m73.692 90.5 3.46-2v4z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m65 93.54c1.104 0 2 0.896 2 2s-0.896 2-2 2-2-0.896-2-2 0.896-2 2-2z" fill="context-stroke" fill-rule="evenodd" stroke="context-stroke" stroke-width=".4pt"/>
</g>
<g>
<path d="m44 62.5v1h34v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m80.308 63-3.46 2v-4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m76.582 60.537v4.9258l4.2598-2.4629-0.40039-0.23047zm0.5332 0.92578 2.6602 1.5371-2.6602 1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m90 66.5v1h19v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m111.31 67-3.46 2v-4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m107.58 64.537v4.9258l4.2598-2.4629-0.40039-0.23047zm0.5332 0.92578 2.6602 1.5371-2.6602 1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m85.5 53.5v4.5h1v-3.5h23.5v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m86 60.308-2-3.46h4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m83.537 56.582 2.4629 4.2598 0.23047-0.40039 2.2324-3.8594zm0.92578 0.5332h3.0742l-1.5371 2.6602z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m52.5 71.5v17.5h1v-16.5h24.5v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g fill-rule="evenodd">
<g>
<path d="m80.308 72-3.46 2v-4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m76.582 69.537v4.9258l4.2598-2.4629-0.40039-0.23047zm0.5332 0.92578 2.6602 1.5371-2.6602 1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
<g>
<path d="m53 87.04c1.104 0 2 0.896 2 2s-0.896 2-2 2-2-0.896-2-2 0.896-2 2-2z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m53 86.773c-1.2483 0-2.2676 1.0173-2.2676 2.2656 0 1.2483 1.0193 2.2676 2.2676 2.2676s2.2676-1.0193 2.2676-2.2676c0-1.2483-1.0193-2.2656-2.2676-2.2656zm0 0.5332c0.95972 0 1.7324 0.77271 1.7324 1.7324 0 0.95972-0.77271 1.7344-1.7324 1.7344s-1.7324-0.77466-1.7324-1.7344c0-0.95972 0.77271-1.7324 1.7324-1.7324z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m45 34.5v1h65v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m42.692 35 3.46-2v4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m46.418 32.537-4.2598 2.4629 0.40039 0.23047 3.8594 2.2324zm-0.5332 0.92578v3.0742l-2.6602-1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m45 43.5v1h65v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m42.692 44 3.46-2v4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m46.418 41.537-4.2598 2.4629 0.40039 0.23047 3.8594 2.2324zm-0.5332 0.92578v3.0742l-2.6602-1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m45 88.5v1h14v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m42.692 89 3.46-2v4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m46.418 86.537-4.2598 2.4629 0.40039 0.23047 3.8594 2.2324zm-0.5332 0.92578v3.0742l-2.6602-1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m76 89.5v1h34v-1z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m73.692 90 3.46-2v4z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m77.418 87.537-4.2598 2.4629 0.40039 0.23047 3.8594 2.2324zm-0.5332 0.92578v3.0742l-2.6602-1.5371z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
<g>
<path d="m64.5 95v11.5h45.5v-1h-44.5v-10.5z" color="#000000" style="-inkscape-stroke:none"/>
<g>
<g fill-rule="evenodd">
<path d="m65 93.04c1.104 0 2 0.896 2 2s-0.896 2-2 2-2-0.896-2-2 0.896-2 2-2z" color="#000000" stroke-width=".4pt" style="-inkscape-stroke:none"/>
<path d="m65 92.773c-1.2483 0-2.2676 1.0173-2.2676 2.2656 0 1.2483 1.0193 2.2676 2.2676 2.2676s2.2676-1.0193 2.2676-2.2676c0-1.2483-1.0193-2.2656-2.2676-2.2656zm0 0.5332c0.95972 0 1.7324 0.77271 1.7324 1.7324 0 0.95972-0.77271 1.7344-1.7324 1.7344s-1.7324-0.77466-1.7324-1.7344c0-0.95972 0.77271-1.7324 1.7324-1.7324z" color="#000000" style="-inkscape-stroke:none"/>
</g>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 11 KiB

125
docs/library/spi_engine/spi_engine.svg Normal file
View File

@ -0,0 +1,125 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg preserveAspectRatio="xMidYMid slice" version="1.1" viewBox="0 0 590 430" xmlns="http://www.w3.org/2000/svg" xmlns:cc="http://creativecommons.org/ns#" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">
<defs>
<marker id="TriangleInM" overflow="visible" orient="auto">
<path transform="scale(-.4)" d="m5.77 0-8.65 5v-10l8.65 5z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
<marker id="TriangleOutM" overflow="visible" orient="auto">
<path transform="scale(.4)" d="m5.77 0-8.65 5v-10l8.65 5z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"/>
</marker>
</defs>
<metadata>
<rdf:RDF>
<cc:Work rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type rdf:resource="http://purl.org/dc/dcmitype/StillImage"/>
</cc:Work>
</rdf:RDF>
</metadata>
<g transform="translate(-243.46 -391.52)">
<path d="m302.94 743.4h-22.651v51.394" fill="none" marker-start="url(#TriangleInM)" stroke="#000" stroke-width="1.6611px"/>
<path d="m474.87 745.96h21.522v48.84" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="269.15515" y="814.40948" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="269.15515" y="814.40948" font-size="16.611px" style="line-height:1.25">sdi</tspan></text>
<text x="481.29056" y="814.40948" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="481.29056" y="814.40948" font-size="16.611px" style="line-height:1.25">sdo</tspan></text>
<g transform="matrix(1.6611 0 0 1.6611 -164.25 -225.71)">
<rect x="286.31" y="573.7" width="95.039" height="18" fill="none" stroke="#2e3436" stroke-linecap="square" stroke-linejoin="round" stroke-width="2"/>
<text x="291.52399" y="585.28876" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="291.52399" y="585.28876" font-size="10px" style="line-height:1.25">Data Shift Register</tspan></text>
</g>
<g transform="matrix(1.6611 0 0 1.6611 -136.25 -262.12)">
<text x="264.92651" y="403.62927" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="264.92651" y="403.62927" font-size="10px" style="line-height:1.25">SDI</tspan></text>
<path d="m273.03 591.14v-183.07" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1px"/>
<g transform="translate(-2.2781 -51.385)">
<path d="m272.23 532.13 6.1607 6.1607" fill="none" stroke="#000" stroke-width="1px"/>
<path d="m272.23 534.13 6.1607 6.1607" fill="none" stroke="#000" stroke-width="1px"/>
</g>
</g>
<g transform="matrix(1.6611 0 0 1.6611 -128.58 -262.12)">
<text x="282.72534" y="403.62927" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="282.72534" y="403.62927" font-size="10px" style="line-height:1.25">SDO</tspan></text>
<g fill="none" stroke="#000" stroke-width="1px">
<path d="m292.46 408.08v181.44" marker-end="url(#TriangleOutM)"/>
<g transform="translate(-28.214 -49.385)">
<path d="m317.59 530.13 6.1607 6.1607"/>
<path d="m317.59 532.13 6.1607 6.1607"/>
</g>
</g>
</g>
<g transform="matrix(1.6611 0 0 1.6611 -276.13 -183.46)">
<rect x="392.95" y="443.75" width="103.54" height="57.326" fill="none" stroke="#2e3436" stroke-linecap="square" stroke-linejoin="round" stroke-width="2"/>
<text x="444.73187" y="463.48257" fill="#000000" font-family="'Liberation Sans'" font-size="10px" letter-spacing="0px" text-anchor="middle" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="444.73187" y="463.48257" text-align="center" style="line-height:1.25">Multifunction</tspan><tspan x="444.73187" y="472.0856" text-align="center" style="line-height:1.25">Counter and Compare</tspan><tspan x="444.73187" y="480.6886" text-align="center" style="line-height:1.25">Unit</tspan></text>
</g>
<g transform="matrix(1.6611 0 0 1.6611 -344.81 -188.26)">
<rect x="434.99" y="388.69" width="49.497" height="27.274" fill="none" stroke="#2e3436" stroke-dasharray="2, 4" stroke-linecap="square" stroke-linejoin="round" stroke-width="2"/>
<text x="438.2764" y="405.90323" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="438.2764" y="405.90323" font-size="10px" style="line-height:1.25">Prescaler</tspan></text>
</g>
<path d="m418.85 509.59v33.558" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<path d="m418.85 415.72v30.108" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="408.78012" y="408.55118" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="408.78012" y="408.55118" font-size="16.611px" style="line-height:1.25">clk</tspan></text>
<path d="m421.4 653.25v64.193" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="427.23248" y="661.8313" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="427.23248" y="661.8313" font-size="9.9663px" style="line-height:1.25">trigger</tspan></text>
<path d="m573.42 760.92v33.751" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="558.86859" y="814.40948" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="558.86859" y="814.40948" font-size="16.611px" style="line-height:1.25">sclk</tspan></text>
<rect x="506.7" y="470.89" width="172.04" height="39.153" fill="none" stroke="#2e3436" stroke-linecap="square" stroke-linejoin="round" stroke-width="3.3221"/>
<text x="521.4248" y="496.40375" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="521.4248" y="496.40375" font-size="16.611px" style="line-height:1.25">Instruction Decoder</tspan></text>
<g transform="matrix(1.6611 0 0 1.6611 -188.63 -262.12)">
<g transform="translate(118.62 -108.22)" fill="none" stroke="#000" stroke-width="1px">
<path d="m323.62 530.13 6.1607 6.1607"/>
<path d="m323.62 532.13 6.1607 6.1607"/>
</g>
<path d="m445.32 408.08v28.636" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1px"/>
<text x="433.90973" y="403.62927" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="433.90973" y="403.62927" font-size="10px" style="line-height:1.25">CMD</tspan></text>
</g>
<g transform="matrix(1.6611 0 0 1.6611 -164.25 -230.61)">
<rect x="490.71" y="576.65" width="57.857" height="18" fill="none" stroke="#2e3436" stroke-linecap="square" stroke-linejoin="round" stroke-width="2"/>
<text x="495.54861" y="588.23334" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="495.54861" y="588.23334" font-size="10px" style="line-height:1.25">chip-select</tspan></text>
</g>
<path d="m698.91 794.67v-33.751" fill="none" marker-start="url(#TriangleInM)" stroke="#000" stroke-width="1.6611px"/>
<text x="690.55219" y="812.86035" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="690.55219" y="812.86035" font-size="16.611px" style="line-height:1.25">cs</tspan></text>
<path d="m553.43 618.61h110.58v101.32" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="649.83191" y="722.30597" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="649.83191" y="722.30597" font-size="6.6442px" style="line-height:1.25">CE</tspan></text>
<path d="m618.13 518.97v81.811h70.338l0.22581 119.15" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="678.35834" y="722.16583" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="678.35834" y="722.16583" font-size="6.6442px" style="line-height:1.25">D</tspan></text>
<text x="690.59619" y="766.43829" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="690.59619" y="766.43829" font-size="6.6442px" style="line-height:1.25">Q</tspan></text>
<g transform="matrix(1.6611 0 0 1.6611 -164.25 -262.12)">
<path d="m462.46 438.77v-30.694" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1px"/>
<text x="448.52087" y="403.62927" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="448.52087" y="403.62927" font-size="10px" style="line-height:1.25">SYNC</tspan></text>
<g transform="translate(135.76 -108.22)" fill="none" stroke="#000" stroke-width="1px">
<path d="m323.62 530.13 6.1607 6.1607"/>
<path d="m323.62 532.13 6.1607 6.1607"/>
</g>
</g>
<g transform="matrix(1.6611 0 0 1.6611 -177.12 -262.12)" fill="none" stroke="#000" stroke-width="1px">
<path d="m416.43 469.61v16.25" marker-end="url(#TriangleOutM)"/>
<g transform="translate(89.732 -55.444)">
<path d="m323.62 530.13 6.1607 6.1607"/>
<path d="m323.62 532.13 6.1607 6.1607"/>
</g>
</g>
<path d="m502.31 492.25h-20.218v-8.3053h-15.029" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-dasharray="1.66105601, 3.32211201" stroke-width="1.6611"/>
<g transform="matrix(1.6611 0 0 1.6611 282.82 -52.635)">
<text x="151.66971" y="482.07889" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="151.66971" y="482.07889" font-size="10px" style="line-height:1.25">Clock Gen</tspan></text>
<rect x="145.34" y="469.5" width="59.213" height="18" fill="none" stroke="#2e3436" stroke-linecap="square" stroke-linejoin="round" stroke-width="2"/>
</g>
<path d="m421.07 670.2h119.92v47.421" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="407.35889" y="718.92664" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="407.35889" y="718.92664" font-size="6.6442px" style="line-height:1.25">CE</tspan></text>
<text x="740.84778" y="812.84009" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="740.84778" y="812.84009" font-size="16.611px" style="line-height:1.25">three_wire</tspan></text>
<g transform="matrix(1.6611 0 0 1.6611 -339.88 -355.36)">
<text x="598.7677" y="555.29401" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="598.7677" y="555.29401" font-size="10px" style="line-height:1.25">Config</tspan></text>
<rect x="592.13" y="544.06" width="43.307" height="17.302" fill="none" stroke="#2e3436" stroke-linecap="square" stroke-linejoin="round" stroke-width="2"/>
</g>
<g fill="none" stroke="#000">
<path d="m718.99 563.32h59.612v231.35" marker-end="url(#TriangleOutM)" stroke-width="1.6611px"/>
<g>
<rect x="250.95" y="432.11" width="574.3" height="346.16" stroke-linecap="square" stroke-linejoin="round" stroke-width="4.9832"/>
<rect x="190.86" y="404.01" width="1.2773" height="0" stroke-linecap="square" stroke-linejoin="round" stroke-width="3.3221"/>
<path d="m528.07 548.15v-27.322" marker-end="url(#TriangleOutM)" stroke-dasharray="1.66105601, 3.32211201" stroke-width="1.6611"/>
<path d="m664.75 517.35v21.715" marker-end="url(#TriangleOutM)" stroke-dasharray="1.66105601, 3.32211201" stroke-width="1.6611"/>
</g>
<path d="m639.39 563.32h-58.483v156.03" marker-end="url(#TriangleOutM)" stroke-width="1.6611px"/>
</g>
<text x="584.97272" y="699.13763" fill="#000000" font-family="'Liberation Sans'" font-size="9.9663px" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="584.97272" y="699.13763" style="line-height:1.25">cpha</tspan><tspan x="584.97272" y="721.73303" style="line-height:1.25">cpol</tspan></text>
<text x="531.49805" y="537.35901" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="531.49805" y="537.35901" font-size="9.9663px" style="line-height:1.25">sleep_compare</tspan></text>
<path d="m664.37 465.87v-49.088" fill="none" marker-end="url(#TriangleOutM)" stroke="#000" stroke-width="1.6611px"/>
<text x="643.03412" y="408.55118" fill="#000000" font-family="'Liberation Sans'" letter-spacing="0px" word-spacing="0px" style="line-height:0%" xml:space="preserve"><tspan x="643.03412" y="408.55118" font-size="16.611px" style="line-height:1.25">active</tspan></text>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 13 KiB

95
docs/library/spi_engine/spi_engine_execution.rst Normal file
View File

@ -0,0 +1,95 @@
.. _spi_engine execution:
SPI Engine Execution Module
================================================================================
.. symbolator:: ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.v
:caption: spi_engine_execution
The SPI Engine Execution peripheral forms the heart of the SPI Engine framework.
It is responsible for handling a SPI Engine control stream and translates it
into low-level SPI bus transactions.
Files
-------------------------------------------------------------------------------
.. list-table::
:widths: 25 75
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/spi_engine_execution/spi_engine_execution.v`
- Verilog source for the peripheral.
* - :git-hdl:`master:library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl`
- TCL script to generate the Vivado IP-integrator project for the peripheral.
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
:path: library/spi_engine/spi_engine_execution
* - NUM_OF_CS
- Number of chip-select signals for the SPI bus (min: 1, max: 8).
* - DEFAULT_SPI_CFG
- Reset configuration value for the
:ref:`spi_engine spi-configuration-register`
* - DEFAULT_CLK_DIV
- Reset configuration value for the
:ref:`spi_engine prescaler-configuration-register`
* - DATA_WIDTH
- Data width of the parallel data stream. Will define the transaction's
granularity. Supported values: 8/16/24/32
* - NUM_OF_SDI
- Number of multiple SDI lines, (min: 1, max: 8)
Signal and Interface Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 25 65
:header-rows: 1
* - Name
- Type
- Description
* - ``clk``
- Clock
- All other signals are synchronous to this clock.
* - ``resetn``
- Synchronous active-low reset
- Resets the internal state machine of the core.
* - ``active``
- Output
- Indicates whether the peripheral is currently active and processing
commands.
* - ``ctrl``
- :ref:`spi_engine control-interface` slave
- SPI Engine Control stream that contains commands and data for the
execution module.
* - ``spi``
- :ref:`spi_engine spi-bus-interface` master
- Low-level SPI bus interface that is controlled by peripheral.
Theory of Operation
--------------------------------------------------------------------------------
The SPI Engine Execution module implements the physical access to the SPI bus.
It implements a small but powerful programmable state machine that translates a
SPI Engine command stream into low-level SPI bus access.
Communication with a command stream generator happens via the ``ctrl``
interface and the low-level SPI access is handled on the ``spi`` interface.
The ``active`` signal is asserted as long as the peripheral is busy executing
incoming commands.
Internally the SPI Engine execution module consists of an instruction encoder
that translates the incoming commands into an internal control signal, a
multi-function counter and compares unit that is responsible for handling the
timing and a shift register which holds the received and transmitted SPI data.
The module has an optional programmable pre-scaler register that can be used to
divide the external clock to the counter and compare unit.
.. image:: spi_engine.svg

90
docs/library/spi_engine/spi_engine_interconnect.rst Normal file
View File

@ -0,0 +1,90 @@
.. _spi_engine interconnect:
SPI Engine Interconnect Module
================================================================================
.. symbolator:: ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
:caption: axi_spi_engine
The SPI Engine Interconnect module allows connecting multiple
:ref:`spi_engine control-interface` masters to a single
:ref:`spi_engine control-interface` slave.
This enables multiple command stream generators to connect to a single
:ref:`spi_engine execution` and consequential give them access to the same SPI bus.
The interconnect modules take care of properly arbitrating between the different
command streams.
Combining multiple command stream generators in a design and connecting them to
a single execution module allows for the creation of flexible and efficient
designs using standard components.
Files
--------------------------------------------------------------------------------
.. list-table::
:widths: 25 75
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v`
- Verilog source for the peripheral.
* - :git-hdl:`master:library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl`
- TCL script to generate the Vivado IP-integrator project for the
peripheral.
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
:path: library/spi_engine/spi_engine_interconnect
* - DATA_WIDTH
- Data width of the parallel SDI/SDO data interfaces.
* - NUM_OF_SDI
- Number of SDI lines on the physical SPI interface.
Signal and Interface Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 25 65
:header-rows: 1
* - Name
- Type
- Description
* - ``clk``
- Clock
- A signals of the module are synchronous to this clock.
* - ``resetn``
- Synchronous active-low reset
- Resets the internal state of the module.
* - ``s0_ctrl``
- :ref:`spi_engine control-interface` slave
- Connects to the first control interface master
* - ``s1_ctrl``
- :ref:`spi_engine control-interface` slave
- Connects to the second control interface master
* - ``m_ctrl``
- :ref:`spi_engine control-interface` master
- Connects to the control interface slave
Theory of Operation
--------------------------------------------------------------------------------
The SPI Engine Interconnect module has multiple
:ref:`spi_engine control-interface` slave ports and a single
:ref:`spi_engine control-interface` master port.
It can be used to connect multiple command stream generators to a single command
execution engine. Arbitration between the streams is done on a priority
basis, streams with a lower index have higher priority. This means if commands
are present on two streams arbitration will be granted to the one with the lower
index. Once arbitration has been granted the port it was granted to stays in
control until it sends a SYNC command. When the interconnect module sees a SYNC
command arbitration will be re-evaluated after the SYNC command has been
completed. This makes sure that once a SPI transaction consisting of multiple
commands has been started it is able to complete without being interrupted by a
higher priority stream.

77
docs/library/spi_engine/spi_engine_offload.rst Normal file
View File

@ -0,0 +1,77 @@
.. _spi_engine offload:
SPI Engine Offload
================================================================================
.. symbolator:: ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.v
The SPI Engine Offload peripheral allows to store a SPI Engine command and SDO
data stream in a RAM or ROM module. The command stream is executed when the
``trigger`` signal is asserted. This allows the execution of SPI transactions
with a very short delay in reaction to a event.
Files
--------------------------------------------------------------------------------
.. list-table::
:widths: 25 75
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/spi_engine_offload/spi_engine_offload.v`
- Verilog source for the peripheral.
* - :git-hdl:`master:library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl`
- TCL script to generate the Vivado IP-integrator project for the
peripheral.
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
:path: library/spi_engine/spi_engine_offload
* - ASYNC_SPI_CLK
- If set to 1 the ``ctrl_clk`` and ``spi_clk`` are assumed to be
asynchronous.
* - CMD_MEM_ADDRESS_WIDTH
- Configures the size of the command stream storage. The size is
``2**CMD_MEM_ADDR_WIDTH`` entries.
* - SDO_MEM_ADDRESS_WIDTH
- Configures the size of the SDO data stream storage. The size is
``2**SDO_MEM_ADDR_WIDTH`` entries.
Signal and Interface Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 25 65
:header-rows: 1
* - Name
- Type
- Description
* - ``ctrl_clk``
- Clock
- The ``spi_engine_offload_ctrl`` signals are synchronous to this clock.
* - ``spi_clk``
- Clock
- The ``spi_engine_ctrl`` signals, ``offload_sdi`` signals and
trigger are synchronous to this clock.
* - ``spi_resetn``
- Synchronous active low reset
- Resets the internal state machine of the core.
* - ``trigger``
- Input
- When asserted the stored command and data stream is send out on the
``spi_engine_ctrl`` interface.
* - ``spi_engine_offload_ctrl``
- :ref:`spi_engine offload-control-interface` slave
- Control interface which allows to re-program the stored command and SDO
data stream.
* - ``spi_engine_ctrl``
- :ref:`spi_engine control-interface` master
- SPI Engine Control stream that contains commands and data.
* - ``offload_sdi``
- Streaming AXI master
- Output stream of the received SPI data.

308
docs/library/spi_engine/tutorial.rst Normal file
View File

@ -0,0 +1,308 @@
.. _spi_engine tutorial:
SPI Engine Tutorial - PulSAR-ADC
================================================================================
The goal of this tutorial is to present the process of adding
:ref:`spi_engine` support for an ADI precision converter or family of converters
using a few simple steps.
The target carrier is the Digilent Cora-z7s board using a Pmod connector.
Evaluating the target device
--------------------------------------------------------------------------------
The aim of this project is to provide support for a family of ADCs which come in
the form of
:dokuwiki:`pulsar-adc-pmods:resources/eval/user-guides/circuits-from-the-lab/pulsar-adc-pmods`.
They all share the same interface and the same PCB, the differences being found
in their performance. The table below offers a comparison between the timing
parameters of the SPI interface for these devices. Using this table we can see
how much they have in common and where the key differences are. All the values
are for 3.3V VIO since the Cora-z7s is only 3.3V capable.
+----------+----------+------+----------+----------+----------+----------+
| Device | Re | KSPS | T\_ | T_CONV | T_CYC | T_ACQ |
| | solution | | SPI_SCLK | max [ns] | min [ns] | min [ns] |
| | | | min [ns] | | | |
+==========+==========+======+==========+==========+==========+==========+
| AD7942 | 14 | 250 | 18 | 2200 | 4000 | 1800 |
+----------+----------+------+----------+----------+----------+----------+
| AD7946 | 14 | 500 | 15 | 1600 | 2000 | 400 |
+----------+----------+------+----------+----------+----------+----------+
| AD7988-1 | 16 | 100 | 12 | 9500 | 1000 | 500 |
+----------+----------+------+----------+----------+----------+----------+
| AD7685 | 16 | 250 | 15 | 2200 | 4000 | 1800 |
+----------+----------+------+----------+----------+----------+----------+
| AD7687 | 16 | 250 | 10 | 2200 | 4000 | 1800 |
+----------+----------+------+----------+----------+----------+----------+
| AD7691 | 16 | 250 | 15 | 2200 | 4000 | 1800 |
+----------+----------+------+----------+----------+----------+----------+
| AD7686 | 16 | 500 | 15 | 1600 | 2000 | 400 |
+----------+----------+------+----------+----------+----------+----------+
| AD7693 | 16 | 500 | 15 | 1600 | 2000 | 400 |
+----------+----------+------+----------+----------+----------+----------+
| AD7 | 16 | 500 | 12 | 1600 | 2000 | 400 |
| 988-5(B) | | | | | | |
+----------+----------+------+----------+----------+----------+----------+
| AD7 | 16 | 500 | 12 | 1200 | 2000 | 800 |
| 988-5(C) | | | | | | |
+----------+----------+------+----------+----------+----------+----------+
| AD7980 | 16 | 1000 | 10 | 710 | 1000 | 290 |
+----------+----------+------+----------+----------+----------+----------+
| AD7983 | 16 | 1333 | 12 | 500 | 750 | 250 |
+----------+----------+------+----------+----------+----------+----------+
| AD7690 | 18 | 400 | 15 | 2100 | 2500 | 400 |
+----------+----------+------+----------+----------+----------+----------+
| AD7982 | 18 | 1000 | 12 | 710 | 1000 | 290 |
+----------+----------+------+----------+----------+----------+----------+
| AD7984 | 18 | 1333 | 12 | 500 | 750 | 250 |
+----------+----------+------+----------+----------+----------+----------+
The device with the most demanding timing specifications is the AD7984. It
requires the highest amount of data (18 bit) to be read in the least amount of
time (T_ACQ 250ns). The other devices will work with the same HDL by just using
different “downgraded” configurations.
SPI Engine hierarchy instantiation
--------------------------------------------------------------------------------
The SPI Engine can be implemented in two ways, either by placing and connecting
each IP individually or by using the function provided by the spi_engine.tcl
script :git-hdl:`master:library/spi_engine/scripts/spi_engine.tcl`
Using the script ensures that the correct connections are being made and that
the IP cores will receive the correct parameter configuration since certain
parameters need to be set to the same value. The function takes the following
argumets
.. code:: tcl
proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {sdi_delay 0} {echo_sclk 0}}
**data_width** will set the width of the data bus / data line used by the SPI
engine to connect to the DMA and which serves the purpose of sending ADC sample
data to the DDR memory. The data_width value will also set the maximum word
length for the SPI transfer. Valid values are are 8/16/24/32. The DMA valid
values are 16/32/64/128[…]. Since the Pulsar_ADC devices are all single SDI/SDO
and some of them require 18bit transfers, this value will be rounded to 32bit.
**async_spi_clk** will chose the reference clock for the SPI Engine. Setting
this parameter to 0 will configure the hierarchy to use the axi clock (100MHz)
as the reference clock. Setting it to 1 will allow for an external referece
clock (spi_clk). Because some devices need 80MHz SCLK, a 160MHz reference clock
is required which implies an external reference.
**num_cs** selects the number of CS lines.
**num_sdi** selects the number of SDI lines.
**sdi_delay** The latch of the SDI line can be delayed with 1, 2 or 3 SPI core
clock cycle. Needed for designs with high SCLK rate (>50MHz).
Configuration tcl code and result below:
.. code:: tcl
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
set data_width 32
set async_spi_clk 1
set num_cs 1
set num_sdi 1
set sdi_delay 1
set hier_spi_engine spi_pulsar_adc
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
.. image:: tutorial/pulsar_hdl_1.svg
:align: center
SPI Engine reference clock
--------------------------------------------------------------------------------
There are 3 categories of devices depending on the SPI interface clock (SCLK):
80 MHz, 50MHz (one device) and 40MHz. SCLK will be derived from the spi_clk
reference signal using an internal prescaler with this formula:
.. math::
f_{sclk} = \frac{f_{clk}}{((div + 1) * 2)}
Therefore a 160MHz reference clock will be needed for the 40 and 80MHz variants
and 100MHz for the 50MHz SCLK. The axi_clkgen IP core will be used to obtain the
160MHz which will be the default value to ensure that the design bitstream meets
timing. This IP can also be configured from software to output 100MHz.
.. code:: tcl
ad_ip_instance axi_clkgen spi_clkgen
ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
Clock source for IP and spi_clk connection
.. code:: tcl
ad_connect $sys_cpu_clk spi_clkgen/clk
ad_connect spi_clk spi_clkgen/clk_0
ad_connect spi_clk spi_pulsar_adc/spi_clk
ad_connect spi_clk axi_pulsar_adc_dma/s_axis_aclk
AD7984 Timing diagram
--------------------------------------------------------------------------------
The operation mode that will be implemented using the SPI Engine in offload mode
is the :math:`\overline{CS}` Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High),
as shown in :datasheet:`AD7984:[{"num"%3A51%2C"gen"%3A0}%2C{"name"%3A"XYZ"}%2C52%2C713%2C0]`,
page 18, figure 30.
Key timing characteristics:
.. code:: tcl
18 bit transfers
750 ns T_CYC
500 ns T_CONV
250 ns T_ACQ
12 ns T_SCLK @ >3V VIO (cora pmod is 3V3)
Sample rate control
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The T_CYC parameter is the what sets the maximum sample rate (1/750 => 1333
KSPS). To achieve precise control over the the sample rate we will use a PWM
generator (AXI PWM GEN) using the spi_clk as reference. The spi_clock is used to
avoid clock domain crossing mechanisms which will introduce latency, decreasing
the overall performance of the system.
.. code:: tcl
ad_ip_instance axi_pwm_gen pulsar_adc_trigger_gen
ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_PERIOD 120
ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_WIDTH 1
ad_connect spi_clk pulsar_adc_trigger_gen/ext_clk
ad_connect $sys_cpu_clk pulsar_adc_trigger_gen/s_axi_aclk
ad_connect sys_cpu_resetn pulsar_adc_trigger_gen/s_axi_aresetn
ad_connect pulsar_adc_trigger_gen/pwm_0 $hier_spi_engine/offload/trigger
.. image:: tutorial/pwm_trigger_1.svg
:align: right
:width: 50%
Since the AXI PWM IP core is connected to the system with AXI4 Lite, the
software will be able to change the frequency of its output at any time. The
resolution of the PWM period is the reference clock period (spi_clk) providing a
wide range of options.
The PWM output will be used as a trigger signal for the offload IP core.
The CS signal will be used to drive CNV and will have the same frequency as the
PWM-trgger signal.
DMA setup
--------------------------------------------------------------------------------
DMA destination bus (connection to Zynq – DDR memory) shall always be 64 bit
wide AXI4 MM and source bus shall be data_wdth \* num_sdi = 32 bit, AXI4 Stream.
.. code:: tcl
ad_ip_instance axi_dmac axi_pulsar_adc_dma
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width //32
ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
The system clock is used as destination clock and the spi_clk is used as source
clock
.. code:: tcl
ad_connect spi_clk axi_pulsar_adc_dma/s_axis_aclk
ad_mem_hp1_interconnect $sys_cpu_clk axi_pulsar_adc_dma/m_dest_axi
System Top
--------------------------------------------------------------------------------
This is a layer on top of the system_wrapper generated by Vivado used to
instantiate IO buffers, I/ODDRs or to create some custom connections which would
be harder to do in the block design. It also alows for more consistency across
projects. In this particular case we use it to place an IO buffer for the ADC
power down signal (pulsar_adc_spi_pd).
System Constraints
--------------------------------------------------------------------------------
The system_constr.xdc file inside the carrier folder
(/coraz7s/system_constr.xdc) is used for defining the physical FPGA pins used by
this particular project (in this case the AD7984 ADC), excluding the "common"
design for the carrier board which has a separate constraints file (i.e. DDR
pins, Ethernet, UART etc). It also contains some timing constraints specific to
the SPI Engine.
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of
[get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0
[get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter
name=~*spi_clkgen*i_mmcm]]
.. code::
# relax the SDO path to help closing timing at high frequencies
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk]
set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk]
Testbench
--------------------------------------------------------------------------------
To check the overall performance of the design and also to expose any major
bugs, the system can be tested using a testbench (:git-testbenches:`main:`).
The testbench framework is designed to use the same bd.tcl as the actual project
:git-testbenches:`main:pulsar_adc_pmdz/system_bd.tcl#L50`
The setup assumes the testbenches repo is cloned inside the hdl repo. To build
the testbench project simply run :code:`make cfg1` from the
*hdl/testbenches/pulsar_adc_pmdz/* folder. Besides exposing possible bugs,
using the testbench will provide the user with an early way of evaluating the
timing of the design. The testbench can also be a very useful tool for IP
development.
Evaluating the result
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Due to the limits of the SPI Engine cores, T_CYC needs to be increased slightly
over the minimum value, to ensure that the design meets the T_CONV minimum. This
will slightly lower the maximum sample rate of the design from 1.333 MSPS to
1.322 MSPS.
.. image:: tutorial/pulsar_hdl_timing_2.png
:width: 100%
Holding CS high for 500ns ensures that we always meet T_CONV minimum.
.. image:: tutorial/pulsar_hdl_timing_3.png
:width: 100%
The 250ns minimum T_ACQ is alse met with a slightly higher value of 256.25ns.
.. image:: tutorial/pulsar_hdl_timing_4.png
:width: 100%
Overall the project appears to be functional and ready for the next step in
development, using software.
Software section
--------------------------------------------------------------------------------
.. important::
This section is still under development.

396
docs/library/spi_engine/tutorial/pulsar_hdl_1.svg Normal file
View File

@ -0,0 +1,396 @@
<svg width="738.61" height="220.28" version="1.1" viewBox="0 0 738.61 220.28" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<defs>
<clipPath id="w">
<path d="m0 0h1245v370h-1245z"/>
</clipPath>
<mask id="v" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="u" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAACpJREFUCJljYGD4/x+CmRgIAGYGBkZGBgZhtp8MTFBt/HiUE20uiQCLuQApXBAg21LM9QAAAABJRU5ErkJggg=="/>
</mask>
<mask id="t" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="s" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABpJREFUCJlj/M/AyADBTAxwMHSY5xkYGBgYAFXpA/LpoCBQAAAAAElFTkSuQmCC"/>
</mask>
<mask id="r" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="q" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABpJREFUCJlj/M/AyADBTAxwMHSY5xkYGBgYAFXpA/LpoCBQAAAAAElFTkSuQmCC"/>
</mask>
<mask id="p" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="o" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABpJREFUCJlj/M/AyADBTAxwMHSY5xkYGBgYAFXpA/LpoCBQAAAAAElFTkSuQmCC"/>
</mask>
<mask id="n" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="m" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABRJREFUCJljYGD4/x+CmRjgYKgxAQ0XBB9x0cwkAAAAAElFTkSuQmCC"/>
</mask>
<mask id="l" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="k" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABRJREFUCJljYGD4/x+CmRjgYKgxAQ0XBB9x0cwkAAAAAElFTkSuQmCC"/>
</mask>
<mask id="j" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="i" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABpJREFUCJlj/M/AyADBTAxwMHSY5xkYGBgYAFXpA/LpoCBQAAAAAElFTkSuQmCC"/>
</mask>
<mask id="h" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="g" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABRJREFUCJljYGD4/x+CmRjgYKgxAQ0XBB9x0cwkAAAAAElFTkSuQmCC"/>
</mask>
<mask id="f" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="e" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAAEBJREFUCJlj/M8AA0wMCMDLxsDAzcrAxCaFJMj4n4GRAYKR1WIFjNjNxaUWv7mMcJqF4f/////////w//9/JCsAiJ8TO7U6ytEAAAAASUVORK5CYII="/>
</mask>
<mask id="d" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="c" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABRJREFUCJljYGD4/x+CmRjgYKgxAQ0XBB9x0cwkAAAAAElFTkSuQmCC"/>
</mask>
<mask id="b" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="a" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABpJREFUCJlj/M/AyADBTAxwMHSY5xkYGBgYAFXpA/LpoCBQAAAAAElFTkSuQmCC"/>
</mask>
</defs>
<g transform="matrix(.59373 0 0 .59373 38.4 418.16)">
<g transform="translate(-64.675 -704.29)" clip-path="url(#w)">
<g transform="translate(97)">
<path d="m-97 0h1244v371h-1244z" fill="#fff"/>
<path d="m0 150-7 7h-14v-14h14z" fill="#ddd4d0"/>
<path d="m0 150-7 7h-14v-14h14z" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<g transform="translate(-25,150)">
<text transform="translate(-34.008,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 3.336 7.3319998 9.9960003 16.667999 23.34 30.011999" y="0">trigger</tspan></text>
</g>
<path d="m0 240-7 7h-14v-14h14z" fill="#ddd4d0"/>
<path d="m0 240-7 7h-14v-14h14z" fill="none" stroke="#2a5e6f" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(-25,240)">
<text transform="translate(-28.008,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 19.344 25.344" y="0">s_axi</tspan></text>
</g>
<path d="m0 260-7 7h-14v-14h14z" fill="#ddd4d0"/>
<path d="m0 260-7 7h-14v-14h14z" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<g transform="translate(-25,260)">
<text transform="translate(-14.664,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 8.6639996" y="0">clk</tspan></text>
</g>
<path d="m0 280-7 7h-14v-14h14z" fill="#ddd4d0"/>
<path d="m0 280-7 7h-14v-14h14z" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<g transform="translate(-25,280)">
<text transform="translate(-33.348,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 3.9960001 10.668 16.667999 23.34 26.676001" y="0">resetn</tspan></text>
</g>
<path d="m0 300-7 7h-14v-14h14z" fill="#ddd4d0"/>
<path d="m0 300-7 7h-14v-14h14z" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<g transform="translate(-25,300)">
<text transform="translate(-36.672,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.007999 30.672001" y="0">spi_clk</tspan></text>
</g>
<path d="m57 212h266l3 1 2 1 1 2 1 3v102l-1 3-1 2-2 1-3 1h-266l-3-1-2-1-1-2-1-3v-102l1-3 1-2 2-1z" fill="#edf6fe"/>
<g transform="translate(190,210)">
<text transform="translate(-75.03,-2.484)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 38.015999 44.015999 50.688 54.683998 61.355999 68.028 74.699997 80.699997 87.372002 94.043999 100.044 102.708 109.38 113.376 120.048 126.72 136.716 143.388" y="0">spi_pulsar_adc_axi_regmap</tspan></text>
</g>
<g transform="translate(190,330)">
<text transform="translate(-56.364,8.616)" fill="#41619f" font-family="Helvetica" font-size="12px"><tspan x="0 6.6719999 12.672 15.336 22.007999 28.007999 34.68 37.344002 44.015999 50.688 57.360001 64.031998 66.695999 73.367996 80.040001 86.711998 92.711998 99.384003 106.056" y="0">axi_spi_engine_v1_0</tspan></text>
</g>
<path d="m40 231h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,52,248)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#v)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,40,249)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#u)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAAFhJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiIBI8xEQoBoE5EU/kcx3Dl7IYNL2kw4nwXVFQjwje03AzMLJz3caJ83Dx522PiDIxwHv0KqhSMAhtEbD3HNJ58AAAAASUVORK5CYII="/>
</g>
<g transform="translate(67,240)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001" y="0">s_axi</tspan></text>
</g>
<path d="m330 231h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,313,248)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#t)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,330,249)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#s)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADRJREFUKJFjdMuZ/P8nEzfDwUlJDAwMDAz2efMYGBgYMPhMDESCgVT4k4l7oKweVThIFQIAk2UKdEPgAjEAAAAASUVORK5CYII="/>
</g>
<g transform="translate(313,240)">
<text transform="translate(-67.25,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.9 29.459999 35.02 37.240002 42.799999 48.360001 53.919998 58.919998 61.700001 65.029999" y="0">spi_engine_ctrl</tspan></text>
</g>
<path d="m330 251h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,313,268)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#r)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,330,269)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#q)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADRJREFUKJFjdMuZ/P8nEzfDwUlJDAwMDAz2efMYGBgYMPhMDESCgVT4k4l7oKweVThIFQIAk2UKdEPgAjEAAAAASUVORK5CYII="/>
</g>
<g transform="translate(313,260)">
<text transform="translate(-108.39,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.9 29.459999 35.02 37.240002 42.799999 48.360001 53.919998 59.48 62.259998 65.040001 67.260002 72.82 78.379997 83.940002 89.5 94.5 97.279999 100.61 102.83" y="0">spi_engine_offload_ctrl0</tspan></text>
</g>
<path d="m40 260h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(52,260)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001 23.34 28.9 34.459999 39.459999 41.68" y="0">s_axi_aclk</tspan></text>
</g>
<path d="m50 280c0-1.657-1.3431-3-3-3s-3 1.343-3 3 1.3431 3 3 3 3-1.343 3-3" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<path d="m40 280h4" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(52,280)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001 23.34 28.9 34.459999 37.790001 43.349998 48.349998 53.91 56.689999" y="0">s_axi_aresetn</tspan></text>
</g>
<path d="m340 280h-10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(328,280)">
<text transform="translate(-11.11,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 2.22 5.5500002" y="0">irq</tspan></text>
</g>
<path d="m40 300h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(52,300)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.34 25.559999" y="0">spi_clk</tspan></text>
</g>
<path d="m336 300c0-1.657-1.343-3-3-3s-3 1.343-3 3 1.343 3 3 3 3-1.343 3-3" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<path d="m340 300h-4" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(328,300)">
<text transform="translate(-46.13,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 21.67 27.23 32.23 37.790001 40.57" y="0">spi_resetn</tspan></text>
</g>
<g fill="none" stroke="#41619f" stroke-miterlimit="10">
<path d="m57 212h266"/>
<path d="m330 219c.003-.111.003-.222 0-.333-.092-3.774-3.226-6.759-7-6.667"/>
<path d="m330 219v102"/>
<path d="m323 328c.111.003.222.003.333 0 3.774-.092 6.759-3.226 6.667-7"/>
<path d="m323 328h-266"/>
<path d="m50 321c-.0027.111-.0027.222 0 .333.092 3.774 3.2261 6.759 7 6.667"/>
<path d="m50 321v-102"/>
<path d="m57 212c-.1111-.003-.2222-.003-.3333 0-3.774.092-6.7587 3.226-6.6667 7"/>
</g>
<path d="m427 192h126l3 1 2 1 1 2 1 3v102l-1 3-1 2-2 1-3 1h-126l-3-1-2-1-1-2-1-3v-102l1-3 1-2 2-1z" fill="#edf6fe"/>
<g transform="translate(490,190)">
<text transform="translate(-76.368,-2.484)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 38.015999 44.015999 50.688 54.683998 61.355999 68.028 74.699997 80.699997 87.372002 90.036003 96.708 100.044 106.716 110.712 116.712 123.384 130.056 136.728 143.39999 149.39999" y="0">spi_pulsar_adc_interconnect</tspan></text>
</g>
<g transform="translate(490,310)">
<text transform="translate(-81.378,8.616)" fill="#41619f" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 42.023998 44.688 51.360001 58.032001 64.704002 67.367996 74.040001 77.375999 84.047997 88.043999 94.043999 100.716 107.388 114.06 120.732 126.732 130.06799 136.74001 142.74001 149.412 156.084" y="0">spi_engine_interconnect_v1_0</tspan></text>
</g>
<path d="m560 241h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,543,258)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#p)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,560,259)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#o)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADRJREFUKJFjdMuZ/P8nEzfDwUlJDAwMDAz2efMYGBgYMPhMDESCgVT4k4l7oKweVThIFQIAk2UKdEPgAjEAAAAASUVORK5CYII="/>
</g>
<g transform="translate(543,250)">
<text transform="translate(-27.22,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 8.3299999 13.89 18.889999 21.67 25" y="0">m_ctrl</tspan></text>
</g>
<path d="m410 211h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,422,228)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#n)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,410,229)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#m)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAACpJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiLBqMJRhYNJIQDXtQcj0yYcxwAAAABJRU5ErkJggg=="/>
</g>
<g transform="translate(437,220)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001 23.9 27.23" y="0">s0_ctrl</tspan></text>
</g>
<path d="m410 231h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,422,248)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#l)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,410,249)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#k)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAACpJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiLBqMJRhYNJIQDXtQcj0yYcxwAAAABJRU5ErkJggg=="/>
</g>
<g transform="translate(437,240)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001 23.9 27.23" y="0">s1_ctrl</tspan></text>
</g>
<path d="m410 260h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(422,260)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 7.2199998" y="0">clk</tspan></text>
</g>
<path d="m420 280c0-1.657-1.343-3-3-3s-3 1.343-3 3 1.343 3 3 3 3-1.343 3-3" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<path d="m410 280h4" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(422,280)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 3.3299999 8.8900003 13.89 19.450001 22.23" y="0">resetn</tspan></text>
</g>
<g fill="none" stroke="#41619f" stroke-miterlimit="10">
<path d="m427 192h126"/>
<path d="m560 199c.003-.111.003-.222 0-.333-.092-3.774-3.226-6.759-7-6.667"/>
<path d="m560 199v102"/>
<path d="m553 308c.111.003.222.003.333 0 3.774-.092 6.759-3.226 6.667-7"/>
<path d="m553 308h-126"/>
<path d="m420 301c-.003.111-.003.222 0 .333.092 3.774 3.226 6.759 7 6.667"/>
<path d="m420 301v-102"/>
<path d="m427 192c-.111-.003-.222-.003-.333 0-3.774.092-6.759 3.226-6.667 7"/>
</g>
<path d="m647 42h286l3 1 2 1 1 2 1 3v122l-1 3-1 2-2 1-3 1h-286l-3-1-2-1-1-2-1-3v-122l1-3 1-2 2-1z" fill="#edf6fe"/>
<g transform="translate(790,40)">
<text transform="translate(-61.698,-2.484)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 38.015999 44.015999 50.688 54.683998 61.355999 68.028 74.699997 80.699997 87.372002 94.043999 97.379997 100.716 103.38 110.052 116.724" y="0">spi_pulsar_adc_offload</tspan></text>
</g>
<g transform="translate(790,180)">
<text transform="translate(-66.708,8.616)" fill="#41619f" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 42.023998 44.688 51.360001 58.032001 64.704002 71.375999 74.711998 78.047997 80.711998 87.384003 94.056 100.728 107.4 113.4 120.072 126.744" y="0">spi_engine_offload_v1_0</tspan></text>
</g>
<path d="m940 91h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,923,108)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#j)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,940,109)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#i)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADRJREFUKJFjdMuZ/P8nEzfDwUlJDAwMDAz2efMYGBgYMPhMDESCgVT4k4l7oKweVThIFQIAk2UKdEPgAjEAAAAASUVORK5CYII="/>
</g>
<g transform="translate(923,100)">
<text transform="translate(-67.25,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.9 29.459999 35.02 37.240002 42.799999 48.360001 53.919998 58.919998 61.700001 65.029999" y="0">spi_engine_ctrl</tspan></text>
</g>
<path d="m630 61h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,642,78)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#h)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,630,79)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#g)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAACpJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiLBqMJRhYNJIQDXtQcj0yYcxwAAAABJRU5ErkJggg=="/>
</g>
<g transform="translate(657,70)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.9 29.459999 35.02 37.240002 42.799999 48.360001 53.919998 59.48 62.259998 65.040001 67.260002 72.82 78.379997 83.940002 89.5 94.5 97.279999 100.61" y="0">spi_engine_offload_ctrl</tspan></text>
</g>
<path d="m940 111h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,923,128)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#f)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,940,129)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#e)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAAHxJREFUKJG9kiEOgDAMRd/IAgjUrsIBdpcJJIeZRHCXXQWNRJCwMAQJgmSkAqj7afv/S1Nl+zEhqEIyBFDEOjGbhuAdwTuqUrOs26nNxGwa4p5QgCha234EIHgHQE6LGcXRYseL8TXHDxn/v6N+bp8ebTegsv94y8oz3tYP5fQtpbkgnLwAAAAASUVORK5CYII="/>
</g>
<g transform="translate(923,120)">
<text transform="translate(-48.36,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5.5599999 8.3400002 11.12 13.34 18.9 24.459999 30.02 35.580002 40.580002 46.139999" y="0">offload_sdi</tspan></text>
</g>
<path d="m630 90h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(642,90)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 7.7800002 11.11 13.33 18.889999 23.889999 26.110001" y="0">ctrl_clk</tspan></text>
</g>
<path d="m630 110h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(642,110)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.34 25.559999" y="0">spi_clk</tspan></text>
</g>
<path d="m640 130c0-1.657-1.343-3-3-3s-3 1.343-3 3 1.343 3 3 3 3-1.343 3-3" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<path d="m630 130h4" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(642,130)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 21.67 27.23 32.23 37.790001 40.57" y="0">spi_resetn</tspan></text>
</g>
<path d="m630 150h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(642,150)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 2.78 6.1100001 8.3299999 13.89 19.450001 25.01" y="0">trigger</tspan></text>
</g>
<g fill="none" stroke="#41619f" stroke-miterlimit="10">
<path d="m647 42h286"/>
<path d="m940 49c.003-.1111.003-.2222 0-.3333-.092-3.774-3.226-6.7587-7-6.6667"/>
<path d="m940 49v122"/>
<path d="m933 178c.111.003.222.003.333 0 3.774-.092 6.759-3.226 6.667-7"/>
<path d="m933 178h-286"/>
<path d="m640 171c-.003.111-.003.222 0 .333.092 3.774 3.226 6.759 7 6.667"/>
<path d="m640 171v-122"/>
<path d="m647 42c-.111-.0027-.222-.0027-.333 0-3.774.092-6.759 3.2261-6.667 7"/>
</g>
<path d="m737 222h106l3 1 2 1 1 2 1 3v82l-1 3-1 2-2 1-3 1h-106l-3-1-2-1-1-2-1-3v-82l1-3 1-2 2-1z" fill="#edf6fe"/>
<g transform="translate(790,220)">
<text transform="translate(-69.366,-2.484)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 38.015999 44.015999 50.688 54.683998 61.355999 68.028 74.699997 80.699997 87.372002 94.043999 100.044 106.716 112.716 119.388 122.724 125.388 132.06" y="0">spi_pulsar_adc_execution</tspan></text>
</g>
<g transform="translate(790,320)">
<text transform="translate(-74.376,8.616)" fill="#41619f" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 42.023998 44.688 51.360001 58.032001 64.704002 71.375999 77.375999 84.047997 90.047997 96.720001 100.056 102.72 109.392 116.064 122.736 128.73599 135.408 142.08" y="0">spi_engine_execution_v1_0</tspan></text>
</g>
<path d="m720 241h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,732,258)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#d)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,720,259)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#c)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAACpJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiLBqMJRhYNJIQDXtQcj0yYcxwAAAABJRU5ErkJggg=="/>
</g>
<g transform="translate(747,250)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 7.7800002 11.11" y="0">ctrl</tspan></text>
</g>
<path d="m850 251h10v18h-10z" fill="#edf6fe"/>
<g transform="matrix(15,0,0,-15,833,268)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#b)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(10,0,0,-18,850,269)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#a)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADRJREFUKJFjdMuZ/P8nEzfDwUlJDAwMDAz2efMYGBgYMPhMDESCgVT4k4l7oKweVThIFQIAk2UKdEPgAjEAAAAASUVORK5CYII="/>
</g>
<g transform="translate(833,260)">
<text transform="translate(-12.78,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56" y="0">spi</tspan></text>
</g>
<path d="m720 270h10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(732,270)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 7.2199998" y="0">clk</tspan></text>
</g>
<path d="m730 290c0-1.657-1.343-3-3-3s-3 1.343-3 3 1.343 3 3 3 3-1.343 3-3" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<path d="m720 290h4" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(732,290)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 3.3299999 8.8900003 13.89 19.450001 22.23" y="0">resetn</tspan></text>
</g>
<path d="m860 280h-10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(848,280)">
<text transform="translate(-26.12,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5.5599999 10.56 13.34 15.56 20.559999" y="0">active</tspan></text>
</g>
<g fill="none" stroke="#41619f" stroke-miterlimit="10">
<path d="m737 222h106"/>
<path d="m850 229c.003-.111.003-.222 0-.333-.092-3.774-3.226-6.759-7-6.667"/>
<path d="m850 229v82"/>
<path d="m843 318c.111.003.222.003.333 0 3.774-.092 6.759-3.226 6.667-7"/>
<path d="m843 318h-106"/>
<path d="m730 311c-.003.111-.003.222 0 .333.092 3.774 3.226 6.759 7 6.667"/>
<path d="m730 311v-82"/>
<path d="m737 222c-.111-.003-.222-.003-.333 0-3.774.092-6.759 3.226-6.667 7"/>
</g>
<path d="m990 120v-7h14l7 7-7 7h-14z" fill="#ddd4d0"/>
<path d="m990 120v-7h14l7 7-7 7h-14z" fill="none" stroke="#2a5e6f" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(1015,120)">
<text transform="translate(0,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 9.9960003 16.667999 23.34 29.34 32.004002 38.004002 44.675999 50.675999 57.348 67.344002 74.015999 76.68" y="0">m_axis_sample</tspan></text>
</g>
<path d="m990 260v-7h14l7 7-7 7h-14z" fill="#ddd4d0"/>
<path d="m990 260v-7h14l7 7-7 7h-14z" fill="none" stroke="#2a5e6f" stroke-miterlimit="10" stroke-width="3"/>
<g transform="translate(1015,260)">
<text transform="translate(0,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 9.9960003 16.667999 22.667999 29.34" y="0">m_spi</tspan></text>
</g>
<path d="m990 350v-7h14l7 7-7 7h-14z" fill="#ddd4d0"/>
<path d="m990 350v-7h14l7 7-7 7h-14z" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<g transform="translate(1015,350)">
<text transform="translate(0,4.308)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 2.664 6.6599998" y="0">irq</tspan></text>
</g>
<g fill="none" stroke-miterlimit="10">
<path d="m0 240h40" stroke="#41619f" stroke-width="4"/>
<g stroke="#102235">
<path d="m0 260h40"/>
<path d="m0 280h40"/>
<path d="m0 300h20v60h350v-220h230"/>
</g>
</g>
<path d="m598 108h5v5h-5z" fill="#102235"/>
<path d="m598 138h5v5h-5z" fill="#102235"/>
<path d="m20 300h20" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<path d="m18 298h5v5h-5z" fill="#102235"/>
<path d="m370 260h40" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<path d="m368 258h5v5h-5z" fill="#102235"/>
<g fill="none" stroke-miterlimit="10">
<g stroke="#102235">
<path d="m630 90h-30v180h120"/>
<path d="m600 110h30"/>
<path d="m340 280h20v70h630"/>
</g>
<path d="m340 240h70" stroke="#41619f" stroke-width="4"/>
<path d="m340 260.55h20v-190h270" stroke="#41619f" stroke-width="4"/>
<path d="m410 280h-30v60h230v-210h20" stroke="#102235"/>
<path d="m610 290h110" stroke="#102235"/>
</g>
<path d="m608 288h5v5h-5z" fill="#102235"/>
<path d="m340 300h40" fill="none" stroke="#102235" stroke-miterlimit="10"/>
<path d="m378 298h5v5h-5z" fill="#102235"/>
<g fill="none" stroke-miterlimit="10">
<g stroke="#41619f" stroke-width="4">
<path d="m860 260h130"/>
<path d="m570 250h150"/>
<path d="m950 120h40"/>
<path d="m410 220h-30v-210h590v90h-20"/>
</g>
<path d="m0 150h630" stroke="#102235"/>
</g>
</g>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 37 KiB

BIN
docs/library/spi_engine/tutorial/pulsar_hdl_timing_2.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 8.1 KiB

BIN
docs/library/spi_engine/tutorial/pulsar_hdl_timing_3.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 8.0 KiB

BIN
docs/library/spi_engine/tutorial/pulsar_hdl_timing_4.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 7.7 KiB

248
docs/library/spi_engine/tutorial/pwm_trigger_1.svg Normal file
View File

@ -0,0 +1,248 @@
<svg width="180" height="96" version="1.1" viewBox="0 0 180 96" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<defs>
<mask id="i" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="h" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAACpJREFUCJljYGD4/x+CmRgIAGYGBkZGBgZhtp8MTFBt/HiUE20uiQCLuQApXBAg21LM9QAAAABJRU5ErkJggg=="/>
</mask>
<mask id="g" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAACwAAAAsCAAAAAA77wXdAAAAAXNCSVQI5gpbmQAAAMpJREFUOI3t1aEKwlAUxvG/dzAQBNPqwGQSBJPJ6jMMTL6BD+AbLPkMPoDVtCzzASxLgiIYBEG2cgxzbIbtnmKRfekc+ME9nHAu/CqdspzUmefpu++vE2lItHRKO7s1URGR2C/sNLVZkcTLbe9styK7HK80VmSCARa6xQUYYKjDIwz0ujrsYcCxOwAcjFICtLjFLf5nnClphoHXQ4evGOCowwcAAtXFTQcAOLEGh58H/Ivd7t1iHD+y2Y1bmX6+jWt/oXscjnU7qOYNsGJn24jkxrcAAAAASUVORK5CYII="/>
</mask>
<mask id="f" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="e" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABpJREFUCJlj/M/AyADBTAxwMHSY5xkYGBgYAFXpA/LpoCBQAAAAAElFTkSuQmCC"/>
</mask>
<mask id="d" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="c" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAAEBJREFUCJlj/M8AA0wMCMDLxsDAzcrAxCaFJMj4n4GRAYKR1WIFjNjNxaUWv7mMcJqF4f/////////w//9/JCsAiJ8TO7U6ytEAAAAASUVORK5CYII="/>
</mask>
<mask id="b" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAAAAAA6mKC9AAAAAXNCSVQI5gpbmQAAAEFJREFUGJWdzEkKgDAQRNGXVjT3v3C7CELSCoK1Kfg1ULQNO0POuMnUQcBIYwJWEPtRMuT92Sz3rfTeJo/GD/CtC3I5CTEZiEGVAAAAAElFTkSuQmCC"/>
</mask>
<mask id="a" x="0" y="0" width="1" height="1" maskUnits="userSpaceOnUse">
<image width="1" height="1" image-rendering="optimizeSpeed" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAAAAABH3BCXAAAAAXNCSVQI5gpbmQAAABVJREFUCJljYGD4/x+CmRgIg0GqFgAm8hP3KF94MAAAAABJRU5ErkJggg=="/>
</mask>
</defs>
<g transform="matrix(0 -.29074 .29074 0 203.03 1017.6)">
<g transform="rotate(90 2592.5 1274.5)">
<path d="m997 242h226l3 1 2 1 1 2 1 3v122l-1 3-1 2-2 1-3 1h-226l-3-1-2-1-1-2-1-3v-122l1-3 1-2 2-1z" fill="#edf6fe"/>
<g transform="translate(1110,380)">
<text transform="translate(-41.016,8.616)" fill="#41619f" font-family="Helvetica" font-size="12px"><tspan x="0 6.6719999 12.672 15.336 22.007999 28.007999 34.007999 40.007999 42.672001 49.344002 56.015999 62.015999 68.688004 75.360001" y="0">axi_sysid_v1_0</tspan></text>
</g>
</g>
<g fill="none" stroke="#41619f" stroke-miterlimit="10">
<path d="m3618-87.942h-122"/>
<path d="m3489-94.942v.33c.092 3.78 3.226 6.76 7 6.67"/>
<path d="m3489-94.942v-226"/>
<path d="m3496-327.94h-.333c-3.774.092-6.759 3.226-6.667 7"/>
<path d="m3496-327.94h122"/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<path d="m697 502h146l3 1 2 1 1 2 1 3v102l-1 3-1 2-2 1-3 1h-146l-3-1-2-1-1-2-1-3v-102l1-3 1-2 2-1z" fill="#edf6fe"/>
<g transform="translate(770,500)">
<text transform="translate(-63.03,-2.484)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6.6719999 13.344 16.007999 22.007999 28.68 32.675999 39.348 46.02 52.692001 58.692001 65.363998 68.699997 72.695999 75.360001 82.031998 88.704002 95.375999 99.372002 106.044 112.716 119.388" y="0">pulsar_adc_trigger_gen</tspan></text>
</g>
<g transform="translate(770,620)">
<text transform="translate(-66.354,8.616)" fill="#41619f" font-family="Helvetica" font-size="12px"><tspan x="0 8.0039997 16.667999 20.004 23.34 31.344 39.348 42.683998 46.02 54.023998 65.351997 75.348 78.683998 88.019997 94.692001 101.364 108.036 112.032 118.704 122.04 128.71201" y="0">ADI AXI PWM Generator</tspan></text>
</g>
<path d="m680 521h10v18h-10z" fill="#edf6fe"/>
</g>
<g transform="matrix(0 15 15 0 3329 -625.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#i)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(0 10 18 0 3328 -637.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#h)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAAFhJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiIBI8xEQoBoE5EU/kcx3Dl7IYNL2kw4nwXVFQjwje03AzMLJz3caJ83Dx522PiDIxwHv0KqhSMAhtEbD3HNJ58AAAAASUVORK5CYII="/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(707,530)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001" y="0">s_axi</tspan></text>
</g>
</g>
<path d="m3317-637.94v10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(692,550)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001 23.34 28.9 34.459999 39.459999 41.68" y="0">s_axi_aclk</tspan></text>
</g>
</g>
<path d="m3297-627.94c1.657 0 3-1.343 3-3s-1.343-3-3-3-3 1.343-3 3 1.343 3 3 3" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<path d="m3297-637.94v4" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(692,570)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001 23.34 28.9 34.459999 37.790001 43.349998 48.349998 53.91 56.689999" y="0">s_axi_aresetn</tspan></text>
</g>
</g>
<path d="m3277-637.94v10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(692,590)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5.5599999 10.56 13.34 18.9 23.9 26.120001" y="0">ext_clk</tspan></text>
</g>
</g>
<path d="m3307-457.94v-10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(848,560)">
<text transform="translate(-32.23,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5.5599999 12.78 21.110001 26.67" y="0">pwm_0</tspan></text>
</g>
</g>
<g fill="none" stroke="#41619f" stroke-miterlimit="10">
<path d="m3365-620.94v146"/>
<path d="m3358-467.94h.333c3.774-.092 6.759-3.226 6.667-7"/>
<path d="m3358-467.94h-102"/>
<path d="m3249-474.94v.333c.092 3.774 3.226 6.759 7 6.667"/>
<path d="m3249-474.94v-146"/>
<path d="m3256-627.94h-.333c-3.774.092-6.759 3.226-6.667 7"/>
<path d="m3256-627.94h102"/>
<path d="m3365-620.94v-.333c-.092-3.774-3.226-6.759-7-6.667"/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<path d="m1017 452h186l3 1 2 1 1 2 1 3v122l-1 3-1 2-2 1-3 1h-186l-3-1-2-1-1-2-1-3v-122l1-3 1-2 2-1z" fill="#aac4f7"/>
<g transform="translate(1110,450)">
<text transform="translate(-40.35,-2.484)" fill="#000000" font-family="Helvetica" font-size="12px"><tspan x="0 6 12.672 15.336 22.007999 28.68 35.352001 38.015999 44.015999 50.688 54.683998 61.355999 68.028 74.699997" y="0">spi_pulsar_adc</tspan></text>
</g>
</g>
<g transform="matrix(0 16 16 0 3396 -304.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#g)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAACwAAAAsCAYAAAAehFoBAAAABHNCSVQICAgIfAhkiAAAAXxJREFUWIXtmU1Kw0AUgL8JmvYc4kLpqu0pBP827UHcC6EF8S7ZqD2EGwsieBetOs9FTeo0aZvQTmcC823CGybhY/Lem/woQGgQkWuBuhxUndi7Htn0ACDSipen27VzFCtSoj+4h9kMxE3OiAjH7VPSdGiMlwp3L0YotS+19SjRTCdJHhdyuHvujywAKqJ7dpeHhnBnkKA8K0MB1OF3Hht68adntv/Iit4wjPApF0yUnh8NYfF4D/nzXQh3Bokbk4pkdz8XbtN2JlOF7O5X3umqMn0s7lT9q/HOru9vW1hBELZNELZNELZN7T5c1me3PadOn27cCgdh2zROuHbRbSqQ8PCzRBC2TRC2TRC2zc5fQnfZc8to3ArnwjGxS4/K5MLP6Y1Lj8o0JiWyb9ZR2aCPfOmlb2sAR/GJE5lNKOBtMn8KNITTdIgSXXaOMwT4aC2cCjk8nSReSc9amvc0yeOVv70AepdjRGRvuS0yryMF/ESa14ekMGetsI/8As09Ul5uNt5/AAAAAElFTkSuQmCC"/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<path d="m1210 491h10v18h-10z" fill="#edf6fe"/>
</g>
<g transform="matrix(0 15 15 0 3359 -124.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#f)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(0 10 18 0 3358 -107.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#e)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADRJREFUKJFjdMuZ/P8nEzfDwUlJDAwMDAz2efMYGBgYMPhMDESCgVT4k4l7oKweVThIFQIAk2UKdEPgAjEAAAAASUVORK5CYII="/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1193,500)">
<text transform="translate(-26.67,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 8.3299999 13.89 18.889999 24.450001" y="0">m_spi</tspan></text>
</g>
<path d="m1210 511h10v18h-10z" fill="#edf6fe"/>
</g>
<g transform="matrix(0 15 15 0 3339 -124.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#d)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(0 10 18 0 3338 -107.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#c)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAAHxJREFUKJG9kiEOgDAMRd/IAgjUrsIBdpcJJIeZRHCXXQWNRJCwMAQJgmSkAqj7afv/S1Nl+zEhqEIyBFDEOjGbhuAdwTuqUrOs26nNxGwa4p5QgCha234EIHgHQE6LGcXRYseL8TXHDxn/v6N+bp8ebTegsv94y8oz3tYP5fQtpbkgnLwAAAAASUVORK5CYII="/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1193,520)">
<text transform="translate(-69.46,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 8.3299999 13.89 19.450001 24.450001 26.67 31.67 37.23 42.23 47.790001 56.119999 61.68 63.900002" y="0">m_axis_sample</tspan></text>
</g>
<path d="m1e3 471h10v18h-10z" fill="#edf6fe"/>
</g>
<g transform="matrix(0 15 15 0 3379 -305.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#b)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAABAAAAAQCAYAAAAf8/9hAAAABHNCSVQICAgIfAhkiAAAAIhJREFUOI1jZGBg+M9AAWDBJeHp6ckgKyvLICUlxdDQ0IDTACZcEtu3b2c480KGYdM5iJKEhATSDEAHb9++pcwADg4OwgY0NDQwODg4MISGhmIoZGNjw2oAIwOeWDDya2JgYGBgOLepDqfL4AbAFBMLYIYSHQYEXYANEOMFil0wDAzAG4h0cQEAfasd4MeTUvsAAAAASUVORK5CYII="/>
</g>
<g transform="matrix(0 10 18 0 3378 -317.94)">
<image transform="matrix(1,0,0,-1,0,1)" width="1" height="1" image-rendering="optimizeSpeed" mask="url(#a)" preserveAspectRatio="none" xlink:href="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAoAAAASCAYAAABit09LAAAABHNCSVQICAgIfAhkiAAAADxJREFUKJFjZGBg+M/AwMBgnzePgYGBgeHgpCQGbHwmBiIBI8xEQoBoE+EK7fPmwd2FjT/qRuIUjig3AgACpR/LAVfpiQAAAABJRU5ErkJggg=="/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1027,480)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 16.120001 21.120001" y="0">s_axi</tspan></text>
</g>
</g>
<path d="m3367-317.94v10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1012,500)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 10.56 12.78 18.34 23.34 25.559999" y="0">spi_clk</tspan></text>
</g>
</g>
<path d="m3347-317.94v10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1012,520)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 5 7.2199998" y="0">clk</tspan></text>
</g>
</g>
<path d="m3327-317.94v10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1012,540)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 3.3299999 8.8900003 13.89 19.450001 22.23" y="0">resetn</tspan></text>
</g>
</g>
<path d="m3307-317.94v10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1012,560)">
<text transform="translate(0,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 2.78 6.1100001 8.3299999 13.89 19.450001 25.01" y="0">trigger</tspan></text>
</g>
</g>
<path d="m3327-97.942v-10" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)">
<g transform="translate(1208,540)">
<text transform="translate(-11.11,3.59)" fill="#000000" font-family="Helvetica" font-size="10px"><tspan x="0 2.22 5.5500002" y="0">irq</tspan></text>
</g>
</g>
<g fill="none" stroke-miterlimit="10">
<g stroke="#41619f">
<g>
<path d="m3415-300.94v186"/>
<path d="m3408-107.94h.333c3.774-.09 6.759-3.23 6.667-7"/>
<path d="m3408-107.94h-122"/>
<path d="m3279-114.94v.33c.092 3.78 3.226 6.76 7 6.67"/>
<path d="m3279-114.94v-186"/>
<path d="m3286-307.94h-.333c-3.774.09-6.759 3.23-6.667 7"/>
<path d="m3286-307.94h122"/>
<path d="m3415-300.94v-.33c-.092-3.78-3.226-6.76-7-6.67"/>
</g>
<g stroke-width="4">
<path d="m3797-1007.9v-30h-480v320h130v1930h-750v-100"/>
<path d="m3677-747.94v370h-290v60"/>
<path d="m3657-747.94v740h-350v30"/>
<path d="m3637-747.94v320h-700v130"/>
<path d="m3617-747.94v40h-280v70"/>
</g>
</g>
<g stroke="#102235">
<path d="m3377-997.94v-30h-70v350h90v260h-140v360h300v-20" stroke-width="3"/>
<path d="m3067-1467.9v20h370v390h-140v370h120v280h-170v380h130v1170h-140v-30" stroke-width="3"/>
<path d="m3277-637.94v-20h130v220h-220v390h-280v-70"/>
<path d="m3367-437.94v120"/>
</g>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<path d="m878 498h5v5h-5z" fill="#102235"/>
</g>
<g fill="none" stroke-miterlimit="10">
<path d="m3327-97.942v50h250v440" stroke="#102235"/>
<path d="m3347-97.942v60h-60v60" stroke="#41619f" stroke-width="4"/>
<path d="m3367-97.942v1710" stroke="#41619f" stroke-width="4"/>
<g stroke="#102235">
<path d="m3047-1467.9v2090h270v510h-220v-20"/>
<path d="m3777-1007.9v-40h-490v350h150v300"/>
<path d="m3347-397.94v80"/>
<path d="m3237-397.94v390"/>
<path d="m3317-697.94v60"/>
<path d="m3577-337.94v-60h-680v100"/>
</g>
</g>
<g transform="rotate(90 2592.5 1274.5)" fill="#102235">
<path d="m918 428h5v5h-5z"/>
<path d="m918 518h5v5h-5z"/>
<path d="m918 628h5v5h-5z"/>
</g>
<g fill="none" stroke="#102235" stroke-miterlimit="10" stroke-width="3">
<path d="m3757-1007.9v-60h-480v400h150v280"/>
<path d="m3327-387.94v70"/>
<path d="m3227-387.94v370"/>
<path d="m3297-667.94v30"/>
</g>
<g transform="rotate(90 2592.5 1274.5)">
<path d="m647 567h7v7h-7z" fill="#102235"/>
</g>
<path d="m3557-337.94v-50h-680v90" fill="none" stroke="#102235" stroke-miterlimit="10" stroke-width="3"/>
<g transform="rotate(90 2592.5 1274.5)" fill="#102235">
<path d="m927 437h7v7h-7z"/>
<path d="m927 537h7v7h-7z"/>
<path d="m927 637h7v7h-7z"/>
</g>
<g fill="none" stroke-miterlimit="10">
<path d="m3357-1407.9v-20h-880v2590h160v-50" stroke="#102235"/>
<path d="m3306-456.94v140" stroke="#fa6e03" stroke-width="2"/>
<path d="m3307-457.94v140" stroke="#fd9749" stroke-width="2"/>
<path d="m3307-457.94v140" stroke="#fd862b"/>
</g>
</g>
</svg>
Side by Side

After

Width:  |  Height:  |  Size: 18 KiB

51
docs/library/template_framework/index.rst Normal file
View File

@ -0,0 +1,51 @@
:orphan:
.. _template_framework:
Framework Template
================================================================================
.. toctree::
:hidden:
Template Module<template_module>
Template Interface<interface>
Instruction Set Template<instruction-set>
{brief introdution}.
Sub-modules
--------------------------------------------------------------------------------
* :ref:`template_framework module`: {brief description}.
Interfaces
--------------------------------------------------------------------------------
* :ref:`template_framework interface`: {brief description}.
Software
--------------------------------------------------------------------------------
* :ref:`template_framework instruction-set`: {brief description}.
Related IP Cores
--------------------------------------------------------------------------------
This list contains cores that are not part of the core {ip name} but
make use of its interfaces and are intend to be used together with the {ip name}.
* :dokuwiki:`util-sigma-delta-spi:resources/fpga/peripherals/util_sigma_delta_spi`:
Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family.
Examples
--------------------------------------------------------------------------------
* :dokuwiki:`CN0363:resources/eval/user-guides/eval-cn0363-pmdz`:
Colorimeter application using the :part:`AD7175-2` Sigma-Delta ADC.
Additional Resources
--------------------------------------------------------------------------------
* :download:`Presentation: SPI Engine Design Philosophy <https://wiki.analog.com/_media/resources/fpga/peripherals/spi-engine3.pdf>`.
* :ref:`spi_engine tutorial`.

125
docs/library/template_framework/instruction-set.rst Normal file
View File

@ -0,0 +1,125 @@
.. _template_framework instruction-set:
Template Instruction Set Specification
================================================================================
The {instruction set} set is a {brief description}
Instructions
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Transfer Instruction
--------------------------------------------------------------------------------
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 0 0 0 0 r w n n n n n n n n
== == == == == == = = = = = = = = = =
{description}
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - r
- Read
- If set to 1 data will be read {...}.
* - w
- Write
- If set to 1 data will be taken from {...}.
* - n
- Length
- n + 1 number of words that {...}.
Other Instruction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 0 1 0 0 t t s s s s s s s s
== == == == == == = = = = = = = = = =
The {instruction name} instruction updates the {...}.
.. math::
delay = t * \frac{div + 1}{f_{clk}}
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - t
- Delay
- Delay before and after setting the new configuration.
* - s
- Chip-select
- The new chip-select configuration.
Yet Another Instruction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
== == == == == == = = = = = = = = = =
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
== == == == == == = = = = = = = = = =
0 0 1 0 0 0 r r v v v v v v v v
== == == == == == = = = = = = = = = =
The {instruction name} instruction updates the {...}.
The configuration writes instruction updates a
:ref:`template_framework configuration-registers`
of the {module name} module with a new value.
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - r
- Register
- Configuration register address.
2'b00 = :ref:`template_framework register`
* - v
- Value
- New value for the configuration register.
.. _template_framework configuration-registers:
Configuration Registers
--------------------------------------------------------------------------------
The {module name} module has a set of {#}-bit configuration registers which
can be used to dynamically modify the behavior of the module at runtime.
.. _template_framework register:
Template Register
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The {registe name} register configures {description}.
.. list-table::
:widths: 10 15 75
:header-rows: 1
* - Bits
- Name
- Description
* - [7:3]
- reserved
- Must always be 0.
* - [2]
- three_wire
- Configures {...}.

47
docs/library/template_framework/interface.rst Normal file
View File

@ -0,0 +1,47 @@
.. _template_framework interface:
Template Interface
================================================================================
The {interface name} is used to {brief description}.
The interface consists of {#} streams:
* The {stream name} stream which carries the {...}.
{brief description, handshaking info}
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml`
- Interface definition file
Signal Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 10 10 70
:header-rows: 1
* - Width
- Name
- Direction (Master)
- Description
* -
- ``cmd_ready``
- Input
- Ready signal of the CMD stream
* -
- ``cmd_valid``
- Output
- Valid signal of the CMD stream
* - [15:0]
- ``cmd_data``
- Output
- Data signal of the CMD stream

59
docs/library/template_framework/template_module.rst Normal file
View File

@ -0,0 +1,59 @@
.. _template_framework module:
Template Module
================================================================================
.. symbolator:: ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.v
:caption: spi_engine_execution
The {module name} is responsible for {brief description}.
Files
-------------------------------------------------------------------------------
.. list-table::
:widths: 25 75
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/spi_engine/spi_engine_execution/spi_engine_execution.v`
- Verilog source for the peripheral.
* - :git-hdl:`master:library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl`
- TCL script to generate the Vivado IP-integrator project for the peripheral.
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
:path: library/spi_engine/spi_engine_interconnect
* - DATA_WIDTH
- Data width of the parallel SDI/SDO data interfaces.
Signal and Interface Pins
--------------------------------------------------------------------------------
.. list-table::
:widths: 10 25 65
:header-rows: 1
* - Name
- Type
- Description
* - ``clk``
- Clock
- All other signals are synchronous to this clock.
* - ``resetn``
- Synchronous active-low reset
- Resets the internal state machine of the core.
* - ``ctrl``
- :ref:`template_framework interface` master
- {brief description}.
Theory of Operation
--------------------------------------------------------------------------------
The {module name} module implements {brief description}.
.. image:: ../spi_engine/spi_engine.svg

152
docs/library/template_ip/index.rst Normal file
View File

@ -0,0 +1,152 @@
:orphan:
.. _template_ip:
IP Template
================================================================================
Features
--------------------------------------------------------------------------------
* AXI-based configuration
* Vivado and Quartus Compatible
Files
--------------------------------------------------------------------------------
.. list-table::
:header-rows: 1
* - Name
- Description
* - :git-hdl:`master:library/axi_dmac/axi_dmac.v`
- Verilog source for the peripheral.
Block Diagram
--------------------------------------------------------------------------------
.. image:: ../axi_dmac/block_diagram.svg
:alt: Template IP block diagram
:align: center
Configuration Parameters
--------------------------------------------------------------------------------
.. hdl-parameters::
:path: library/spi_engine/spi_engine_interconnect
* - DATA_WIDTH
- Data width of the parallel SDI/SDO data interfaces.
.. _template_ip interface:
Interface
--------------------------------------------------------------------------------
.. list-table:: Clock and reset
:header-rows: 1
* - Name
- Type
- Description
* - ``clk``
- input
- All signals are synchronous to this clock.
* - ``resetn``
- input
- Synchronous active low resey.
.. list-table:: DMA_TX interface
:header-rows: 1
* - Name
- Type
- Description
* - ``dac_enable_*``
- output
- If set, the channel is enabled (one for each channel).
* - ``dac_valid``
- output
- Indicates valid data request for all channels
.. list-table:: AXI_S_MM interface
:header-rows: 1
* - Name
- Type
- Description
* - ``s_axi_*``
-
- Standard AXI Slave Memory Map interface .
Detailed Architecture
--------------------------------------------------------------------------------
::
.. image:: detailed_architecture.svg
:alt: Template IP detailed architecture
:align: center
Detailed Description
--------------------------------------------------------------------------------
The top module instantiates
* The ADC channel register map.
* The ADC common register map.
* The AXI handling interface.
The data from the interface module is processed by the ADC channel module.
The Up_adc_common module implements the ADC COMMON register map, allowing for
basic monitoring and control of the ADC.
The Up_adc_channel module implements the ADC CHANNEL register map, allowing for
basic monitoring and control of the ADC's channel.
Register Map
--------------------------------------------------------------------------------
.. csv-table:: Base (common to all cores)
:file: ../common/regmap_base.csv
:class: regmap
:header-rows: 2
.. csv-table:: ADC Common (axi_ad*)
:file: ../common/regmap_adc_common.csv
:class: regmap
:header-rows: 2
.. csv-table:: ADC Channel (axi_ad*)
:file: ../common/regmap_adc_channel.csv
:class: regmap
:header-rows: 2
Design Guidelines
--------------------------------------------------------------------------------
The control of the chip is done through an SPI interface, which is needed at the
system level.
The :ref:`template_ip interface` must be connected directly to the top file of
the design, as IO primitives are part of the IP.
The example design uses a DMA to move the data from the output of the IP to memory.
If the data needs to be processed in HDL before moving to the memory, it can be
done at the output of the IP (at the system level) or inside the ADC interface
module (at the IP level).
The example design uses a processor to program all the registers.
If no processor is available in your system, you can create your IP starting
from the interface module.
Software Guidelines
--------------------------------------------------------------------------------
Linux is supported also using :git-linux:`/`.
References
--------------------------------------------------------------------------------
* :git-hdl:`/`, :git-hdl:`library/axi_ad777x` library.
* :git-linux:`/`.
* :xilinx:`Zynq-7000 SoC Overview:support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf`.
* :xilinx:`Zynq-7000 SoC Packaging and Pinout:support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf`.

35
docs/make.bat Executable file
View File

@ -0,0 +1,35 @@
@ECHO OFF
pushd %~dp0
REM Command file for Sphinx documentation
if "%SPHINXBUILD%" == "" (
set SPHINXBUILD=sphinx-build
)
set SOURCEDIR=.
set BUILDDIR=_build
if "%1" == "" goto help
%SPHINXBUILD% >NUL 2>NUL
if errorlevel 9009 (
echo.
echo.The 'sphinx-build' command was not found. Make sure you have Sphinx
echo.installed, then set the SPHINXBUILD environment variable to point
echo.to the full path of the 'sphinx-build' executable. Alternatively you
echo.may add the Sphinx directory to PATH.
echo.
echo.If you don't have Sphinx installed, grab it from
echo.http://sphinx-doc.org/
exit /b 1
)
%SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
goto end
:help
%SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O%
:end
popd

9
docs/requirements.txt Normal file
View File

@ -0,0 +1,9 @@
sphinx
wavedrom
sphinxcontrib-wavedrom
sphinxcontrib-mermaid
sphinxcontrib-bibtex
sphinxcontrib-svg2pdfconverter
furo
https://github.com/hdl/pyhdlparser/tarball/master
https://github.com/hdl/symbolator/tarball/master

0
docs/HDL_logo.png → docs/sources/HDL_logo.png
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 64 KiB

After

Width:  |  Height:  |  Size: 64 KiB

0
docs/HDL_logo.svg → docs/sources/HDL_logo.svg
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 52 KiB

After

Width:  |  Height:  |  Size: 52 KiB

0
docs/HDL_logo_w.png → docs/sources/HDL_logo_w.png
View File

Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 71 KiB

After

Width:  |  Height:  |  Size: 71 KiB

61
docs/sources/custom.css Executable file
View File

@ -0,0 +1,61 @@
.sidebar-brand {
background-color: #f8f9fb;
border-radius: .25em;
margin: var(--sidebar-item-spacing-vertical)
calc(var(--sidebar-item-spacing-horizontal)/2)
0
calc(var(--sidebar-item-spacing-horizontal)/2);
padding: 0;
}
.sidebar-brand::before {
content: "";
display: inline-block;
width: 100%;
height: 4rem;
background-image: url(HDL_logo.svg);
background-size: auto 4rem;
background-position: center;
background-repeat: no-repeat;
}
.sidebar-brand-text {
display: none;
}
body[data-theme="dark"] .sidebar-brand {
color: #fff;
}
@media (min-width: 56em){
.content {
width: 52em;
}
}
figure > object {
max-width: 100%;
}
img {
background: #fff;
border-radius: .25em;
padding: .5em 0;
}
iframe {
width: calc(50.625rem - 1rem);
height: calc(28.47rem - 0.5625rem);
margin-left: -1rem;
}
@media (max-width:50.625rem) {
iframe {
width: calc(100vw - 1rem);
height: calc(56.25vw - 1rem);
margin-left: -1rem;
}
}
.WaveDrom {
background: #fff;
border-radius: .25em;
padding: .5em 0;
}
table.regmap {
font-size: .75em;
}
table.regmap .caption-text{
font-size: 1rem;
}

313
docs/sources/icon.svg Executable file
View File

@ -0,0 +1,313 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
width="32"
height="32"
viewBox="0 0 32 32"
version="1.1"
id="svg5"
xml:space="preserve"
sodipodi:docname="icon.svg"
inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns="http://www.w3.org/2000/svg"
xmlns:svg="http://www.w3.org/2000/svg"><sodipodi:namedview
id="namedview7"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:showpageshadow="2"
inkscape:pageopacity="0.0"
inkscape:pagecheckerboard="0"
inkscape:deskcolor="#d1d1d1"
inkscape:document-units="px"
showgrid="true"
inkscape:zoom="6.8203125"
inkscape:cx="-31.670103"
inkscape:cy="16.788087"
inkscape:window-width="2560"
inkscape:window-height="1014"
inkscape:window-x="0"
inkscape:window-y="0"
inkscape:window-maximized="1"
inkscape:current-layer="layer1"
inkscape:pageshadow="2"><inkscape:grid
type="xygrid"
id="grid8087" /></sodipodi:namedview><defs
id="defs2" /><g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"><g
id="g1080"
transform="matrix(0.5079365,0,0,0.5079365,43.292289,12.009306)"><g
id="g1143-2-8"
transform="matrix(0.76131478,0,0,0.76131478,-297.44221,103.91797)"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"><rect
y="-162.30205"
x="295.42365"
height="41.057423"
width="41.057423"
id="rect944-2-8"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-3-7"
d="m 298.6707,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-0-9-1"
d="m 304.40773,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-04-6-0"
d="m 310.14475,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-8-5-1"
d="m 315.88178,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-2-7-0"
d="m 321.61879,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-20-4-7"
d="m 327.35582,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-24-3-9"
d="m 333.09288,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-9-0"
d="m 340.88127,-159.11929 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-4-7"
d="m 340.88127,-153.41595 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-4-4-6"
d="m 340.88127,-147.71262 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-0-0-9"
d="m 340.88127,-142.00928 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-84-6-3"
d="m 340.88127,-136.30594 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-2-0-3"
d="m 340.88127,-130.60263 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-5-22-6"
d="m 340.88127,-124.89928 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-2-8-4"
d="m 291.12955,-159.18692 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-7-4-9"
d="m 291.12955,-153.48358 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-4-5-3-8"
d="m 291.12955,-147.78025 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-0-7-1-4"
d="m 291.12955,-142.07691 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-84-5-1-6"
d="m 291.12955,-136.37357 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-2-2-1-9"
d="m 291.12955,-130.67026 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-5-2-9-9"
d="m 291.12955,-124.96691 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-86-0-7"
d="m 298.74924,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-0-6-0-8"
d="m 304.48627,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-04-0-0-0"
d="m 310.22329,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-8-0-2-1"
d="m 315.96032,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-2-9-5-4"
d="m 321.69733,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-20-1-7-3"
d="m 327.43436,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-24-2-6-5"
d="m 333.17142,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#ffffff;stroke-width:3.97158;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /></g><path
sodipodi:type="star"
style="fill:#ff8d34;fill-opacity:1;stroke:none;stroke-width:0.720357;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1"
id="path888-7"
sodipodi:sides="3"
sodipodi:cx="-50.695606"
sodipodi:cy="144.73032"
sodipodi:r1="9.623745"
sodipodi:r2="4.811872"
sodipodi:arg1="2.0971887"
sodipodi:arg2="3.1443862"
inkscape:flatsided="false"
inkscape:rounded="0"
inkscape:randomized="0"
inkscape:transform-center-x="-9.049263"
inkscape:transform-center-y="-0.05080837"
d="m -55.530743,153.05125 0.02328,-8.33438 0.02328,-8.33437 7.206139,4.18735 7.206139,4.18735 -7.229422,4.14702 z"
transform="matrix(3.7795276,0,0,3.7795276,128.82448,-539.10474)" /><g
id="g1143-2"
transform="matrix(0.76131478,0,0,0.76131478,-297.44221,103.91797)"
style="fill:#646464;fill-opacity:1"><rect
y="-162.30205"
x="295.42365"
height="41.057423"
width="41.057423"
id="rect944-2"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.89496;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-3"
d="m 298.6707,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-0-9"
d="m 304.40773,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-04-6"
d="m 310.14475,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-8-5"
d="m 315.88178,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-2-7"
d="m 321.61879,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-20-4"
d="m 327.35582,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-24-3"
d="m 333.09288,-166.72734 c 0,4.58547 0,4.39441 0,4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-9"
d="m 340.88127,-159.11929 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-4"
d="m 340.88127,-153.41595 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-4-4"
d="m 340.88127,-147.71262 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-0-0"
d="m 340.88127,-142.00928 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-84-6"
d="m 340.88127,-136.30594 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-2-0"
d="m 340.88127,-130.60263 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-5-22"
d="m 340.88127,-124.89928 c -4.58547,0 -4.39441,0 -4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-2-8"
d="m 291.12955,-159.18692 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-7-4"
d="m 291.12955,-153.48358 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-4-5-3"
d="m 291.12955,-147.78025 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-0-7-1"
d="m 291.12955,-142.07691 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-84-5-1"
d="m 291.12955,-136.37357 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-8-2-2-1"
d="m 291.12955,-130.67026 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-5-5-2-9"
d="m 291.12955,-124.96691 c 4.58547,0 4.39441,0 4.39441,0"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-86-0"
d="m 298.74924,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-0-6-0"
d="m 304.48627,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-04-0-0"
d="m 310.22329,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-8-0-2"
d="m 315.96032,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-2-9-5"
d="m 321.69733,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-20-1-7"
d="m 327.43436,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /><path
inkscape:connector-curvature="0"
id="path946-24-2-6"
d="m 333.17142,-116.79528 c 0,-4.58547 0,-4.39441 0,-4.39441"
style="fill:#646464;fill-opacity:1;stroke:#000000;stroke-width:1.60492;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /></g><text
xml:space="preserve"
style="font-style:normal;font-weight:normal;font-size:9.14888px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#ffffff;fill-opacity:1;stroke:none;stroke-width:0.228722"
x="-67.670258"
y="-2.1524136"
id="text1626-8-9"><tspan
sodipodi:role="line"
id="tspan1624-6-1"
x="-67.670258"
y="-2.1524136"
style="font-style:normal;font-variant:normal;font-weight:500;font-stretch:normal;font-size:9.14888px;font-family:AzbukaW01-Medium;-inkscape-font-specification:'AzbukaW01-Medium, Medium';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:-0.196133px;writing-mode:lr-tb;text-anchor:start;fill:#ffffff;fill-opacity:1;stroke-width:0.228722">FPGA</tspan></text></g></g></svg>
Side by Side

After

Width:  |  Height:  |  Size: 23 KiB