diff --git a/projects/fmcomms2/c5soc/system_bd.qsys b/projects/fmcomms2/c5soc/system_bd.qsys
index 524ecf219..349ec1a88 100644
--- a/projects/fmcomms2/c5soc/system_bd.qsys
+++ b/projects/fmcomms2/c5soc/system_bd.qsys
@@ -73,6 +73,22 @@
          type = "String";
       }
    }
+   element gpio
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element gpio.s1
+   {
+      datum baseAddress
+      {
+         value = "65680";
+         type = "String";
+      }
+   }
    element spi_ad9361
    {
       datum _sortIndex
@@ -265,11 +281,7 @@
  <interface name="axi_ad9361_0_rx_if" internal="axi_ad9361.rx_if" />
  <interface name="axi_ad9361_0_tx_clock" internal="axi_ad9361.tx_clock" />
  <interface name="axi_ad9361_0_tx_if" internal="axi_ad9361.tx_if" />
- <interface
-   name="axi_ad9361_debug_if"
-   internal="axi_ad9361.debug_if"
-   type="conduit"
-   dir="end" />
+ <interface name="axi_ad9361_debug_if" internal="axi_ad9361.debug_if" />
  <interface
    name="axi_ad9361_device_clock"
    internal="axi_ad9361.device_clock"
@@ -359,6 +371,11 @@
    type="conduit"
    dir="end" />
  <interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="gpio_external_connection"
+   internal="gpio.external_connection"
+   type="conduit"
+   dir="end" />
  <interface name="hps_0_f2h_cold_reset_req" internal="sys_hps.f2h_cold_reset_req" />
  <interface
    name="hps_0_f2h_debug_reset_req"
@@ -442,6 +459,7 @@
   <parameter name="C_DMA_LENGTH_WIDTH" value="24" />
   <parameter name="C_DMA_TYPE_DEST" value="0" />
   <parameter name="C_DMA_TYPE_SRC" value="2" />
+  <parameter name="C_FIFO_SIZE" value="4" />
   <parameter name="C_SYNC_TRANSFER_START" value="1" />
   <parameter name="PCORE_ID" value="0" />
  </module>
@@ -458,9 +476,24 @@
   <parameter name="C_DMA_LENGTH_WIDTH" value="24" />
   <parameter name="C_DMA_TYPE_DEST" value="2" />
   <parameter name="C_DMA_TYPE_SRC" value="0" />
+  <parameter name="C_FIFO_SIZE" value="4" />
   <parameter name="C_SYNC_TRANSFER_START" value="0" />
   <parameter name="PCORE_ID" value="0" />
  </module>
+ <module name="gpio" kind="altera_avalon_pio" version="15.0" enabled="1">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="5" />
+ </module>
  <module name="spi_ad9361" kind="altera_avalon_spi" version="15.0" enabled="1">
   <parameter name="avalonSpec" value="2.0" />
   <parameter name="clockPhase" value="0" />
@@ -1379,6 +1412,15 @@
   <parameter name="baseAddress" value="0x00010080" />
   <parameter name="defaultConnection" value="false" />
  </connection>
+ <connection
+   kind="avalon"
+   version="15.0"
+   start="sys_hps.h2f_lw_axi_master"
+   end="gpio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010090" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
  <connection
    kind="avalon"
    version="15.0"
@@ -1441,6 +1483,7 @@
  <connection kind="clock" version="15.0" start="sys_clk.clk" end="sys_id.clk" />
  <connection kind="clock" version="15.0" start="sys_clk.clk" end="sys_gpio.clk" />
  <connection kind="clock" version="15.0" start="sys_clk.clk" end="spi_ad9361.clk" />
+ <connection kind="clock" version="15.0" start="sys_clk.clk" end="gpio.clk" />
  <connection
    kind="clock"
    version="15.0"
@@ -1587,6 +1630,11 @@
    version="15.0"
    start="sys_clk.clk_reset"
    end="axi_dmac_dac.m_src_axi_reset" />
+ <connection
+   kind="reset"
+   version="15.0"
+   start="sys_clk.clk_reset"
+   end="gpio.reset" />
  <connection
    kind="reset"
    version="15.0"
diff --git a/projects/fmcomms2/c5soc/system_project.tcl b/projects/fmcomms2/c5soc/system_project.tcl
index 0621a111d..ccfa80843 100755
--- a/projects/fmcomms2/c5soc/system_project.tcl
+++ b/projects/fmcomms2/c5soc/system_project.tcl
@@ -67,12 +67,21 @@ set_location_assignment PIN_E4  -to tx_data_out[5]
 set_location_assignment PIN_D4  -to "tx_data_out[5](n)"
 
 set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_resetb
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_en_agc
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_sync
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_enable
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ad9361_txnrx
+
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_mosi
 set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_miso
 
 set_location_assignment PIN_C4  -to ad9361_resetb
+set_location_assignment PIN_C5  -to ad9361_en_agc
+set_location_assignment PIN_D5  -to ad9361_sync
+set_location_assignment PIN_B11 -to ad9361_enable
+set_location_assignment PIN_C12 -to ad9361_txnrx
 set_location_assignment PIN_A8  -to spi_csn
 set_location_assignment PIN_H12 -to spi_clk
 set_location_assignment PIN_H13 -to spi_mosi
diff --git a/projects/fmcomms2/c5soc/system_top.v b/projects/fmcomms2/c5soc/system_top.v
index b353b90c4..31fc90e26 100644
--- a/projects/fmcomms2/c5soc/system_top.v
+++ b/projects/fmcomms2/c5soc/system_top.v
@@ -135,6 +135,10 @@ module system_top (
   // gpio interface
 
   ad9361_resetb,
+  ad9361_en_agc,
+  ad9361_sync,
+  ad9361_enable,
+  ad9361_txnrx,
 
   // spi
 
@@ -239,6 +243,10 @@ module system_top (
   // gpio interface
 
   output            ad9361_resetb;
+  output            ad9361_en_agc;
+  output            ad9361_sync;
+  output            ad9361_enable;
+  output            ad9361_txnrx;
 
   // spi interface
 
@@ -301,8 +309,6 @@ module system_top (
   assign vga_vs = vid_v_sync;
   assign {vga_b,vga_g,vga_r} =  {vid_b,vid_g,vid_r};
 
-  assign ad9361_resetb = 1'b1;
-
   // instantiations
 
   sld_signaltap #(
@@ -504,7 +510,8 @@ module system_top (
 		.util_dac_unpack_channels_data_dac_data_03 (dac_data_q1),
 		.util_dac_unpack_channels_data_fifo_valid (dac_fifo_valid),
 		.util_dac_unpack_channels_data_dma_rd (dac_rd_en),
-		.util_dac_unpack_channels_data_dma_data (dac_ddata)
+		.util_dac_unpack_channels_data_dma_data (dac_ddata),
+    .gpio_external_connection_export ({ad9361_resetb, ad9361_en_agc, ad9361_sync, ad9361_enable, ad9361_txnrx})
 	);
 
 endmodule