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wfifo: added axi stream support

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Rejeesh Kutty 2014-10-15 14:43:17 -04:00
parent 0aed11fa6c
commit f0b25c39a3
2 changed files with 22 additions and 3 deletions
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24
library/util_wfifo/util_wfifo.v
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@ -50,6 +50,7 @@ module util_wfifo (
s_clk,
s_wr,
s_wdata,
s_wready,
s_wovf,
fifo_rst,
@ -65,6 +66,7 @@ module util_wfifo (
parameter M_DATA_WIDTH = 32;
parameter S_DATA_WIDTH = 64;
parameter S_READY_ENABLE = 0;
// common clock
@ -79,6 +81,7 @@ module util_wfifo (
input s_clk;
output s_wr;
output [S_DATA_WIDTH-1:0] s_wdata;
input s_wready;
input s_wovf;
// fifo interface
@ -97,11 +100,13 @@ module util_wfifo (
reg m_wovf_m1 = 'd0;
reg m_wovf_m2 = 'd0;
reg m_wovf = 'd0;
reg s_wr = 'd0;
reg s_wr_int = 'd0;
// internal signals
wire m_wovf_s;
wire [S_DATA_WIDTH-1:0] s_wdata_s;
wire s_wready_s;
// defaults
@ -130,16 +135,29 @@ module util_wfifo (
assign fifo_rd = ~fifo_rempty;
always @(posedge s_clk) begin
s_wr <= fifo_rd;
s_wr_int <= fifo_rd;
end
genvar s;
generate
for (s = 0; s < S_DATA_WIDTH; s = s + 1) begin: g_rdata
assign s_wdata[s] = fifo_rdata[(S_DATA_WIDTH-1)-s];
assign s_wdata_s[s] = fifo_rdata[(S_DATA_WIDTH-1)-s];
end
endgenerate
assign s_wready_s = (S_READY_ENABLE == 0) ? 1'b1 : s_wready;
ad_axis_inf_rx #(.DATA_WIDTH(S_DATA_WIDTH)) i_axis_inf (
.clk (s_clk),
.rst (fifo_rst),
.valid (s_wr_int),
.last (1'd0),
.data (s_wdata_s),
.inf_valid (s_wr),
.inf_last (),
.inf_data (s_wdata),
.inf_ready (s_wready_s));
endmodule
// ***************************************************************************

1
library/util_wfifo/util_wfifo_ip.tcl
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@ -5,6 +5,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_wfifo
adi_ip_files util_wfifo [list \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"util_wfifo.v" ]
adi_ip_properties_lite util_wfifo