From f0da125a4e7f9eef30e8b067561631d9689a6f6b Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 20 Apr 2017 18:43:37 +0300 Subject: [PATCH] ad_mmcm_drp: Fix generate block Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate. --- library/xilinx/common/ad_mmcm_drp.v | 265 ++++++++++++++-------------- 1 file changed, 136 insertions(+), 129 deletions(-) diff --git a/library/xilinx/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v index 1fb25fa3f..8cd8cef97 100644 --- a/library/xilinx/common/ad_mmcm_drp.v +++ b/library/xilinx/common/ad_mmcm_drp.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -112,134 +112,141 @@ module ad_mmcm_drp #( // instantiations generate - if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin - MMCM_ADV #( - .BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .CLOCK_HOLD ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (MMCM_VCO_DIV), - .CLKFBOUT_MULT_F (MMCM_VCO_MUL), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), - .CLKOUT0_PHASE (MMCM_CLK0_PHASE), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), - .CLKOUT1_PHASE (MMCM_CLK1_PHASE), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), - .CLKOUT2_PHASE (MMCM_CLK2_PHASE), - .CLKOUT2_DUTY_CYCLE (0.500), - .CLKOUT2_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), - .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), - .REF_JITTER1 (0.010)) - i_mmcm ( - .CLKIN1 (clk), - .CLKFBIN (bufg_fb_clk_s), - .CLKFBOUT (mmcm_fb_clk_s), - .CLKOUT0 (mmcm_clk_0_s), - .CLKOUT1 (mmcm_clk_1_s), - .CLKOUT2 (mmcm_clk_2_s), - .LOCKED (mmcm_locked_s), - .DCLK (up_clk), - .DEN (up_drp_sel), - .DADDR (up_drp_addr[6:0]), - .DWE (up_drp_wr), - .DI (up_drp_wdata), - .DO (up_drp_rdata_s), - .DRDY (up_drp_ready_s), - .CLKFBOUTB (), - .CLKOUT0B (), - .CLKOUT1B (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - .CLKIN2 (clk2), - .CLKINSEL (clk_sel), - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_rst)); - end - if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin - MMCME2_ADV #( - .BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (MMCM_VCO_DIV), - .CLKFBOUT_MULT_F (MMCM_VCO_MUL), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), - .CLKOUT0_PHASE (MMCM_CLK0_PHASE), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), - .CLKOUT1_PHASE (MMCM_CLK1_PHASE), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT1_USE_FINE_PS ("FALSE"), - .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), - .CLKOUT2_PHASE (MMCM_CLK2_PHASE), - .CLKOUT2_DUTY_CYCLE (0.500), - .CLKOUT2_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), - .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), - .REF_JITTER1 (0.010)) - i_mmcm ( - .CLKIN1 (clk), - .CLKFBIN (bufg_fb_clk_s), - .CLKFBOUT (mmcm_fb_clk_s), - .CLKOUT0 (mmcm_clk_0_s), - .CLKOUT1 (mmcm_clk_1_s), - .CLKOUT2 (mmcm_clk_2_s), - .LOCKED (mmcm_locked_s), - .DCLK (up_clk), - .DEN (up_drp_sel), - .DADDR (up_drp_addr[6:0]), - .DWE (up_drp_wr), - .DI (up_drp_wdata), - .DO (up_drp_rdata_s), - .DRDY (up_drp_ready_s), - .CLKFBOUTB (), - .CLKOUT0B (), - .CLKOUT1B (), - .CLKOUT2B (), - .CLKOUT3 (), - .CLKOUT3B (), - .CLKOUT4 (), - .CLKOUT5 (), - .CLKOUT6 (), - .CLKIN2 (clk2), - .CLKINSEL (clk_sel), - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (), - .CLKINSTOPPED (), - .CLKFBSTOPPED (), - .PWRDWN (1'b0), - .RST (mmcm_rst)); + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), + .REF_JITTER1 (0.010)) + i_mmcm ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); + BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); + BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); + BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); + + end else begin /* MMCM_DEVICE_TYPE == 1 */ + + MMCM_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .CLOCK_HOLD ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), + .REF_JITTER1 (0.010)) + i_mmcm ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); + BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); + BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); + BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); + end endgenerate - BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); - BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); - BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); - BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); endmodule