ad_mmcm_drp: Fix generate block
Can not be multiple 'if' statements inside a generate block. If there are multiple cases use if/esle statement, but always should be one single if/else inside a generate.main
Istvan Csomortani
parent
806947444f
commit
f0da125a4e
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@ -112,68 +112,6 @@ module ad_mmcm_drp #(
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// instantiations
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// instantiations
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generate
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generate
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if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin
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MMCM_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.CLOCK_HOLD ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (MMCM_VCO_DIV),
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.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
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.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT2_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
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.REF_JITTER1 (0.010))
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i_mmcm (
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.CLKIN1 (clk),
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.CLKFBIN (bufg_fb_clk_s),
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.CLKFBOUT (mmcm_fb_clk_s),
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.CLKOUT0 (mmcm_clk_0_s),
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.CLKOUT1 (mmcm_clk_1_s),
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.CLKOUT2 (mmcm_clk_2_s),
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.LOCKED (mmcm_locked_s),
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.DCLK (up_clk),
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.DEN (up_drp_sel),
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.DADDR (up_drp_addr[6:0]),
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.DWE (up_drp_wr),
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.DI (up_drp_wdata),
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.DO (up_drp_rdata_s),
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.DRDY (up_drp_ready_s),
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.CLKFBOUTB (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN2 (clk2),
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.CLKINSEL (clk_sel),
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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end
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if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
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if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
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MMCME2_ADV #(
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MMCME2_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.BANDWIDTH ("OPTIMIZED"),
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@ -233,14 +171,83 @@ module ad_mmcm_drp #(
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.CLKFBSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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.RST (mmcm_rst));
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end
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endgenerate
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BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
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BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
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BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
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BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
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BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
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BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
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BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
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BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
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end else begin /* MMCM_DEVICE_TYPE == 1 */
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MMCM_ADV #(
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.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.CLOCK_HOLD ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (MMCM_VCO_DIV),
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.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
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.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
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.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
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.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
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.CLKOUT2_DUTY_CYCLE (0.500),
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.CLKOUT2_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
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.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
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.REF_JITTER1 (0.010))
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i_mmcm (
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.CLKIN1 (clk),
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.CLKFBIN (bufg_fb_clk_s),
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.CLKFBOUT (mmcm_fb_clk_s),
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.CLKOUT0 (mmcm_clk_0_s),
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.CLKOUT1 (mmcm_clk_1_s),
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.CLKOUT2 (mmcm_clk_2_s),
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.LOCKED (mmcm_locked_s),
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.DCLK (up_clk),
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.DEN (up_drp_sel),
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.DADDR (up_drp_addr[6:0]),
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.DWE (up_drp_wr),
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.DI (up_drp_wdata),
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.DO (up_drp_rdata_s),
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.DRDY (up_drp_ready_s),
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.CLKFBOUTB (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN2 (clk2),
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.CLKINSEL (clk_sel),
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (),
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.CLKINSTOPPED (),
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.CLKFBSTOPPED (),
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.PWRDWN (1'b0),
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.RST (mmcm_rst));
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BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
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BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
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BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
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BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
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end
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endgenerate
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endmodule
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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