From f0e8b7adec97aa46d060660f6dd62acbdc2de43b Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 10 Apr 2017 19:30:57 +0200 Subject: [PATCH] axi_adc_trigger: Reduce AXI address width The axi_adc_trigger does not use the full width of the AXI interface address. It only responds to register access in the first 32 registers. Reduce the size of the AXI address to 7 bit accordingly. This allows the scripts to correctly infer the internal register map size which will cause the interconnect to filter out access to these unused register. This slightly reduces utilization by getting rid of some pipeline registers. Signed-off-by: Lars-Peter Clausen --- library/axi_adc_trigger/axi_adc_trigger.v | 13 +++--- library/axi_adc_trigger/axi_adc_trigger_reg.v | 45 +++++++++---------- 2 files changed, 28 insertions(+), 30 deletions(-) diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v index 2614a4051..02f32b050 100644 --- a/library/axi_adc_trigger/axi_adc_trigger.v +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -62,7 +62,7 @@ module axi_adc_trigger( input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, - input [31:0] s_axi_awaddr, + input [ 6:0] s_axi_awaddr, input [ 2:0] s_axi_awprot, output s_axi_awready, input s_axi_wvalid, @@ -73,7 +73,7 @@ module axi_adc_trigger( output [ 1:0] s_axi_bresp, input s_axi_bready, input s_axi_arvalid, - input [31:0] s_axi_araddr, + input [ 6:0] s_axi_araddr, input [ 2:0] s_axi_arprot, output s_axi_arready, output s_axi_rvalid, @@ -85,14 +85,14 @@ module axi_adc_trigger( wire up_clk; wire up_rstn; - wire [13:0] up_waddr; + wire [ 4:0] up_waddr; wire [31:0] up_wdata; wire up_wack; wire up_wreq; wire up_rack; wire [31:0] up_rdata; wire up_rreq; - wire [13:0] up_raddr; + wire [ 4:0] up_raddr; wire [ 1:0] io_selection; @@ -379,7 +379,10 @@ module axi_adc_trigger( .up_rdata(up_rdata), .up_rack(up_rack)); - up_axi i_up_axi ( + up_axi #( + .AXI_ADDRESS_WIDTH(7), + .ADDRESS_WIDTH(5) + ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v index f26e4af39..ddb2bd092 100644 --- a/library/axi_adc_trigger/axi_adc_trigger_reg.v +++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v @@ -69,18 +69,16 @@ module axi_adc_trigger_reg ( input up_rstn, input up_clk, input up_wreq, - input [13:0] up_waddr, + input [ 4:0] up_waddr, input [31:0] up_wdata, output reg up_wack, input up_rreq, - input [13:0] up_raddr, + input [ 4:0] up_raddr, output reg [31:0] up_rdata, output reg up_rack); // internal signals - wire up_wreq_s; - wire up_rreq_s; wire [ 9:0] config_trigger; // internal registers @@ -100,9 +98,6 @@ module axi_adc_trigger_reg ( reg [31:0] up_delay_trigger= 32'h0; reg up_triggered = 1'h0; - assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; - assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0; - assign low_level = config_trigger[1:0]; assign high_level = config_trigger[3:2]; assign any_edge = config_trigger[5:4]; @@ -128,52 +123,52 @@ module axi_adc_trigger_reg ( up_trigger_out_mix <= 'd0; up_triggered <= 1'd0; end else begin - up_wack <= up_wreq_s; - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin up_scratch <= up_wdata; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin trigger_o <= up_wdata[1:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin io_selection <= up_wdata[1:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin up_config_trigger <= up_wdata[9:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin up_limit_a <= up_wdata[15:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin up_function_a <= up_wdata[1:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin up_hysteresis_a <= up_wdata; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin up_trigger_l_mix_a <= up_wdata[3:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin up_limit_b <= up_wdata[15:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin up_function_b <= up_wdata[1:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin up_hysteresis_b <= up_wdata; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin up_trigger_l_mix_b <= up_wdata[3:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin up_trigger_out_mix <= up_wdata[2:0]; end - if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin up_delay_trigger <= up_wdata; end // if (triggered == 1'b1) begin // up_triggered <= 1'b1; -// end else if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hf)) begin +// end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin // up_triggered <= up_wdata[0]; // end end @@ -186,8 +181,8 @@ module axi_adc_trigger_reg ( up_rack <= 'd0; up_rdata <= 'd0; end else begin - up_rack <= up_rreq_s; - if (up_rreq_s == 1'b1) begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin case (up_raddr[4:0]) 5'h0: up_rdata <= up_version; 5'h1: up_rdata <= up_scratch;