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axi_hdmi_tx: Remove hdmi_full_range register

main
AndreiGrozav 2016-05-27 14:04:40 +03:00
parent 9c6e80fca2
commit f10c1e6e93
3 changed files with 1 additions and 13 deletions
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3
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -187,7 +187,6 @@ module axi_hdmi_tx (
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire hdmi_full_range_s;
wire hdmi_csc_bypass_s;
wire hdmi_ss_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
@ -258,7 +257,6 @@ module axi_hdmi_tx (
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
@ -346,7 +344,6 @@ module axi_hdmi_tx (
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),

2
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -83,7 +83,6 @@ module axi_hdmi_tx_core (
// processor interface
hdmi_full_range,
hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel,
@ -151,7 +150,6 @@ module axi_hdmi_tx_core (
// processor interface
input hdmi_full_range;
input hdmi_csc_bypass;
input hdmi_ss_bypass;
input [ 1:0] hdmi_srcsel;

9
library/common/up_hdmi_tx.v
View File

@ -43,7 +43,6 @@ module up_hdmi_tx (
hdmi_clk,
hdmi_rst,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel,
@ -94,7 +93,6 @@ module up_hdmi_tx (
input hdmi_clk;
output hdmi_rst;
output hdmi_full_range;
output hdmi_csc_bypass;
output hdmi_ss_bypass;
output [ 1:0] hdmi_srcsel;
@ -142,7 +140,6 @@ module up_hdmi_tx (
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_full_range = 'd0;
reg up_csc_bypass = 'd0;
reg up_ss_bypass = 'd0;
reg [ 1:0] up_srcsel = 'd1;
@ -190,7 +187,6 @@ module up_hdmi_tx (
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_full_range <= 'd0;
up_csc_bypass <= 'd0;
up_ss_bypass <= 'd0;
up_srcsel <= 'd1;
@ -222,7 +218,6 @@ module up_hdmi_tx (
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_ss_bypass <= up_wdata[2];
up_full_range <= up_wdata[1];
up_csc_bypass <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin
@ -296,7 +291,7 @@ module up_hdmi_tx (
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'd0, up_resetn};
12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass};
12'h011: up_rdata <= {29'd0, up_ss_bypass, 1'b0, up_csc_bypass};
12'h012: up_rdata <= {30'd0, up_srcsel};
12'h013: up_rdata <= {8'd0, up_const_rgb};
12'h015: up_rdata <= up_hdmi_clk_count_s;
@ -332,7 +327,6 @@ module up_hdmi_tx (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_ss_bypass,
up_full_range,
up_csc_bypass,
up_srcsel,
up_const_rgb,
@ -352,7 +346,6 @@ module up_hdmi_tx (
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_ss_bypass,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_srcsel,
hdmi_const_rgb,