From f1403aa593e3b5eef3091a487038ea89e0e9e015 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 25 Mar 2019 06:42:55 +0000 Subject: [PATCH] axi_pulse_gen: Update constraint file - add missing false paths - change the bus skew constraint to a false path, for some reason the tool does not change the path's requirement after a set_bus_skew constraint --- .../axi_pulse_gen/axi_pulse_gen_constr.ttcl | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/library/axi_pulse_gen/axi_pulse_gen_constr.ttcl b/library/axi_pulse_gen/axi_pulse_gen_constr.ttcl index 79f32ef7c..9844b3efe 100644 --- a/library/axi_pulse_gen/axi_pulse_gen_constr.ttcl +++ b/library/axi_pulse_gen/axi_pulse_gen_constr.ttcl @@ -12,25 +12,31 @@ set_property ASYNC_REG TRUE \ [get_cells -hier {*cdc_sync_stage1_reg*}] \ [get_cells -hier {*cdc_sync_stage2_reg*}] - ## it is constrained to a 250MHz external clock, it can be relaxed if required - ## max skew must be num_of_synchronization_stages x destination_clock_period_ns - set_bus_skew -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/cdc_hold_reg*}] \ - -to [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_data_reg*}] \ - 8 - set_bus_skew -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/cdc_hold_reg*}] \ - -to [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_data_reg*}] \ - 8 + set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_data_reg*}] \ + + set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_data_reg*}] \ set_false_path \ -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_toggle_d1_reg/C}] \ -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] set_false_path \ -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_toggle_d1_reg/C}] \ -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] set_false_path \ -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/out_toggle_d1_reg/C}] \ -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] <: } :>