library- add a timer for quick start
parent
fd8b524953
commit
f19b8c62a1
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@ -138,6 +138,7 @@ module up_adc_common #(
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reg [ 7:0] up_usr_chanmax_int = 'd0;
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reg [31:0] up_adc_start_code = 'd0;
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reg [31:0] up_adc_gpio_out_int = 'd0;
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reg [31:0] up_timer = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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@ -340,6 +341,20 @@ module up_adc_common #(
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end
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endgenerate
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// timer with premature termination
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_timer <= 32'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
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up_timer <= up_wdata;
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end else if (up_timer > 0) begin
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up_timer <= up_timer - 1'b1;
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end
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end
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end
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// processor read interface
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assign up_rack = up_rack_int;
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@ -377,6 +392,7 @@ module up_adc_common #(
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8'h2f: up_rdata_int <= up_adc_gpio_out_int;
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8'h30: up_rdata_int <= up_pps_rcounter;
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8'h31: up_rdata_int <= {31'b0, up_pps_status};
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8'h40: up_rdata_int <= up_timer;
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default: up_rdata_int <= 0;
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endcase
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end else begin
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@ -134,6 +134,7 @@ module up_dac_common #(
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reg up_status_unf = 'd0;
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reg [ 7:0] up_usr_chanmax_int = 'd0;
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reg [31:0] up_dac_gpio_out_int = 'd0;
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reg [31:0] up_timer = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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reg dac_sync_d = 'd0;
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@ -343,6 +344,20 @@ module up_dac_common #(
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end
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endgenerate
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// timer with premature termination
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_timer <= 32'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
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up_timer <= up_wdata;
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end else if (up_timer > 0) begin
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up_timer <= up_timer - 1'b1;
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end
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end
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end
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// processor read interface
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assign up_rack = up_rack_int;
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@ -380,6 +395,7 @@ module up_dac_common #(
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8'h2f: up_rdata_int <= up_dac_gpio_out_int;
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8'h30: up_rdata_int <= up_pps_rcounter;
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8'h31: up_rdata_int <= up_pps_status;
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8'h40: up_rdata_int <= up_timer;
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default: up_rdata_int <= 0;
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endcase
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end else begin
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