library/common- reset fix
parent
32b3cfd8b9
commit
f1ed27105f
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@ -768,7 +768,7 @@ module up_gt_channel (
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// rx sysref & sync
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always @(posedge rx_clk) begin
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always @(posedge rx_clk or posedge rx_rst_m) begin
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if (rx_rst_m == 1'b1) begin
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rx_sysref_sel_m1 <= 'd0;
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rx_sysref_sel <= 'd0;
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@ -796,7 +796,7 @@ module up_gt_channel (
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// tx sysref & sync
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always @(posedge tx_clk) begin
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always @(posedge tx_clk or posedge tx_rst_m) begin
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if (tx_rst_m == 1'b1) begin
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tx_sysref_sel_m1 <= 'd0;
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tx_sysref_sel <= 'd0;
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