zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad7616_sdz: Remove zc706 support

main
Stanca Pop 2023-10-25 10:59:31 +03:00 committed by StancaPop
parent 3446cc2100
commit f1f3968485
7 changed files with 0 additions and 531 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
projects/ad7616_sdz/zc706/Makefile
View File

@ -1,33 +0,0 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7616_sdz_zc706
M_DEPS += serial_if_constr.xdc
M_DEPS += parallel_if_constr.xdc
M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v
LIB_DEPS += axi_ad7616
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_pwm_gen
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += sysid_rom
include ../../scripts/project-xilinx.mk

39
projects/ad7616_sdz/zc706/parallel_if_constr.xdc
View File

@ -1,39 +0,0 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7616
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS25} [get_ports adc_db[0] ] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports adc_db[1] ] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25} [get_ports adc_db[2] ] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports adc_db[3] ] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports adc_db[4] ] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_db[5] ] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports adc_db[6] ] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports adc_db[7] ] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports adc_db[8] ] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports adc_db[9] ] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports adc_db[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports adc_db[11]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports adc_db[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_db[13]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_db[14]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_db[15]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports adc_rd_n] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_n] ; ## FMC_LPC_LA09_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports adc_cs_n] ; ## FMC_LPC_LA04_N

33
projects/ad7616_sdz/zc706/serial_if_constr.xdc
View File

@ -1,33 +0,0 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# ad7616
# data interface
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs_n] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[0]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports adc_hw_rngsel[1]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports adc_busy] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports adc_seq_en] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports adc_reset_n] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS25} [get_ports adc_os[0]] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS25} [get_ports adc_os[1]] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports adc_os[2]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_burst] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports adc_crcen] ; ## FMC_LPC_LA02_N

26
projects/ad7616_sdz/zc706/system_bd.tcl
View File

@ -1,26 +0,0 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
# system level parameters
set SER_PAR_N $ad_project_params(SER_PAR_N)
adi_project_files ad7616_sdz_zc706 [list \
"../../../library/common/ad_edge_detect.v" \
"../../../library/util_cdc/sync_bits.v"]
source ../common/ad7616_bd.tcl

63
projects/ad7616_sdz/zc706/system_project.tcl
View File

@ -1,63 +0,0 @@
###############################################################################
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
##--------------------------------------------------------------
# IMPORTANT: Set AD7616 operation and interface mode
#
# The get_env_param procedure retrieves parameter value from the environment if exists,
# other case returns the default value specified in its second parameter field.
#
# How to use over-writable parameters from the environment:
#
# e.g.
# make SER_PAR_N=1
#
# SER_PAR_N - Defines the interface type (serial OR parallel)
# - Default value is 1
#
# LEGEND: Serial - 1
# Parallel - 0
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
# SL5 - mounted - Serial
# SL5 - unmounted - Parallel
#
##--------------------------------------------------------------
if {[info exists ::env(SER_PAR_N)]} {
set S_SER_PAR_N [get_env_param SER_PAR_N 0]
} elseif {![info exists SER_PAR_N]} {
set S_SER_PAR_N 1
}
adi_project ad7616_sdz_zc706 0 [list \
SER_PAR_N $S_SER_PAR_N \
]
adi_project_files ad7616_sdz_zc706 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
switch $S_SER_PAR_N {
1 {
adi_project_files ad7616_sdz_zc706 [list \
"system_top_si.v" \
"serial_if_constr.xdc"
]
}
0 {
adi_project_files ad7616_sdz_zc706 [list \
"system_top_pi.v" \
"parallel_if_constr.xdc"
]
}
}
adi_project_run ad7616_sdz_zc706

173
projects/ad7616_sdz/zc706/system_top_pi.v
View File

@ -1,173 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
inout [15:0] adc_db,
output adc_rd_n,
output adc_wr_n,
output adc_cs_n,
output adc_reset_n,
output adc_cnvst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire adc_db_t;
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
// instantiations
ad_iobuf #(
.DATA_WIDTH(7)
) i_iobuf_adc_cntrl (
.dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_seq_en, // 37
adc_chsel})); // 35:33
assign gpio_i[63:44] = gpio_o[63:44];
assign gpio_i[32] = gpio_o[32];
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[15:0]),
.dio_o(adc_db_i[15:0]),
.dio_p(adc_db[15:0]));
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.rx_cnvst (adc_cnvst),
.rx_cs_n (adc_cs_n),
.rx_busy (adc_busy),
.rx_db_o (adc_db_o),
.rx_db_i (adc_db_i),
.rx_db_t (adc_db_t),
.rx_rd_n (adc_rd_n),
.rx_wr_n (adc_wr_n));
endmodule

164
projects/ad7616_sdz/zc706/system_top_si.v
View File

@ -1,164 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
output ad7616_spi_sclk,
output ad7616_spi_sdo,
input [ 1:0] ad7616_spi_sdi,
output ad7616_spi_cs_n,
output adc_reset_n,
output adc_cnvst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel,
output adc_crcen,
output adc_burst,
output [ 2:0] adc_os
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
.dio_p ({adc_reset_n, // 43
adc_hw_rngsel, // 42:41
adc_os, // 40:38
adc_seq_en, // 37
adc_burst, // 36
adc_chsel, // 35:33
adc_crcen})); // 32
assign gpio_i[63:44] = gpio_o[63:44];
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.ad7616_spi_sdo (ad7616_spi_sdo),
.ad7616_spi_sdi (ad7616_spi_sdi),
.ad7616_spi_cs (ad7616_spi_cs),
.ad7616_spi_sclk (ad7616_spi_sclk),
.rx_cnvst (adc_cnvst),
.rx_busy (adc_busy));
endmodule