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ad9361/xilinx/lvds_if- fix frame check

main
Rejeesh Kutty 2017-07-25 16:37:01 -04:00
parent 704512f0d4
commit f26c1de38a
1 changed files with 6 additions and 3 deletions
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9
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
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@ -170,6 +170,7 @@ module axi_ad9361_lvds_if #(
// internal signals
wire [ 3:0] rx_frame_d_s;
wire [ 5:0] rx_data_1_s;
wire [ 5:0] rx_data_0_s;
wire [ 1:0] rx_frame_s;
@ -211,12 +212,14 @@ module axi_ad9361_lvds_if #(
// frame check
assign rx_frame_d_s = {rx_frame_s, rx_frame};
always @(posedge l_clk) begin
if (rx_valid == 1'd1) begin
if (rx_r1_mode == 1'd1) begin
rx_frame_d <= {rx_frame_s, rx_frame};
rx_frame_d <= rx_frame_d_s;
end else begin
rx_frame_d <= {~rx_frame_s, ~rx_frame};
rx_frame_d <= ~rx_frame_d_s;
end
end
end
@ -323,7 +326,7 @@ module axi_ad9361_lvds_if #(
always @(posedge l_clk) begin
if (rx_valid == 1'b1) begin
if (rx_frame_d == rx_frame_s) begin
if (rx_frame_d == rx_frame_d_s) begin
adc_status_p <= rx_locked;
end else begin
adc_status_p <= 1'b0;