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spi_engine: Revert Offload AXI signals, ctrl fixup (#1288) 

Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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Jorge Marques 2024-03-14 11:45:33 -03:00 committed by GitHub
parent a9e0836a77
commit f2a00c8528
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2 changed files with 7 additions and 7 deletions
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8
library/spi_engine/interfaces/interfaces_ip.tcl
View File

@ -22,11 +22,11 @@ adi_if_define "spi_engine_ctrl"
adi_if_ports input 1 cmd_ready adi_if_ports input 1 cmd_ready
adi_if_ports output 1 cmd_valid adi_if_ports output 1 cmd_valid
adi_if_ports output 16 cmd_data adi_if_ports output 16 cmd_data
adi_if_ports input 1 sdo_data_ready adi_if_ports input 1 sdo_ready
adi_if_ports output 1 sdo_data_valid adi_if_ports output 1 sdo_valid
adi_if_ports output -1 sdo_data adi_if_ports output -1 sdo_data
adi_if_ports output 1 sdi_data_ready adi_if_ports output 1 sdi_ready
adi_if_ports input 1 sdi_data_valid adi_if_ports input 1 sdi_valid
adi_if_ports input -1 sdi_data adi_if_ports input -1 sdi_data
adi_if_ports output 1 sync_ready adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid adi_if_ports input 1 sync_valid

6
library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
View File

@ -66,9 +66,9 @@ adi_add_bus "offload_sdi" "master" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \
{ \ { \
{"offload_sdi_valid" "tvalid"} \ {"offload_sdi_valid" "TVALID"} \
{"offload_sdi_ready" "tready"} \ {"offload_sdi_ready" "TREADY"} \
{"offload_sdi_data" "tdata"} \ {"offload_sdi_data" "TDATA"} \
} }
adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn" adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn"