diff --git a/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl b/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl index 20dcc024c..61a968ba6 100644 --- a/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl +++ b/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl @@ -175,9 +175,9 @@ connect_bd_net -net axi_ad9625_gt_rx_ip_sof [get_bd_pins axi_ad9625_gt/r connect_bd_net -net axi_ad9625_gt_rx_ip_data [get_bd_pins axi_ad9625_gt/rx_ip_data] [get_bd_pins axi_ad9625_jesd/rx_tdata] connect_bd_net -net axi_ad9625_gt_rx_data [get_bd_pins axi_ad9625_gt/rx_data] [get_bd_pins axi_ad9625_core/rx_data] connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9625_adc_dwr [get_bd_pins axi_ad9625_core/adc_dwr] [get_bd_pins axi_ad9625_dma/fifo_wr_en] -connect_bd_net -net axi_ad9625_adc_dsync [get_bd_pins axi_ad9625_core/adc_dsync] [get_bd_pins axi_ad9625_dma/fifo_wr_sync] -connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins axi_ad9625_core/adc_ddata] [get_bd_pins axi_ad9625_dma/fifo_wr_din] +connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins axi_ad9625_dma/fifo_wr_en] +connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_valid] [get_bd_pins axi_ad9625_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins axi_ad9625_dma/fifo_wr_din] connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow] connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2] @@ -290,7 +290,7 @@ connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins ila_jesd_rx_mon connect_bd_net -net axi_ad9625_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] connect_bd_net -net axi_ad9625_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] connect_bd_net -net axi_ad9625_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] -connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] +connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3] # address map diff --git a/projects/ad9625_fmc/zc706/system_bd.tcl b/projects/ad9625_fmc/zc706/system_bd.tcl index 354e41478..f6cc0dc95 100644 --- a/projects/ad9625_fmc/zc706/system_bd.tcl +++ b/projects/ad9625_fmc/zc706/system_bd.tcl @@ -15,27 +15,27 @@ connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_p connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] delete_bd_objs [get_bd_nets axi_ad9625_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9625_adc_dwr] -delete_bd_objs [get_bd_nets axi_ad9625_adc_ddata] +delete_bd_objs [get_bd_nets axi_ad9625_adc_enable] +delete_bd_objs [get_bd_nets axi_ad9625_adc_data] delete_bd_objs [get_bd_nets axi_ad9625_adc_dovf] -delete_bd_objs [get_bd_nets axi_ad9625_adc_dsync] +delete_bd_objs [get_bd_nets axi_ad9625_adc_valid] connect_bd_net -net [get_bd_nets axi_ad9625_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_ad9625_gt/rx_rst] connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_ps7/FCLK_RESET2_N] +connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] -connect_bd_net -net axi_ad9625_adc_dwr [get_bd_pins axi_ad9625_core/adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] -connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins axi_ad9625_core/adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] +connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins plddr3_fifo/adc_wr] +connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins plddr3_fifo/adc_wdata] connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] -connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins plddr3_fifo/axi_xfer_req] connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk] connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en] connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din] connect_bd_net -net axi_ad9625_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9625_adc_dsync [get_bd_pins axi_ad9625_core/adc_dsync] [get_bd_pins axi_ad9625_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_valid] [get_bd_pins axi_ad9625_dma/fifo_wr_sync] -connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] +connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3] set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon] set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon @@ -46,7 +46,7 @@ set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins ila_dma_mon/clk] connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins ila_dma_mon/probe1] +connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2] connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 48fe2ed88..d7f93512c 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -31,6 +31,33 @@ if {$sys_zynq == 0} { set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] } + set dac_clk [create_bd_port -dir O dac_clk] + set dac_valid_0 [create_bd_port -dir O dac_valid_0] + set dac_enable_0 [create_bd_port -dir O dac_enable_0] + set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] + set dac_valid_1 [create_bd_port -dir O dac_valid_1] + set dac_enable_1 [create_bd_port -dir O dac_enable_1] + set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] + set dac_valid_2 [create_bd_port -dir O dac_valid_2] + set dac_enable_2 [create_bd_port -dir O dac_enable_2] + set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] + set dac_valid_3 [create_bd_port -dir O dac_valid_3] + set dac_enable_3 [create_bd_port -dir O dac_enable_3] + set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] + set dac_drd [create_bd_port -dir I dac_drd] + set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] + + set adc_clk [create_bd_port -dir O adc_clk] + set adc_enable_0 [create_bd_port -dir O adc_enable_0] + set adc_valid_0 [create_bd_port -dir O adc_valid_0] + set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] + set adc_enable_1 [create_bd_port -dir O adc_enable_1] + set adc_valid_1 [create_bd_port -dir O adc_valid_1] + set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] + set adc_dwr [create_bd_port -dir I adc_dwr] + set adc_dsync [create_bd_port -dir I adc_dsync] + set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] + # dac peripherals set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] @@ -50,11 +77,7 @@ if {$sys_zynq == 0} { set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma -if {$sys_zynq == 1} { - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma -} else { set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma -} set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma if {$sys_zynq == 1} { @@ -83,11 +106,7 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma -if {$sys_zynq == 1} { - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma -} else { set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma -} if {$sys_zynq == 1} { @@ -233,8 +252,20 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] - connect_bd_net -net axi_ad9144_dac_drd [get_bd_pins axi_ad9144_core/dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] - connect_bd_net -net axi_ad9144_dac_ddata [get_bd_pins axi_ad9144_core/dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] + connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] + connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] + connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] + connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] + connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] + connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] + connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] + connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] + connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] + connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] + connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] + connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] + connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] + connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] @@ -258,12 +289,23 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] - connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core/adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] - connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] + connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] + connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] + connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] + connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] + connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] + connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] + connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + # dac/adc clocks + + connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] + # interconnect (cpu) connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi]