From f2d2092297071bb2bb097857b6b5f5a222319403 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 31 Jul 2019 09:41:50 +0100 Subject: [PATCH] axi_dacfifo: Add don't touch for the constraints to apply --- library/xilinx/axi_dacfifo/axi_dacfifo_rd.v | 4 ++-- library/xilinx/axi_dacfifo/axi_dacfifo_wr.v | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v index b50ae0673..141642534 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v @@ -108,9 +108,9 @@ module axi_dacfifo_rd #( reg axi_data_req = 1'b0; reg [ 4:0] axi_read_state = 5'b0; reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0; - reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0; + (* dont_touch = "true" *) reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0; - reg axi_mem_laddr_toggle = 1'b0; + (* dont_touch = "true" *) reg axi_mem_laddr_toggle = 1'b0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0; diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v index 04e2b1108..339e4440b 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v @@ -57,7 +57,7 @@ module axi_dacfifo_wr #( input dma_xfer_req, input dma_xfer_last, - output reg [ 3:0] dma_last_beats, + (* dont_touch = "true" *) output reg [ 3:0] dma_last_beats, // last address for read side