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axi_dacfifo: Add don't touch for the constraints to apply

main
Adrian Costina 2019-07-31 09:41:50 +01:00
parent c3739b1f30
commit f2d2092297
2 changed files with 3 additions and 3 deletions
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4
library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
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@ -108,9 +108,9 @@ module axi_dacfifo_rd #(
reg axi_data_req = 1'b0; reg axi_data_req = 1'b0;
reg [ 4:0] axi_read_state = 5'b0; reg [ 4:0] axi_read_state = 5'b0;
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0; reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0; (* dont_touch = "true" *) reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0;
reg axi_mem_laddr_toggle = 1'b0; (* dont_touch = "true" *) reg axi_mem_laddr_toggle = 1'b0;
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0;
reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0; reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0;

2
library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
View File

@ -57,7 +57,7 @@ module axi_dacfifo_wr #(
input dma_xfer_req, input dma_xfer_req,
input dma_xfer_last, input dma_xfer_last,
output reg [ 3:0] dma_last_beats, (* dont_touch = "true" *) output reg [ 3:0] dma_last_beats,
// last address for read side // last address for read side