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axi_clkgen: Propagate clock settings to output pins 

Calculate the output clock frequencies based on the input clock frequencies
and the default divider settings and configure the output clock pins
accordingly. This allows connected peripherals to infer the frequency of
the clock.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-20 20:25:17 +02:00
parent af913863d4
commit f319d1b5d4
1 changed files with 45 additions and 0 deletions
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45
library/axi_clkgen/bd/bd.tcl
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@ -20,6 +20,51 @@ proc axi_clkgen_get_infer_period {ip param clk_name} {
} }
} }
proc propagate {cellpath otherinfo} {
set ip [get_bd_cells $cellpath]
set vco_mul [get_property CONFIG.VCO_MUL $ip]
set vco_div [get_property CONFIG.VCO_DIV $ip]
set clk0_div [get_property CONFIG.CLK0_DIV $ip]
set clk1_div [get_property CONFIG.CLK1_DIV $ip]
if {$vco_mul == {} || $vco_mul < 1} {
set vco_mul 1
}
if {$vco_div == {} || $vco_div < 1} {
set vco_div 1
}
if {$clk0_div == {} || $clk0_div < 1} {
set clk0_div 1
}
if {$clk1_div == {} || $clk0_div < 1} {
set clk1_div 1
}
set clk [get_bd_pins "$ip/clk"]
set clk_freq [get_property CONFIG.FREQ_HZ $clk]
if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} {
set clk2 [get_bd_pins "$ip/clk"]
set clk2_freq [get_property CONFIG.FREQ_HZ $clk2]
# Use the larger of the two
if {$clk_freq == {} || $clk2_freq > $clk_freq} {
set clk_freq $clk2_freq
}
}
if {$clk_freq != {}} {
set clk0_out [get_bd_pins "$ip/clk_0"]
set clk0_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk0_div)]
set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out
if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} {
set clk0_out [get_bd_pins "$ip/clk_1"]
set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)]
set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out
}
}
}
proc post_propagate {cellpath otherinfo} { proc post_propagate {cellpath otherinfo} {
set ip [get_bd_cells $cellpath] set ip [get_bd_cells $cellpath]